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0001 mcf548x
0002 =======
0003 Copyright (c) 2007 embedded brains GmbH & Co. KG
0004
0005 Parts of the code has been derived from the "dBUG source code"
0006 package Freescale is providing for M548X EVBs. The usage of
0007 the modified or unmodified code and it's integration into the
0008 generic mcf548x BSP has been done according to the Freescale
0009 license terms.
0010
0011 The Freescale license terms can be reviewed in the file
0012
0013 LICENSE.Freescale
0014
0015 The generic mcf548x BSP has been developed on the basic
0016 structures and modules of the av5282 BSP.
0017
0018 The license and distribution terms for this file may be
0019 found in the file LICENSE in this distribution or at
0020 http://www.rtems.org/license/LICENSE.
0021
0022
0023 Description: Generic mcf548x BSP
0024
0025 The genmcf548x supports several boards based on the Freescale MCF547x/8x
0026 ColdFire microcontrollers
0027
0028
0029 Supported Hardware: mcf5484FireEngine
0030 -----------------------------
0031 ```
0032 CPU: MCF548x, 200MHz
0033 XLB: 100 MHz, which is the main clock for all onchip peripherals
0034 RAM: 64M (m5484FireEngine)
0035 Boot-Flash: 2M (m5484FireEngine)
0036 Code-Flash: 16M (m5484FireEngine)
0037 Core-SRAM: 8K
0038 Core-SysRAM: 32K
0039 Boot-Monitor:None
0040 ```
0041
0042
0043 Supported Hardware: COBRA5475
0044 -----------------------------
0045 ```
0046 CPU: MCF5475, 266MHz
0047 XLB: 132 MHz, which is the main clock for all onchip peripherals
0048 RAM: 128M
0049 Boot-Flash: 32M
0050 Core-SRAM: 8K
0051 Core-SysRAM: 32K
0052 Boot-Monitor:DBug
0053 ```
0054
0055 ACKNOWLEDGEMENTS:
0056 -----------------
0057 This BSP is based on the
0058
0059 av5282 BSP
0060
0061 and the work of
0062
0063 D. Peter Siddons
0064 Brett Swimley
0065 Jay Monkman
0066 Eric Norum
0067 Mike Bertosh
0068
0069
0070 BSP INFO:
0071 ---------
0072 ```
0073 BSP NAME: genmcf548x
0074 BOARD: various MCF547x/8x based boards
0075 CPU FAMILY: ColdFire 548x
0076 CPU: MCF5475/MCF5484
0077 FPU: MCF548x FPU, context switch supported by RTEMS multitasking
0078 EMAC: MCF548x EMAC context switch supported by RTEMS multitasking (handeld together with FPU context)
0079 ```
0080
0081
0082 PERIPHERALS
0083 -----------
0084 ```
0085 TIMERS: 2 slice timers, 4 general purpose timers (SLT0 is used for RTEMS clock, SLT1 is used for diagnostic pupose)
0086 RESOLUTION: System tick 10 millieconds (via SLT0)
0087 SERIAL PORTS: Internal PSC 0-3
0088 NETWORKING: Internal 10/100MHz FEC on two channels
0089 ```
0090
0091
0092 DRIVER INFORMATION
0093 ------------------
0094 ```
0095 CLOCK DRIVER: SLT0
0096 TIMER DRIVER: SLT1 (diagnostics)
0097 TTY DRIVER: PSC0-3
0098 ```
0099
0100
0101 STDIO
0102 -----
0103 ```
0104 PORT: PSC0 (UART mode) terminal
0105 ELECTRICAL: RS-232
0106 BAUD: 9600
0107 BITS PER CHARACTER: 8
0108 PARITY: None
0109 STOP BITS: 1
0110 MODES: Interrupt driven (polled mode alternatively)
0111 ```
0112
0113
0114 Memory map
0115 ==========
0116 ```
0117 Memory map of m5484FireEngine as set up by BSP initialization:
0118
0119 +--------------------------------------------------+
0120 0000 0000 | 64 MByte SDRAM (external) | 03FF FFFF
0121 . .
0122 . .
0123 . .
0124
0125
0126 m5484FireEngine:
0127
0128
0129 | | 0FFF FFFF
0130 +--------------------------------------------------+
0131 1000 0000 | internal per. registers via MBAR | 1003 FFFF
0132 . .
0133 . .
0134 . .
0135 | |
0136 +--------------------------------------------------+
0137 2000 0000 | 8K core SRAM (internal) | 2000 1FFF
0138 . .
0139 . .
0140 . .
0141
0142 m5484FireEngine:
0143
0144 | |
0145 +--------------------------------------------------+
0146 E000 0000 | 16M code flash (external) | E0FF FFFF
0147 . .
0148 . .
0149 . .
0150 | |
0151 +--------------------------------------------------+
0152 FF80 0000 | External 8 MByte Flash memory | FF9F FFFF
0153 . .
0154 . .
0155 . .
0156 | | FFFF FFFF
0157 +--------------------------------------------------+
0158 ```
0159
0160 ```
0161 Memory map for COBRA5475 as set up by DBug:
0162
0163 +--------------------------------------------------+
0164 F000 0000 | 128 MByte SDRAM (external) |
0165 . .
0166 . (first 256KByte reserved for DBug) .
0167 . . F03F FFFF
0168 F040 0000 | |
0169 . .
0170 . .
0171 . .
0172 | | F7FF FFFF
0173 +--------------------------------------------------+
0174 FC00 0000 | 32M code flash (external) |
0175 . .
0176 . .
0177 . .
0178 | | FDFF FFFF
0179 +--------------------------------------------------+
0180 FE00 0000 | internal per. registers via MBAR |
0181 . .
0182 . .
0183 . .
0184 | | FE03 FFFF
0185 +--------------------------------------------------+
0186 FF00 0000 | 8K core SRAM (internal) |
0187 . .
0188 . .
0189 . .
0190 | | FF00 1FFF
0191 +--------------------------------------------------+
0192 ```
0193
0194
0195 Interrupt map
0196 =============
0197 ```
0198 +-----+-----------------------------------------------------------------------+
0199 | | PRIORITY |
0200 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0201 |LEVEL| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0202 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0203 | 7 | | | | | | | | |
0204 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0205 | 6 | | | | | | | | |
0206 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0207 | 5 | | | | | | | | |
0208 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0209 | 4 | | | | | | | | SLT0 |
0210 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0211 | 3 | PSC 0 | PSC 1 | PSC 2 | PSC 3 | | | | |
0212 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0213 | 2 | | | | | FEC0/1 | MCDMA | | |
0214 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0215 | 1 | | | | | | | | |
0216 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0217 ```
0218
0219
0220 TIMING TESTS
0221 ------------
0222
0223 tbd.
