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0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002 
0003 /*
0004  *  This file contains the entry point for the application.
0005  *  The name of this entry point is compiler dependent.
0006  *  It jumps to the BSP which is responsible for performing
0007  *  all initialization.
0008  */
0009 
0010 /*
0011  *  COPYRIGHT (c) 1989-1999.
0012  *  On-Line Applications Research Corporation (OAR).
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  *
0035  * Based on the `gen68360' board support package, and covered by the
0036  * original distribution terms.
0037  *
0038  * Geoffroy Montel
0039  * France Telecom - CNET/DSM/TAM/CAT
0040  * 4, rue du Clos Courtel
0041  * 35512 CESSON-SEVIGNE
0042  * FRANCE
0043  *
0044  * e-mail: g_montel@yahoo.com
0045  */
0046 
0047 #include <rtems/asm.h>
0048 #include <m68349.inc>
0049 
0050 #include <bsp.h> /* to indicate dependencies */
0051 
0052 /* old addresses for AST68340 only, undefine for AST68349 */
0053 #define _OLD_ASTECC 1
0054 
0055 BEGIN_CODE
0056     /*
0057      * Step 1: Decide on Reset Stack Pointer and Initial Program Counter
0058      */
0059 Entry:
0060     .long   SYM(m340)+1024      |   0: Initial SSP
0061     .long   start           |   1: Initial PC
0062     .long   SYM(_uhoh)      |   2: Bus error
0063     .long   SYM(_uhoh)      |   3: Address error
0064     .long   SYM(_uhoh)      |   4: Illegal instruction
0065     .long   SYM(_uhoh)      |   5: Zero division
0066     .long   SYM(_uhoh)      |   6: CHK, CHK2 instruction
0067     .long   SYM(_uhoh)      |   7: TRAPcc, TRAPV instructions
0068     .long   SYM(_uhoh)      |   8: Privilege violation
0069     .long   SYM(_uhoh)      |   9: Trace
0070     .long   SYM(_uhoh)      |  10: Line 1010 emulator
0071     .long   SYM(_uhoh)      |  11: Line 1111 emulator
0072     .long   SYM(_uhoh)      |  12: Hardware breakpoint
0073     .long   SYM(_uhoh)      |  13: Reserved for coprocessor violation
0074     .long   SYM(_uhoh)      |  14: Format error
0075     .long   SYM(_uhoh)      |  15: Uninitialized interrupt
0076     .long   SYM(_uhoh)      |  16: Unassigned, reserved
0077     .long   SYM(_uhoh)      |  17:
0078     .long   SYM(_uhoh)      |  18:
0079     .long   SYM(_uhoh)      |  19:
0080     .long   SYM(_uhoh)      |  20:
0081     .long   SYM(_uhoh)      |  21:
0082     .long   SYM(_uhoh)      |  22:
0083     .long   SYM(_uhoh)      |  23:
0084     .long   SYM(_spuriousInterrupt) |  24: Spurious interrupt
0085     .long   SYM(_uhoh)      |  25: Level 1 interrupt autovector
0086     .long   SYM(_uhoh)      |  26: Level 2 interrupt autovector
0087     .long   SYM(_uhoh)      |  27: Level 3 interrupt autovector
0088     .long   SYM(_uhoh)      |  28: Level 4 interrupt autovector
0089     .long   SYM(_uhoh)      |  29: Level 5 interrupt autovector
0090     .long   SYM(_uhoh)      |  30: Level 6 interrupt autovector
0091     .long   SYM(_uhoh)      |  31: Level 7 interrupt autovector
0092     .long   SYM(_uhoh)      |  32: Trap instruction (0-15)
0093     .long   SYM(_uhoh)      |  33:
0094     .long   SYM(_uhoh)      |  34:
0095     .long   SYM(_uhoh)      |  35:
0096     .long   SYM(_uhoh)      |  36:
0097     .long   SYM(_uhoh)      |  37:
0098     .long   SYM(_uhoh)      |  38:
0099     .long   SYM(_uhoh)      |  39:
0100     .long   SYM(_uhoh)      |  40:
0101     .long   SYM(_uhoh)      |  41:
0102     .long   SYM(_uhoh)      |  42:
0103     .long   SYM(_uhoh)      |  43:
0104     .long   SYM(_uhoh)      |  44:
0105     .long   SYM(_uhoh)      |  45:
0106     .long   SYM(_uhoh)      |  46:
0107     .long   SYM(_uhoh)      |  47:
0108     .long   SYM(_uhoh)      |  48: Reserved for coprocessor
0109     .long   SYM(_uhoh)      |  49:
0110     .long   SYM(_uhoh)      |  50:
0111     .long   SYM(_uhoh)      |  51:
0112     .long   SYM(_uhoh)      |  52:
0113     .long   SYM(_uhoh)      |  53:
0114     .long   SYM(_uhoh)      |  54:
0115     .long   SYM(_uhoh)      |  55:
0116     .long   SYM(_uhoh)      |  56:
0117     .long   SYM(_uhoh)      |  57:
0118     .long   SYM(_uhoh)      |  58:
0119     .long   SYM(_uhoh)      |  59: Unassigned, reserved
0120     .long   SYM(_uhoh)      |  60:
0121     .long   SYM(_uhoh)      |  61:
0122     .long   SYM(_uhoh)      |  62:
0123     .long   SYM(_uhoh)      |  63:
0124     .long   SYM(_uhoh)      |  64: User defined vectors (192)
0125     .long   SYM(_uhoh)      |  65:
0126     .long   SYM(_uhoh)      |  66:
0127     .long   SYM(_uhoh)      |  67:
0128     .long   SYM(_uhoh)      |  68:
0129     .long   SYM(_uhoh)      |  69:
0130     .long   SYM(_uhoh)      |  70:
0131     .long   SYM(_uhoh)      |  71:
0132     .long   SYM(_uhoh)      |  72:
0133     .long   SYM(_uhoh)      |  73:
0134     .long   SYM(_uhoh)      |  74:
0135     .long   SYM(_uhoh)      |  75:
0136     .long   SYM(_uhoh)      |  76:
0137     .long   SYM(_uhoh)      |  77:
0138     .long   SYM(_uhoh)      |  78:
0139     .long   SYM(_uhoh)      |  79:
0140     .long   SYM(_uhoh)      |  80:
0141     .long   SYM(_uhoh)      |  81:
0142     .long   SYM(_uhoh)      |  82:
0143     .long   SYM(_uhoh)      |  83:
0144     .long   SYM(_uhoh)      |  84:
0145     .long   SYM(_uhoh)      |  85:
0146     .long   SYM(_uhoh)      |  86:
0147     .long   SYM(_uhoh)      |  87:
0148     .long   SYM(_uhoh)      |  88:
0149     .long   SYM(_uhoh)      |  89:
0150     .long   SYM(_uhoh)      |  90:
0151     .long   SYM(_uhoh)      |  91:
0152     .long   SYM(_uhoh)      |  92:
0153     .long   SYM(_uhoh)      |  93:
0154     .long   SYM(_uhoh)      |  94:
0155     .long   SYM(_uhoh)      |  95:
0156     .long   SYM(_uhoh)      |  96:
0157     .long   SYM(_uhoh)      |  97:
0158     .long   SYM(_uhoh)      |  98:
0159     .long   SYM(_uhoh)      |  99:
0160     .long   SYM(_uhoh)      | 100:
0161     .long   SYM(_uhoh)      | 101:
0162     .long   SYM(_uhoh)      | 102:
0163     .long   SYM(_uhoh)      | 103:
0164     .long   SYM(_uhoh)      | 104:
0165     .long   SYM(_uhoh)      | 105:
0166     .long   SYM(_uhoh)      | 106:
0167     .long   SYM(_uhoh)      | 107:
0168     .long   SYM(_uhoh)      | 108:
0169     .long   SYM(_uhoh)      | 109:
0170     .long   SYM(_uhoh)      | 110:
0171     .long   SYM(_uhoh)      | 111:
0172     .long   SYM(_uhoh)      | 112:
0173     .long   SYM(_uhoh)      | 113:
0174     .long   SYM(_uhoh)      | 114:
0175     .long   SYM(_uhoh)      | 115:
0176     .long   SYM(_uhoh)      | 116:
0177     .long   SYM(_uhoh)      | 117:
0178     .long   SYM(_uhoh)      | 118:
0179     .long   SYM(_uhoh)      | 119:
0180     .long   SYM(_uhoh)      | 120:
0181     .long   SYM(_uhoh)      | 121:
0182     .long   SYM(_uhoh)      | 122:
0183     .long   SYM(_uhoh)      | 123:
0184     .long   SYM(_uhoh)      | 124:
0185     .long   SYM(_uhoh)      | 125:
0186     .long   SYM(_uhoh)      | 126:
0187     .long   SYM(_uhoh)      | 127:
0188     .long   SYM(_uhoh)      | 128:
0189     .long   SYM(_uhoh)      | 129:
0190     .long   SYM(_uhoh)      | 130:
0191     .long   SYM(_uhoh)      | 131:
0192     .long   SYM(_uhoh)      | 132:
0193     .long   SYM(_uhoh)      | 133:
0194     .long   SYM(_uhoh)      | 134:
0195     .long   SYM(_uhoh)      | 135:
0196     .long   SYM(_uhoh)      | 136:
0197     .long   SYM(_uhoh)      | 137:
0198     .long   SYM(_uhoh)      | 138:
0199     .long   SYM(_uhoh)      | 139:
0200     .long   SYM(_uhoh)      | 140:
0201     .long   SYM(_uhoh)      | 141:
0202     .long   SYM(_uhoh)      | 142:
0203     .long   SYM(_uhoh)      | 143:
0204     .long   SYM(_uhoh)      | 144:
0205     .long   SYM(_uhoh)      | 145:
0206     .long   SYM(_uhoh)      | 146:
0207     .long   SYM(_uhoh)      | 147:
0208     .long   SYM(_uhoh)      | 148:
0209     .long   SYM(_uhoh)      | 149:
0210     .long   SYM(_uhoh)      | 150:
0211     .long   SYM(_uhoh)      | 151:
0212     .long   SYM(_uhoh)      | 152:
0213     .long   SYM(_uhoh)      | 153:
0214     .long   SYM(_uhoh)      | 154:
0215     .long   SYM(_uhoh)      | 155:
0216     .long   SYM(_uhoh)      | 156:
0217     .long   SYM(_uhoh)      | 157:
0218     .long   SYM(_uhoh)      | 158:
0219     .long   SYM(_uhoh)      | 159:
0220     .long   SYM(_uhoh)      | 160:
0221     .long   SYM(_uhoh)      | 161:
0222     .long   SYM(_uhoh)      | 162:
0223     .long   SYM(_uhoh)      | 163:
0224     .long   SYM(_uhoh)      | 164:
0225     .long   SYM(_uhoh)      | 165:
0226     .long   SYM(_uhoh)      | 166:
0227     .long   SYM(_uhoh)      | 167:
0228     .long   SYM(_uhoh)      | 168:
0229     .long   SYM(_uhoh)      | 169:
0230     .long   SYM(_uhoh)      | 170:
0231     .long   SYM(_uhoh)      | 171:
0232     .long   SYM(_uhoh)      | 172:
0233     .long   SYM(_uhoh)      | 173:
0234     .long   SYM(_uhoh)      | 174:
0235     .long   SYM(_uhoh)      | 175:
0236     .long   SYM(_uhoh)      | 176:
0237     .long   SYM(_uhoh)      | 177:
0238     .long   SYM(_uhoh)      | 178:
0239     .long   SYM(_uhoh)      | 179:
0240     .long   SYM(_uhoh)      | 180:
0241     .long   SYM(_uhoh)      | 181:
0242     .long   SYM(_uhoh)      | 182:
0243     .long   SYM(_uhoh)      | 183:
0244     .long   SYM(_uhoh)      | 184:
0245     .long   SYM(_uhoh)      | 185:
0246     .long   SYM(_uhoh)      | 186:
0247     .long   SYM(_uhoh)      | 187:
0248     .long   SYM(_uhoh)      | 188:
0249     .long   SYM(_uhoh)      | 189:
0250     .long   SYM(_uhoh)      | 190:
0251     .long   SYM(_uhoh)      | 191:
0252     .long   SYM(_uhoh)      | 192:
0253     .long   SYM(_uhoh)      | 193:
0254     .long   SYM(_uhoh)      | 194:
0255     .long   SYM(_uhoh)      | 195:
0256     .long   SYM(_uhoh)      | 196:
0257     .long   SYM(_uhoh)      | 197:
0258     .long   SYM(_uhoh)      | 198:
0259     .long   SYM(_uhoh)      | 199:
0260     .long   SYM(_uhoh)      | 200:
0261     .long   SYM(_uhoh)      | 201:
0262     .long   SYM(_uhoh)      | 202:
0263     .long   SYM(_uhoh)      | 203:
0264     .long   SYM(_uhoh)      | 204:
0265     .long   SYM(_uhoh)      | 205:
0266     .long   SYM(_uhoh)      | 206:
0267     .long   SYM(_uhoh)      | 207:
0268     .long   SYM(_uhoh)      | 208:
0269     .long   SYM(_uhoh)      | 209:
0270     .long   SYM(_uhoh)      | 210:
0271     .long   SYM(_uhoh)      | 211:
0272     .long   SYM(_uhoh)      | 212:
0273     .long   SYM(_uhoh)      | 213:
0274     .long   SYM(_uhoh)      | 214:
0275     .long   SYM(_uhoh)      | 215:
0276     .long   SYM(_uhoh)      | 216:
0277     .long   SYM(_uhoh)      | 217:
0278     .long   SYM(_uhoh)      | 218:
0279     .long   SYM(_uhoh)      | 219:
0280     .long   SYM(_uhoh)      | 220:
0281     .long   SYM(_uhoh)      | 221:
0282     .long   SYM(_uhoh)      | 222:
0283     .long   SYM(_uhoh)      | 223:
0284     .long   SYM(_uhoh)      | 224:
0285     .long   SYM(_uhoh)      | 225:
0286     .long   SYM(_uhoh)      | 226:
0287     .long   SYM(_uhoh)      | 227:
0288     .long   SYM(_uhoh)      | 228:
0289     .long   SYM(_uhoh)      | 229:
0290     .long   SYM(_uhoh)      | 230:
0291     .long   SYM(_uhoh)      | 231:
0292     .long   SYM(_uhoh)      | 232:
0293     .long   SYM(_uhoh)      | 233:
0294     .long   SYM(_uhoh)      | 234:
0295     .long   SYM(_uhoh)      | 235:
0296     .long   SYM(_uhoh)      | 236:
0297     .long   SYM(_uhoh)      | 237:
0298     .long   SYM(_uhoh)      | 238:
0299     .long   SYM(_uhoh)      | 239:
0300     .long   SYM(_uhoh)      | 240:
0301     .long   SYM(_uhoh)      | 241:
0302     .long   SYM(_uhoh)      | 242:
0303     .long   SYM(_uhoh)      | 243:
0304     .long   SYM(_uhoh)      | 244:
0305     .long   SYM(_uhoh)      | 245:
0306     .long   SYM(_uhoh)      | 246:
0307     .long   SYM(_uhoh)      | 247:
0308     .long   SYM(_uhoh)      | 248:
0309     .long   SYM(_uhoh)      | 249:
0310     .long   SYM(_uhoh)      | 250:
0311     .long   SYM(_uhoh)      | 251:
0312     .long   SYM(_uhoh)      | 252:
0313     .long   SYM(_uhoh)      | 253:
0314     .long   SYM(_uhoh)      | 254:
0315     .long   SYM(_uhoh)      | 255:
0316 
0317 /*
0318  * Default trap handler
0319  * With an oscilloscope you can see AS* stop
0320  */
0321     PUBLIC (_uhoh)
0322 SYM(_uhoh): nop             | Leave spot for breakpoint
0323 /*  stop    #0x2700             | Stop with interrupts disabled */
0324     move.w  #0x2700,sr
0325     move.w  (a7),_boot_panic_registers+4    | SR
0326     move.l  2(a7),_boot_panic_registers | PC
0327     move.w  6(a7),_boot_panic_registers+6   | format & vector
0328     movem.l d0-d7/a0-a7, _boot_panic_registers+8
0329     movec   sfc, d0
0330     movem.l d0, _boot_panic_registers+72
0331     movec   dfc, d0
0332     movem.l d0, _boot_panic_registers+76
0333     movec   vbr, d0
0334     movem.l d0, _boot_panic_registers+80
0335     jmp SYM(_dbug_dumpanic)
0336     bra.s   _crt0_cold_start
0337 
0338 /*
0339  * Log, but otherwise ignore, spurious interrupts
0340  */
0341     PUBLIC (_spuriousInterrupt)
0342 SYM(_spuriousInterrupt):
0343     addql   #1,SYM(_M68kSpuriousInterruptCount)
0344     rte
0345 
0346 /*
0347  * Place the low-order 3 octets of the board's ethernet address at
0348  * a `well-known' fixed location relative to the startup location.
0349  */
0350     .align 2
0351     .word   0           | Padding
0352 ethernet_address_buffer:
0353     .word   0x08F3          | Default address
0354     .word   0xDEAD
0355     .word   0xCAFE
0356 
0357 BEGIN_DATA
0358 
0359 /* equates */
0360 
0361 .equ    _CPU340, 0x0
0362 .equ    _CPU349, 0x31
0363 
0364 #ifdef _OLD_ASTECC              /* old addresses for AST68340 only */
0365 .equ    _EPLD_CS_BASE, 0x1
0366 .equ    _PROM_Start, 0x01000000         /* CS0 */
0367 .equ    _FLEX_Start, 0x08000000         /* CS2 */
0368 .equ    _I2C_Start, 0x0c000000          /* CS3 */
0369 
0370 .equ    _BCCram_Start, 0x00000000           /* CS1  64 Kbytes */
0371 .equ    _BCCram_Size, 0x00010000            /* CS1  64 Kbytes */
0372 
0373 .equ    _ExtRam_Start, 0x10000000       /* SRAM */
0374 .equ    _ExtRam_Size, 0x00400000        /* 4 Mbytes */
0375 
0376 .equ    _FastRam_Start, 0x00000000      /* overlap /CS1 for the first 4 Kbytes */
0377 .equ    _FastRam_Size, 0x00001000       /* 4 Kbytes */
0378 
0379 #else   /* new addresses for AST68349 and 68340 */
0380 
0381 .equ    _EPLD_CS_BASE, 0x5
0382 .equ    _PROM_Start, 0x50000000         /* CS0 */
0383 .equ    _FLEX_Start, 0x08000000         /* CS2 */
0384 .equ    _I2C_Start, 0x0c000000          /* CS3 */
0385 
0386 .equ    _BCCram_Start, 0x00000000           /* CS1  64 Kbytes */
0387 .equ    _BCCram_Size, 0x00010000            /* CS1  64 Kbytes */
0388 
0389 .equ    _ExtRam_Start, 0x80000000       /* DRAM */
0390 .equ    _ExtRam_Size, 0x00400000        /* 4 Mbytes */
0391 
0392 .equ    _FastRam_Start, 0x00000000      /* overlap /CS1 for the first 4 Kbytes */
0393 .equ    _FastRam_Size, 0x00001000       /* 4 Kbytes */
0394 #endif
0395 
0396 .equ    _SPEED349, 0xD680           /* 24 Mhz */
0397 .equ    _SPEED340, 0xD700           /* 25 Mhz */
0398 /* .equ _SPEED340, 0xCE00            16 Mhz */
0399 
0400 #define crt0_boot_type  d0          /* cold/warm start (must be D0) */
0401 #define crt0_temp   d1
0402 #define crt0_cpu_type   d2
0403 #define crt0_csswitch   d3
0404 #define crt0_buswidth   d4
0405 #define crt0_pdcs   d5
0406 #define crt0_spare6 d6
0407 #define crt0_spare7 d7
0408 #define crt0_sim_base   a0
0409 #define crt0_glue   a1
0410 #define crt0_dram   a2
0411 #define crt0_ptr3   a3
0412 #define crt0_ptr4   a4
0413 #define crt0_ptr5   a5
0414 #define crt0_ptr6   a6
0415 
0416 /* -- PDCS buffer equates -- */
0417 .equ    pdcs_mask, 0x1F             /* DRAM configuration */
0418 .equ    pdcs_sw12, 7                /* switch 12 */
0419 .equ    pdcs_sw11, 6                /* switch 11 */
0420 .equ    pdcs_sw14, 5                /* switch 14 */
0421 
0422 .equ    bit_cache, pdcs_sw12            /* enable cache if on */
0423 .equ    bit_meminit, pdcs_sw11          /* init memory if on */
0424 
0425 /* -- Initialization stack and vars -- */
0426 
0427 /* When using DWARF, everything must be a multiple of 16-bits. */
0428 #if 1
0429 _AsteccBusWidth:    ds.w 0x0101
0430 _AsteccCsSwitch:    ds.w 0x0101
0431 #else
0432 _AsteccBusWidth:    ds.b 1
0433 _AsteccCsSwitch:    ds.b 1
0434 #endif
0435 _AsteccCpuName:     ds.l 1
0436 
0437 .align 4
0438 
0439 _crt0_init_stack:
0440         ds.l    500
0441 _crt0_init_stktop:
0442 
0443 /* -- Initialization code -- */
0444 BEGIN_CODE
0445 
0446 .align 4
0447         dc.l    _crt0_init_stktop        /* reset SP */
0448         dc.l    _crt0_cold_start         /* reset PC */
0449         dc.l    _crt0_warm_start
0450 
0451 /* When using DWARF, everything must be a multiple of 16-bits. */
0452         .ascii  "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards "
0453         .text
0454         dc.w    0
0455 .align 4
0456 
0457 .globl start
0458 start:
0459 
0460 _crt0_cold_start:
0461     moveq.l #0,crt0_boot_type           | signal cold reset
0462     bra.s   _crt0_common_start
0463 
0464 _crt0_warm_start:
0465     moveq.l #1,crt0_boot_type           | signal warm reset
0466 
0467 _crt0_common_start:
0468     move.w  #0x2700,sr                      | disable interrupts and switch to interrupt mode
0469     movea.l #_crt0_init_stktop,sp           | set up initialization stack
0470 
0471     move.l  #Entry,crt0_temp            | VBR initialization
0472     movec.l crt0_temp,vbr               |
0473     moveq.l #0x07,crt0_temp
0474     movec.l crt0_temp,dfc               | prepare access in CPU space
0475     move.l  #(BASE_SIM+0x111),crt0_temp         | mask CPU, RESERVED USER SPACES
0476     moves.l crt0_temp,BASE_REG          | base initialization (must be MOVES, PCC-130795)
0477 
0478     movea.l #BASE_SIM,crt0_sim_base
0479 
0480     /* -- disable Bus Monitor -- */
0481     move.b  #0,SIM_SYPCR(crt0_sim_base)         | system protection control register
0482 
0483     /* -- enable A31-A24 -- */
0484     clr.b   SIM_PPRA1(crt0_sim_base)
0485 
0486     /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */
0487     move.w  #0x427F,SIM_MCR(crt0_sim_base)
0488 
0489     /* -- enable /IRQ3, 5, 6, 7 -- */
0490     move.b   #0xE8,SIM_PPRB(crt0_sim_base)
0491 
0492     /* -- enable autovector on /IRQ7 -- */
0493     move.b   #0x80,SIM_AVR(crt0_sim_base)
0494 
0495     /* -- test CPU type -- */
0496     cmp.b     #_CPU349,SIM_IDR(crt0_sim_base)
0497     bne   cpu_is_68340
0498 
0499 /*-------------------------------------------------------------------------------------------*/
0500 cpu_is_68349:
0501 
0502     /* -- set cpu clock -- */
0503     move.w  #_SPEED349,SIM_SYNCR(crt0_sim_base)         | clock
0504 
0505 sync_wait349:
0506     btst.b  #3,(SIM_SYNCR+1)(crt0_sim_base)
0507     beq sync_wait349
0508 
0509     /* to allow access to the EPLD internal registers, it is necessary
0510     to disable the global chip-select /CS0 (which decodes every external
0511     cycles). To do that, we initialize the 68349 internal RAM,
0512     copy a part of the initialization code in it, and jump there.
0513     from that moment, /CS0 is not used, therefore it can be initialized
0514     with its default value. Its width may be incorrect, but it will be
0515     adjusted later. The goal is to avoid any conflict with
0516     the accesses to the EPLD registers.
0517     When this is done, we read the RESET parameters (boot prom width
0518     and chip-select switch) and proceed with the initialization
0519     when all is done, we jump back to the boot prom now
0520     decoded with a properly configured /CS0 */
0521 
0522     /*-------------------------------------*/
0523     /* -- configure internal SRAM banks -- */
0524 
0525     move.l  #0x00000000,QDMM_MCR(crt0_sim_base)
0526     move.l  #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base)
0527     move.l  #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base)
0528     move.l  #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base)
0529     move.l  #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base)
0530 
0531     /*--------------------------------------------------------*/
0532     /* -- copy to address of the 68349 initialization code -- */
0533 
0534     lea.l       _copy_start_code(%pc),crt0_ptr3
0535     lea.l       _copy_end_code(%pc),crt0_ptr4
0536     move.l      crt0_ptr4,crt0_temp
0537     sub.l       crt0_ptr3,crt0_temp
0538     add.l       #3,crt0_temp                | adjust to next long word
0539     lsr.l       #2,crt0_temp
0540 
0541     move.l      #_FastRam_Start,crt0_ptr4
0542 _copy_loop:
0543     move.l      (crt0_ptr3)+,(crt0_ptr4)+
0544     subq.l      #1,crt0_temp
0545     bne.s       _copy_loop
0546     bra.l       _FastRam_Start              | jump to code in internal RAM
0547 
0548     /*------------------------------------*/
0549     /* -- start of initialization code -- */
0550 
0551 _copy_start_code:
0552     bra.l       _begin_68349_init
0553 
0554     /*----------------------------------------------------------*/
0555     /*  Astecc  68349 board : chip-select initialization values */
0556 
0557 _table_csepld:
0558 /* When using DWARF, everything must be a multiple of 16-bits. */
0559 #if 1
0560     dc.w (((_EPLD_CS_BASE&0x0F)+0x80) << 8) | 0x80 | 16 bits, 0ws
0561     dc.w 0x9090             | 16 bits, ext /dsack
0562 
0563 #else
0564     dc.b    (_EPLD_CS_BASE&0x0F)+0x80   | 16 bits, 0ws
0565     dc.b    0x80                | 16 bits, 0 ws
0566     dc.b    0x90                | 16 bits, ext /dsack
0567     dc.b    0x90                | 16 bits, ext /dsack
0568 #endif
0569 
0570 _table_cs349:
0571     dc.l    0x003FFFF4                          | Mask CS0 (4Mbytes PROM, 32bits, 1WS)
0572     dc.l    (_PROM_Start&0xFFFFFF00)+0x00000003         | Base CS0
0573     dc.l    0x003FFFF1                          | MASK CS1 (4Mbytes RAM, 16bits, 0WS)
0574     dc.l    (_BCCram_Start&0xFFFFFF00)+0x00000003       | Base CS1
0575     dc.l    0x000000FF                          | MASK CS2 (FLEX, ext DTACK, 256 bytes)
0576     dc.l    (_FLEX_Start&0xFFFFFF00)+0x00000003         | Base CS2
0577     dc.l    0x000000FF                          | Mask CS3 (I2C, ext DTACK, 256 bytes)
0578     dc.l    (_I2C_Start&0xFFFFFF00)+0x00000003          | Base CS3
0579 
0580     /*-------------------------------------------------*/
0581 _begin_68349_init:
0582 
0583     /*-------------------------------------------------*/
0584     /* 68349 chip select initialization
0585 
0586     at this stage, the width of /CS0 may be incorrect
0587     it will be corrected later
0588     */
0589 
0590 _cs68349_init:
0591     lea.l       SIM_MASKH0(crt0_sim_base),crt0_ptr4
0592     lea.l       _table_cs349(%pc),crt0_ptr3
0593 
0594     moveq.l     #0x07,crt0_temp
0595 _cs349_init2:
0596     move.l      (crt0_ptr3)+,(crt0_ptr4)+
0597     dbra        crt0_temp,_cs349_init2
0598 
0599     /*-----------------------------------------------*/
0600     /* -- prepare access to the internal registers --*/
0601     moveq.l     #EPLD_SPACE,crt0_temp
0602     movec.l     crt0_temp,dfc
0603     movec.l     crt0_temp,sfc
0604     move.l      #GLUE_EPLD,crt0_glue
0605     move.l      #DRAM_EPLD,crt0_dram
0606 
0607     /*-------------------------------------------*/
0608     /* EPLD generated /CS[3..0] must be disabled */
0609 
0610 _csepld_clear:
0611     move.l      crt0_glue,crt0_ptr4
0612     move.w      #3,crt0_spare6
0613     clr.b       crt0_temp
0614 
0615 _csepld_clear1:
0616     moves.b     crt0_temp,(crt0_ptr4)+
0617     dbra        crt0_spare6,_csepld_clear1
0618 
0619     /*---------------------------------------------------------*/
0620     /* -- get width of boot PROM, and active chip-select set --*/
0621     moves.b     REG_BUSWIDTH(crt0_dram),crt0_csswitch
0622     move.b      crt0_csswitch,crt0_buswidth
0623 
0624     /* state of CS_SWITCH  : sel == 0 => CPU chip_selects  (/CS[3..0])
0625                            : sel == 1 => EPLD chip_selects (/CS[3..0]) */
0626     and.b       #1,crt0_csswitch
0627 
0628     /* bus width of /CS0 during reset       bw[1..0]  : 0   1   2       3
0629                                             bus width : 32  16  8   ext./dsackx */
0630     rol.b       #2,crt0_buswidth
0631     and.b       #3,crt0_buswidth
0632 
0633     /*----------------------------------------------------*/
0634     /* -- configure chip select 0 with boot prom width -- */
0635     lea.l       SIM_MASKH0(crt0_sim_base),crt0_ptr4
0636     lea.l       _table_cs349(%pc),crt0_ptr3
0637     move.l      (crt0_ptr3)+,crt0_temp
0638     and.b       #0xFC,crt0_temp             | clear PS0 & PS1
0639     or.b        crt0_buswidth,crt0_temp         | set boot PROM bus width
0640     move.l      crt0_temp,(crt0_ptr4)+
0641 
0642     /*------------------------*/
0643     /* -- read PDCS buffer -- */
0644     moves.b     REG_PDCS(crt0_glue),crt0_pdcs
0645 /*  move.b      #0x3F,crt0_pdcs                     pour test */
0646 
0647     /*---------------------------------------*/
0648     /* -- EPLD chip-select initialization -- */
0649     /*---------------------------------------*/
0650     btst.b      #0,crt0_csswitch
0651     beq     _cs_init_end
0652 
0653     /*--------------------------------------------*/
0654     /* 68349 generated /CS[3..0] must be disabled */
0655     lea.l       SIM_MASKH0(crt0_sim_base),crt0_ptr4
0656     lea.l       _table_cs349(%pc),crt0_ptr3
0657     moveq.l     #0x03,crt0_temp
0658 _cs349_clear:
0659     move.l      (crt0_ptr3)+,(crt0_ptr4)+
0660     move.l      (crt0_ptr3)+,crt0_spare6
0661     and.b       #0xFE,crt0_spare6           | disable chip-select
0662     move.l      crt0_spare6,(crt0_ptr4)+
0663     dbra        crt0_temp,_cs349_clear
0664 
0665     /*---------------------------------------------*/
0666     /* EPLD generated /CS[3..0] must be configured */
0667 _csepld_init:
0668     move.l      crt0_glue,crt0_ptr4
0669     lea.l       _table_csepld(%pc),crt0_ptr3
0670 
0671     move.b      (crt0_ptr3)+,crt0_temp
0672     or.b        #0x20,crt0_temp             | default width is 32 bits
0673     tst.b       crt0_buswidth               | is boot PROM bus width 32 bits ?
0674     beq     _csepld1                | if not
0675     and.b       #0xDF,crt0_temp             | set width to 16 bits
0676 _csepld1:
0677     moves.b     crt0_temp,(crt0_ptr4)+
0678 
0679     moveq.l     #0x02,crt0_spare6
0680 _csepld2:
0681     move.b      (crt0_ptr3)+,crt0_temp
0682     moves.b     crt0_temp,(crt0_ptr4)+
0683     dbra        crt0_spare6,_csepld2
0684 
0685 _cs_init_end:
0686 
0687     /*--------------------------------------*/
0688     /* -- DRAM controller initialization -- */
0689 _dram_init:
0690     move.w      #15,crt0_temp
0691     move.l      #_ExtRam_Start,crt0_ptr3
0692 
0693 _dram_init1:
0694     clr.l       (crt0_ptr3)+                | must access DRAM
0695     dbra        crt0_temp,_dram_init1           | prior to init refresh
0696 
0697 _dram_init2:
0698     move.b      #3,crt0_temp
0699     moves.b     crt0_temp,REG_WS(crt0_dram)         | set 3 wait-states
0700 
0701     move.b      #0x81,crt0_temp
0702     moves.b     crt0_temp,REG_REFRESH(crt0_dram)    | refresh every 10ยตs
0703 
0704     move.b      #0,crt0_temp
0705     moves.b     crt0_temp,REG_CONFIG(crt0_dram)     | default size = 4Mbytes
0706 
0707     /*-----------------------*/
0708     /* -- configure cache -- */
0709 _init_cache:
0710     move.l      #0x000001E0,CACHE_MCR(crt0_sim_base)
0711     btst.b      #bit_cache,crt0_pdcs
0712     bne     _init_cache_end
0713     or.l        #0x00000001,CACHE_MCR(crt0_sim_base)
0714 
0715 _init_cache_end:
0716 
0717     /*-----------------------------*/
0718     /* -- timers initialization -- */
0719 
0720     clr.b       crt0_temp
0721     moves.b     crt0_temp,REG_TIMER1(crt0_glue)     | disable timer 1
0722     moves.b     crt0_temp,REG_TIMER2(crt0_glue)     | disable timer 2
0723 
0724     /*--------------------------*/
0725     /* -- I2C initialization -- */
0726     move.b      #3,crt0_temp
0727     moves.b     crt0_temp,REG_I2C(crt0_glue)        | tri-states I2C ports
0728 
0729     /*-----------------------------------------*/
0730     /* -- baudrate generator initialization -- */
0731     move.b      #2,crt0_temp
0732     moves.b     crt0_temp,REG_BAUDRATE(crt0_glue)   | baudrate = 38400
0733 
0734     /*-------------------------------*/
0735     /* --  IO port initialization -- */
0736     clr.b       crt0_temp
0737     moves.b     crt0_temp,REG_IO(crt0_glue)     | set port as input
0738 
0739     /* -- */
0740 
0741     move.l      #68349,crt0_cpu_type
0742 
0743     /* -- jump back to PROM -- */
0744 
0745     jmp.l       (_fill_test)                | must be absolute long
0746 
0747 _copy_end_code:
0748 
0749 /*-------------------------------------------------
0750   initialization code for the 68340 board
0751   -------------------------------------------------*/
0752 
0753     /* Astecc  68340 board : chip-select initialization values */
0754 _table_cs340:
0755     dc.l    0x003FFFF0                      /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */
0756     dc.l    ((_PROM_Start&0xFFFFFF00)+0x00000003)   /* Base CS0 */
0757     dc.l    0x0000FFFD                      /* MASK CS1 (RAMBCC340, 0WS, FTE) */
0758     dc.l    ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */
0759     dc.l    0x000000FF                      /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */
0760     dc.l    ((_FLEX_Start&0xFFFFFF00)+0x00000003)   /* Base CS2 */
0761     dc.l    0x000000FF                      /* Mask CS3 (I2C, ext DTACK, 256 bytes) */
0762     dc.l    ((_I2C_Start&0xFFFFFF00)+0x00000003)    /* Base CS3 */
0763 
0764 cpu_is_68340:
0765 
0766     /* -- set cpu clock -- */
0767     move.w  #_SPEED340,SIM_SYNCR(crt0_sim_base)         | clock
0768 sync_wait340:
0769     btst.b  #3,(SIM_SYNCR+1)(crt0_sim_base)
0770     beq sync_wait340
0771 
0772     /* -- chip select initialization -- */
0773     lea.l   SIM_MASKH0(crt0_sim_base),crt0_ptr4
0774     lea.l   _table_cs340(%pc),crt0_ptr3
0775     moveq.l #0x07,crt0_temp
0776 _b_cs340:
0777     move.l  (crt0_ptr3)+,crt0_ptr5
0778     move.l  crt0_ptr5,(crt0_ptr4)+              | pour test
0779     dbra    crt0_temp,_b_cs340
0780 
0781     move.l  #68340,crt0_cpu_type
0782     move.b  #0,crt0_csswitch                | CPU
0783     move.b  #1,crt0_buswidth                | 16 bits
0784 
0785     /*-------------------------------------------------
0786       fill RAM if COLDSTART
0787       -------------------------------------------------*/
0788 _fill_test:
0789 
0790     tst.l   crt0_boot_type
0791     bne     _dont_fill
0792 
0793     cmp.b   #_CPU349,SIM_IDR(crt0_sim_base)
0794     bne _fill
0795     btst.b  #bit_meminit,crt0_pdcs
0796     bne _dont_fill
0797 
0798     /* fill main memory */
0799 _fill:
0800     move.l  #_crt0_init_stack,crt0_ptr3         | skip Astecc vars
0801     move.l  #_ExtRam_Start,crt0_temp
0802     sub.l   #_crt0_init_stack,crt0_temp
0803     add.l   #_ExtRam_Size,crt0_temp             | get size
0804     lsr.l   #2,crt0_temp                        | ajust for long word
0805 _fill_loop:
0806     clr.l   (crt0_ptr3)+
0807     subq.l  #1,crt0_temp
0808     bne     _fill_loop
0809 
0810     cmp.b   #_CPU349,SIM_IDR(crt0_sim_base)
0811     bne _fill_bccram
0812 
0813     /* fill QDMM memory */
0814     movea.l #_FastRam_Start,crt0_ptr3           | get start
0815     move.l  #_FastRam_Size,crt0_temp            | get size
0816     lsr.l   #2,crt0_temp                        | ajust for long word
0817 
0818 _QDMMfill_loop:
0819     clr.l   (crt0_ptr3)+
0820     subq.l  #1,crt0_temp
0821     bne _QDMMfill_loop
0822     bra _dont_fill
0823 
0824     /* fill BCC memory */
0825 _fill_bccram:
0826     movea.l #_BCCram_Start,crt0_ptr3            | get start
0827     move.l  #_BCCram_Size,crt0_temp             | get size
0828     lsr.l   #2,crt0_temp                        | ajust for long word
0829 _BCCfill_loop:
0830     clr.l   (crt0_ptr3)+
0831     subq.l  #1,crt0_temp
0832     bne     _BCCfill_loop
0833 
0834     /*-------------------------------------------------*/
0835 _dont_fill:
0836     move.b  crt0_csswitch,_AsteccCsSwitch
0837     move.b  crt0_buswidth,_AsteccBusWidth
0838     move.l  crt0_cpu_type,_AsteccCpuName
0839 
0840     jmp SYM(_Init68340)                 | Start C code (which never returns)
0841 
0842 /*
0843  * Copy DATA segment, clear BSS segment, set up real stack,
0844  * initialize heap, start C program.
0845  * Assume that DATA and BSS sizes are multiples of 4.
0846  */
0847     PUBLIC (_CopyDataClearBSSAndStart)
0848 SYM(_CopyDataClearBSSAndStart):
0849     lea SYM(_copy_start),a0             | Get start of DATA in RAM
0850     lea SYM(_etext),a2                  | Get start of DATA in ROM
0851     cmpl    a0,a2                       | Are they the same?
0852     beq.s   NOCOPY                      | Yes, no copy necessary
0853     lea SYM(_copy_end),a1               | Get end of DATA in RAM
0854     bra.s   COPYLOOPTEST                    | Branch into copy loop
0855 COPYLOOP:
0856     movel   a2@+,a0@+                   | Copy word from ROM to RAM
0857 COPYLOOPTEST:
0858     cmpl    a1,a0                       | Done?
0859     bcs.s   COPYLOOP                    | No, skip
0860 NOCOPY:
0861 
0862     lea _clear_start,a0                 | Get start of BSS
0863     lea _clear_end,a1                   | Get end of BSS
0864     clrl    d0                      | Value to set
0865     bra.s   ZEROLOOPTEST                    | Branch into clear loop
0866 ZEROLOOP:
0867     movel   d0,a0@+                     | Clear a word
0868 ZEROLOOPTEST:
0869     cmpl    a1,a0                       | Done?
0870     bcs.s   ZEROLOOP                    | No, skip
0871 
0872     movel   #_ISR_Stack_area_end,a7     | set master stack pointer
0873     movel   d0,a7@-                     | command line
0874     jsr SYM(boot_card)                  | Call C main
0875 
0876     PUBLIC (_mainDone)
0877 SYM(_mainDone):
0878     nop                         | Leave spot for breakpoint
0879     movew   #1,a7                       | Force a double bus error
0880     movel   d0,a7@-                     | This should cause a RESET
0881 /*  stop    #0x2700                     | Stop with interrupts disabled */
0882     move.w  #0x2700,sr
0883     bra.l   SYM(_mainDone)                  | Stuck forever
0884 
0885         .align 2
0886 BEGIN_DATA_DCL
0887         .align 2
0888     PUBLIC (environ)
0889 SYM (environ):
0890     .long   0
0891     PUBLIC (_M68kSpuriousInterruptCount)
0892 SYM (_M68kSpuriousInterruptCount):
0893     .long   0
0894 END_DATA_DCL
0895 
0896 END
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