Warning, /bsps/m68k/gen68340/include/m68349.inc is written in an unsupported language. File is not indexed.
0001 /*----------------------------------------------------------------------------
0002 * file name: M68349.INC P. CADIC CNET/DSM/TAM/CAT
0003 *
0004 * MC68349 BCC Board Support Package
0005 *
0006 * date: 31/07/97
0007 *
0008 * Description: EQUATES FOR 68349 DEVICES
0009 *
0010 * Modifications:
0011 * - adapted for GNU CC by G.Montel 26/05/98
0012 *----------------------------------------------------------------------------*/
0013
0014 | -- SIM equates --
0015
0016 .equ BASE_REG, 0x3FF00
0017 .equ BASE_SIM, 0xEFFFF000 | pour correction du bug 68349 sur IACK
0018
0019 .equ SIM_MCR, 0x000 | module configuration register
0020 .equ SIM_IDR, 0x002 | processor identification register
0021 .equ SIM_SYNCR, 0x004 | clock synthesizer control register
0022 .equ SIM_AVR, 0x006 | autovector register
0023 .equ SIM_RSR, 0x007 | reset status register
0024
0025 | -- Port A
0026 .equ SIM_PORTA, 0x011 | port A data
0027 .equ SIM_DDRA, 0x013 | port A direction data
0028 .equ SIM_PPRA1, 0x015 | Port A pin assignement 1
0029 .equ SIM_PPRA2, 0x017 | Port A pin assignement 2
0030
0031 | -- Port B
0032 .equ SIM_PORTB, 0x019 | port B data
0033 .equ SIM_PORTB1, 0x01B | port B data auxiliary
0034 .equ SIM_DDRB, 0x01D | port B direction data
0035 .equ SIM_PPRB, 0x01F | Port B pin assignement
0036
0037 .equ SIM_SWIV, 0x020 | SW interrupt vector
0038 .equ SIM_SYPCR, 0x021 | System protection control register
0039 .equ SIM_PICR, 0x022 | Periodic interrupt control register
0040 .equ SIM_PITR, 0x024 | Periodic interrupt timing register
0041 .equ SIM_SWSR, 0x027 | Sofware service
0042
0043 | -- Chip select
0044 .equ SIM_MASKH0, 0x040 | mask register CS0
0045 .equ SIM_MASKL0, 0x042 | mask register CS0
0046 .equ SIM_ADDRH0, 0x044 | base address CS0
0047 .equ SIM_ADDRL0, 0x046 | base address CS0
0048
0049 .equ SIM_MASKH1, 0x048 | mask register CS1
0050 .equ SIM_MASKL1, 0x04A | mask register CS1
0051 .equ SIM_ADDRH1, 0x04C | base address CS1
0052 .equ SIM_ADDRL1, 0x04E | base address CS1
0053
0054 .equ SIM_MASKH2, 0x050 | mask register CS2
0055 .equ SIM_MASKL2, 0x052 | mask register CS2
0056 .equ SIM_ADDRH2, 0x054 | base address CS2
0057 .equ SIM_ADDRL2, 0x056 | base address CS2
0058
0059 .equ SIM_MASKH3, 0x058 | mask register CS3
0060 .equ SIM_MASKL3, 0x05A | mask register CS3
0061 .equ SIM_ADDRH3, 0x05C | base address CS3
0062 .equ SIM_ADDRL3, 0x05E | base address CS3
0063
0064 | -- TIMERS equates --
0065
0066 | __ TIMER 0
0067
0068 .equ TIM_MCR0, 0x600 | Module configuration register
0069 .equ TIM_IR0, 0x604 | interrupt register
0070 .equ TIM_CR0, 0x606 | controle register
0071 .equ TIM_SR0, 0x608 | Status/prescaler register
0072 .equ TIM_CNTR0, 0x60A | counter register
0073 .equ TIM_PREL10, 0x60C | Preload register 1
0074 .equ TIM_PREL20, 0x60E | Preload register 2
0075 .equ TIM_COM0, 0x610 | Compare register
0076
0077 | __ TIMER 1
0078
0079 .equ TIM_MCR1, 0x640 | Module configuration register
0080 .equ TIM_IR1, 0x644 | interrupt register
0081 .equ TIM_CR1, 0x646 | controle register
0082 .equ TIM_SR1, 0x648 | Status/prescaler register
0083 .equ TIM_CNTR1, 0x64A | counter register
0084 .equ TIM_PREL11, 0x64C | Preload register 1
0085 .equ TIM_PREL21, 0x64E | Preload register 2
0086 .equ TIM_COM1, 0x650 | Compare register
0087
0088 | -- U.A.R.T. equates --
0089
0090 .equ UA_MCRH, 0x700 | module configuration register
0091 .equ UA_MCRL, 0x701 | module configuration register
0092 .equ UA_ILR, 0x704 | Interrupt level
0093 .equ UA_IVR, 0x705 | Interrupt vector
0094
0095 .equ UA_MR1A, 0x710 | Mode register 1 A
0096 .equ UA_MR2A, 0x720 | Mode register 2 A
0097 .equ UA_CSRA, 0x711 | Clock_select regiter A
0098 .equ UA_SRA, 0x711 | status register A
0099 .equ UA_CRA, 0x712 | command register A
0100 .equ UA_RBA, 0x713 | receive buffer A
0101 .equ UA_TBA, 0x713 | transmit buffer A
0102
0103 .equ UA_IPCR, 0x714 | input port change register
0104 .equ UA_ACR, 0x714 | auxiliary control register
0105 .equ UA_ISR, 0x715 | interrupt status register
0106 .equ UA_IER, 0x715 | interrupt enable register
0107
0108 .equ UA_MR1B, 0x718 | Mode register 1 B
0109 .equ UA_MR2B, 0x721 | Mode register 2 B
0110 .equ UA_CSRB, 0x719 | Clock_select regiter B
0111 .equ UA_SRB, 0x719 | status register B
0112 .equ UA_CRB, 0x71A | command register A
0113 .equ UA_RBB, 0x71B | receive buffer A
0114 .equ UA_TBB, 0x71B | transmit buffer A
0115
0116 .equ UA_IP, 0x71D | Input port register
0117 .equ UA_OPCR, 0x71D | output port control register
0118 .equ UA_OPS, 0x71E | output port bit set
0119 .equ UA_OPR, 0x71F | output port bit reset
0120 .equ TX_A_EN, 0x01 | Tx A irq enable
0121 .equ TX_B_EN, 0x10 | Tx B irq enable
0122 .equ TX_A_DIS, 0xFE | Tx A irq enable
0123 .equ TX_B_DIS, 0xEF | Tx B irq enable
0124 .equ TX_AB_DIS, 0x22
0125
0126
0127 | -- DMA equates
0128 .equ DMA_MCR0, 0x780 | module configuration register
0129 .equ DMA_IR0, 0x784 | Interrupt register
0130 .equ DMA_CCR0, 0x788 | Channel control register
0131 .equ DMA_CSR0, 0x78A | Channel status register
0132 .equ DMA_FCR0, 0x78B | Function code register
0133 .equ DMA_SARH0, 0x78C | Source adresse register
0134 .equ DMA_SARL0, 0x78E | Source adresse register
0135 .equ DMA_DARH0, 0x790 | destination adresse register
0136 .equ DMA_DARL0, 0x792 | destination adresse register
0137 .equ DMA_BTCH0, 0x794 | byte transfer register
0138 .equ DMA_BTCL0, 0x796 | byte transfer register
0139
0140 .equ DMA_MCR1, 0x7A0 | module configuration register
0141 .equ DMA_IR1, 0x7A4 | Interrupt register
0142 .equ DMA_CCR1, 0x7A8 | Channel control register
0143 .equ DMA_CSR1, 0x7AA | Channel status register
0144 .equ DMA_FCR1, 0x7AB | Function code register
0145 .equ DMA_SARH1, 0x7AC | Source adresse register
0146 .equ DMA_SARL1, 0x7AE | Source adresse register
0147 .equ DMA_DARH1, 0x7B0 | destination adresse register
0148 .equ DMA_DARL1, 0x7B2 | destination adresse register
0149 .equ DMA_BTCH1, 0x7B4 | byte transfer register
0150 .equ DMA_BTCL1, 0x7B6 | byte transfer register
0151
0152 | -- cache equates
0153 .equ CACHE_MCR, 0xFC0 | cache config reg. (long)
0154
0155 | -- quad data memory module (QDMM) equates
0156 .equ QDMM_MCR, 0xC00 | QDMM config reg (long)
0157 .equ QDMM_QBAR0, 0xC10 | QDMM base 0 (long)
0158 .equ QDMM_QBAR1, 0xC14 | QDMM base 1 (long)
0159 .equ QDMM_QBAR2, 0xC18 | QDMM base 2 (long)
0160 .equ QDMM_QBAR3, 0xC1C | QDMM base 3 (long)
0161
0162
0163
0164 |-----------------------------------------------------
0165 | AST68349 internal registers
0166 |-----------------------------------------------------
0167 .equ EPLD_SPACE, 3 | "reserved user" space
0168 .equ CPU_SPACE, 7 | "CPU" space
0169
0170 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0171 | GLUE EPLD
0172 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0173
0174 .equ GLUE_EPLD, 0xB0000000
0175
0176 |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0177 | configuration of /CS0 :
0178 |
0179 | 7 6 5 4 3 2 1 0
0180 | +---+---+---+---+---+---+---+---+
0181 | |ena|val|wid| ws|b31|b30|b29|b28|
0182 | +---+---+---+---+---+---+---+---+
0183 |
0184 | b[31..28] : base address for decoding /CS[3..0]
0185 | the decoding is as follow :
0186 |
0187 | +----------+------------+------+
0188 | | a[31..28] | a[27..26] | /CS |
0189 | +-----------+-----------+------+
0190 | | b[31..28] | 00 | /CS0 | each /CS decodes 64 Mbytes
0191 | | b[31..28] | 01 | /CS1 |
0192 | | b[31..28] | 10 | /CS2 |
0193 | | b[31..28] | 11 | /CS3 |
0194 | +-----------------------+------+
0195 |
0196 | after /RESET, /CS0 is validated for every cycle, until programmed
0197 |
0198 | ws : number of wait-states : 0 => 0 ws
0199 | 1 => external /dsackx
0200 | wid : width of chip-select : 0 => 16 bits
0201 | 1 => 32 bits
0202 | ena : enable chip-select : 0 => disabled
0203 | 1 => enabled
0204 |
0205 | val : automatic validation. set after reset
0206 | cleared when /CS0 is configured
0207 |
0208 .equ REG_CS0, 0
0209
0210
0211 |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0212 | configuration of /CS1 to /CS3:
0213 |
0214 | 7 6 5 4 3 2 1 0
0215 | +---+---+---+---+---+---+---+---+
0216 | |ena| x |wid| ws| x | x | x | x |
0217 | +---+---+---+---+---+---+---+---+
0218 |
0219 | ws : number of wait-states : 0 => 0 ws
0220 | 1 => external /dsackx
0221 | wid : width of chip-select : 0 => 16 bits
0222 | 1 => 32 bits
0223 | ena : enable chip-select : 0 => disabled
0224 | 1 => enabled
0225 .equ REG_CS1, 1
0226 .equ REG_CS2, 2
0227 .equ REG_CS3, 3
0228
0229 |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0230 | I2C register
0231 |
0232 | 7 6 5 4 3 2 1 0
0233 | +---+---+---+---+---+---+---+----+
0234 | | x | x | x | x | x | x |clk|data|
0235 | +---+---+---+---+---+---+---+----+
0236 | bidirecionnal pin, open drain output.
0237 | set bit to 1 to read external state of pin
0238 |
0239 .equ REG_I2C, 4
0240
0241 |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0242 | PDCS register
0243 |
0244 | 7 6 5 4 3 2 1 0
0245 | +---+---+---+---+---+---+---+---+
0246 | |s12|s11|s14|pd5|pd4|pd3|pd2|pd1|
0247 | +---+---+---+---+---+---+---+---+
0248 | pd[5..1] : value read on the DRAM module
0249 | S12, S11 and S14 : "user reserved" configuration switch
0250 |
0251 .equ REG_PDCS, 5
0252
0253 |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0254 | timer1 register
0255 |
0256 | 7 6 5 4 3 2 1 0
0257 | +---+---+---+---+---+---+---+---+
0258 | |ena| x | x | x | x | x | d1| d0|
0259 | +---+---+---+---+---+---+---+---+
0260 |
0261 | the timer clock is the 1000Hz clock of the ASTECC platform
0262 | the timer is reloaded on each write to the register, or if the input
0263 | TIN1 is set to 0.
0264 | on overflow, the open drain output TOUT1 is set to 0
0265 | the timer must be disabled to return TOUT1 to the inactive state
0266 |
0267 .equ REG_TIMER1, 6
0268
0269 |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0270 | timer2 register
0271 |
0272 | 7 6 5 4 3 2 1 0
0273 | +---+---+---+---+---+---+---+---+
0274 | |ena| x | x | x | x | x | d1| d0|
0275 | +---+---+---+---+---+---+---+---+
0276 | the timer clock is the 1000Hz clock of the ASTECC platform
0277 | the timer is reloaded on each write to the register, or if the input
0278 | TIN2 is set to 0.
0279 | on overflow, the open drain output TOUT2 is set to 0
0280 | the timer must be disabled to return TOUT2 to the inactive state
0281 |
0282 .equ REG_TIMER2, 7
0283
0284 |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0285 | baudrate generator register
0286 |
0287 | 7 6 5 4 3 2 1 0
0288 | +---+---+---+---+---+---+---+---+
0289 | | x | x | x | x | x | d2| d1| d0|
0290 | +---+---+---+---+---+---+---+---+
0291 |
0292 | d[2..0] : divider of a 3.6864 Mhz clock
0293 |
0294 | d[2..0] : 0 1 2 3 4 5 6 7
0295 | divides by : 2 4 6 8 10 12 14 16
0296 | SCLK (Mhz) : 1.8432 0.9216 0.6144 0.4608 x 0.3072 x 0.2304
0297 | baudrate : 115200 57600 38400 28800 x 19200 x 14400
0298 |
0299 .equ REG_BAUDRATE, 8
0300
0301 |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0302 | IO register
0303 |
0304 | 7 6 5 4 3 2 1 0
0305 | +---+---+---+---+---+---+---+---+
0306 | | x | x | x |io4|io3|io2|io1|io0|
0307 | +---+---+---+---+---+---+---+---+
0308 |
0309 | io[4..0] : data written to port
0310 |
0311 | maximum current load is about 5 mA per pin
0312 |
0313 .equ REG_IO, 9
0314
0315 |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0316 | IO port
0317 |
0318 | 7 6 5 4 3 2 1 0
0319 | +---+---+---+---+---+---+---+---+
0320 | | x | x | x |io4|io3|io2|io1|io0|
0321 | +---+---+---+---+---+---+---+---+
0322 |
0323 | io[4..0] : data read from port
0324 |
0325 .equ REG_IO_PORT, 10
0326
0327 |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0328 | IO direction register
0329 |
0330 | 7 6 5 4 3 2 1 0
0331 | +---+---+---+---+---+---+---+---+
0332 | | x | x | x | x | x |dr2|dr1|dr0|
0333 | +---+---+---+---+---+---+---+---+
0334 |
0335 | dr0 : 0 => io port 0 is configured as input (default after /RESET)
0336 | 1 => io port 0 is configured as output
0337 |
0338 | dr1 : 0 => io port 1 is configured as input (default after /RESET)
0339 | 1 => io port 1 is configured as output
0340 |
0341 | dr2 : 0 => io ports 2 to 4 are configured as input (default after /RESET)
0342 | 1 => io ports 2 to 4 are configured as output
0343 |
0344 .equ REG_DIR_IO, 11
0345
0346
0347
0348
0349 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0350 | DRAM EPLD
0351 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0352
0353 .equ DRAM_EPLD, 0xA0000000
0354
0355 |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0356 | number of wait-state for DRAM
0357 |
0358 | 7 6 5 4 3 2 1 0
0359 | +---+---+---+---+---+---+---+---+
0360 | | x | x | x | x | x | x |ws1|ws0|
0361 | +---+---+---+---+---+---+---+---+
0362 |
0363 | ws[1..0] : 0 1 2 3
0364 | wait states : 0 1 2 3
0365 |
0366 .equ REG_WS, 0
0367
0368 |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0369 | configuration of refresh for DRAM
0370 |
0371 | 7 6 5 4 3 2 1 0
0372 | +---+---+---+---+---+---+---+---+
0373 | |ena| x | x | x | x | x |rf1|rf0|
0374 | +---+---+---+---+---+---+---+---+
0375 |
0376 | rf[1..0] : 0 1 2 3
0377 | refresh : 5µs 10µs 15µs 20µs
0378 |
0379 | ena == 0 : refresh disabled
0380 | ena == 1 : refresh enabled
0381 |
0382 .equ REG_REFRESH, 1
0383
0384 |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0385 | configuration of DRAM module size
0386 |
0387 | 7 6 5 4 3 2 1 0
0388 | +---+---+---+---+---+---+---+---+
0389 | | x | x | x | x | x |sz2|sz1|sz0|
0390 | +---+---+---+---+---+---+---+---+
0391 |
0392 | sz[2..0] : 0 1 2 3 4 5 6 7
0393 | size (Mbytes): 4 8 16 32 64 128 0 0
0394 |
0395 .equ REG_CONFIG, 2
0396
0397 |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0398 | bus width of /CS0 during reset bw[1..0] : 0 1 2 3
0399 | bus width : 32 16 8 ext. /dsackx
0400 |
0401 | state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0])
0402 | : sel == 1 => EPLD chip_selects (/CS[3..0])
0403 |
0404 | 7 6 5 4 3 2 1 0
0405 | +---+---+---+---+---+---+---+---+
0406 | |bw1|bw0| x | x | x | x | x |sel|
0407 | +---+---+---+---+---+---+---+---+
0408 |
0409 .equ REG_BUSWIDTH, 3
0410
