Warning, /bsps/m68k/gen68340/include/m68340.inc is written in an unsupported language. File is not indexed.
0001 /*----------------------------------------------------------------------------
0002 * file name: M68340.INC JC RAHUEL CNET/DSM/TAM/CAT
0003 *
0004 * MC68340 BCC Board Support Package
0005 *
0006 * date: 1/12/1993
0007 *
0008 * Copyright 1989, Ready Systems FRANCE
0009 *
0010 * Supports: VRTX32 and RTscope
0011 *
0012 * Related Board: MOTOROLA BCC M68340
0013 *
0014 * Description: EQUATES FOR 68340 DEVICES
0015 *
0016 * Changes:
0017 * - Geoffroy Montel (g_montel@yahoo.com) :
0018 * changed EQU syntax for GNU as
0019 *
0020 *----------------------------------------------------------------------------*/
0021
0022 /************************************************
0023 * ATTENTION: must match defs. in C header file *
0024 ************************************************/
0025
0026 /* -- SIM equates -- system integration module */
0027 .equ BASE_REG, 0x3FF00
0028 .equ BASE_SIM, 0xEFFFF000
0029 .equ SIM_MCR, 0x000 /* module configuration register */
0030 .equ SIM_SYNCR, 0x004 /* clock synthesizer control register */
0031 .equ SIM_AVR, 0x006 /* autovector register */
0032 .equ SIM_RSR, 0x007 /* reset status register */
0033
0034 /* -- Port A -- */
0035 .equ SIM_PORTA, 0x011 /* port A data */
0036 .equ SIM_DDRA, 0x013 /* port A direction data */
0037 .equ SIM_PPRA1, 0x015 /* Port A pin assignement 1 */
0038 .equ SIM_PPRA2, 0x017 /* Port A pin assignement 2 */
0039
0040 /* -- Port B -- */
0041 .equ SIM_PORTB, 0x019 /* port B data */
0042 .equ SIM_PORTB1, 0x01B /* port B data auxiliary */
0043 .equ SIM_DDRB, 0x01D /* port B direction data */
0044 .equ SIM_PPRB, 0x01F /* Port B pin assignement */
0045 .equ SIM_SWIV, 0x020 /* SW interrupt vector */
0046 .equ SIM_SYPCR, 0x021 /* System protection control register */
0047 .equ SIM_PICR, 0x022 /* Periodic interrupt control register */
0048 .equ SIM_PITR, 0x024 /* Periodic interrupt timing register */
0049 .equ SIM_SWSR, 0x027 /* Sofware service */
0050
0051 /* -- Chip select -- */
0052 .equ SIM_MASKH0, 0x040 /* mask register CS0 */
0053 .equ SIM_MASKL0, 0x042 /* mask register CS0 */
0054 .equ SIM_ADDRH0, 0x044 /* base address CS0 */
0055 .equ SIM_ADDRL0, 0x046 /* base address CS0 */
0056 .equ SIM_MASKH1, 0x048 /* mask register CS1 */
0057 .equ SIM_MASKL1, 0x04A /* mask register CS1 */
0058 .equ SIM_ADDRH1, 0x04C /* base address CS1 */
0059 .equ SIM_ADDRL1, 0x04E /* base address CS1 */
0060 .equ SIM_MASKH2, 0x050 /* mask register CS2 */
0061 .equ SIM_MASKL2, 0x052 /* mask register CS2 */
0062 .equ SIM_ADDRH2, 0x054 /* base address CS2 */
0063 .equ SIM_ADDRL2, 0x056 /* base address CS2 */
0064 .equ SIM_MASKH3, 0x058 /* mask register CS3 */
0065 .equ SIM_MASKL3, 0x05A /* mask register CS3 */
0066 .equ SIM_ADDRH3, 0x05C /* base address CS3 */
0067 .equ SIM_ADDRL3, 0x05E /* base address CS3 */
0068
0069 /* -- TIMERS equates -- */
0070
0071 /* __ TIMER 0 */
0072 .equ TIM_MCR0, 0x600 /* Module configuration register */
0073 .equ TIM_IR0, 0x604 /* interrupt register */
0074 .equ TIM_CR0, 0x606 /* controle register */
0075 .equ TIM_SR0, 0x608 /* Status/prescaler register */
0076 .equ TIM_CNTR0, 0x60A /* counter register */
0077 .equ TIM_PREL10, 0x60C /* Preload register 1 */
0078 .equ TIM_PREL20, 0x60E /* Preload register 2 */
0079 .equ TIM_COM0, 0x610 /* Compare register */
0080
0081 /* __ TIMER 1 */
0082
0083 .equ TIM_MCR1, 0x640 /* Module configuration register */
0084 .equ TIM_IR1, 0x644 /* interrupt register */
0085 .equ TIM_CR1, 0x646 /* controle register */
0086 .equ TIM_SR1, 0x648 /* Status/prescaler register */
0087 .equ TIM_CNTR1, 0x64A /* counter register */
0088 .equ TIM_PREL11, 0x64C /* Preload register 1 */
0089 .equ TIM_PREL21, 0x64E /* Preload register 2 */
0090 .equ TIM_COM1, 0x650 /* Compare register */
0091
0092 /* -- U.A.R.T. equates -- */
0093
0094 .equ UA_MCRH, 0x700 /* module configuration register */
0095 .equ UA_MCRL, 0x701 /* module configuration register */
0096 .equ UA_ILR, 0x704 /* Interrupt level */
0097 .equ UA_IVR, 0x705 /* Interrupt vector */
0098 .equ UA_MR1A, 0x710 /* Mode register 1 A */
0099 .equ UA_MR2A, 0x720 /* Mode register 2 A*/
0100 .equ UA_CSRA, 0x711 /* Clock_select register A */
0101 .equ UA_SRA, 0x711 /* status register A */
0102 .equ UA_CRA, 0x712 /* command register A */
0103 .equ UA_RBA, 0x713 /* receive buffer A */
0104 .equ UA_TBA, 0x713 /* transmit buffer A */
0105 .equ UA_IPCR, 0x714 /* input port change register */
0106 .equ UA_ACR, 0x714 /* auxiliary control register */
0107 .equ UA_ISR, 0x715 /* interrupt status register */
0108 .equ UA_IER, 0x715 /* interrupt enable register */
0109 .equ UA_MR1B, 0x718 /* Mode register 1 B */
0110 .equ UA_MR2B, 0x721 /* Mode register 2 B */
0111 .equ UA_CSRB, 0x719 /* Clock_select register B */
0112 .equ UA_SRB, 0x719 /* status register B */
0113 .equ UA_CRB, 0x71A /* command register A */
0114 .equ UA_RBB, 0x71B /* receive buffer A */
0115 .equ UA_TBB, 0x71B /* transmit buffer A */
0116 .equ UA_IP, 0x71D /* Input port register */
0117 .equ UA_OPCR, 0x71D /* output port control register */
0118 .equ UA_OPS, 0x71E /* output port bit set */
0119 .equ UA_OPR, 0x71F /* output port bit reset */
0120 .equ TX_A_EN, 0x01 /* Tx A irq enable */
0121 .equ TX_B_EN, 0x10 /* Tx B irq enable */
0122 .equ TX_A_DIS, 0xFE /* Tx A irq enable */
0123 .equ TX_B_DIS, 0xEF /* Tx B irq enable */
0124 .equ TX_AB_DIS, 0x22
0125
0126 /* -- DMA equates -- */
0127 .equ DMA_MCR0, 0x780 /* module configuration register */
0128 .equ DMA_IR0, 0x784 /* Interrupt register */
0129 .equ DMA_CCR0, 0x788 /* Channel control register */
0130 .equ DMA_CSR0, 0x78A /* Channel status register */
0131 .equ DMA_FCR0, 0x78B /* Function code register */
0132 .equ DMA_SARH0, 0x78C /* Source adresse register */
0133 .equ DMA_SARL0, 0x78E /* Source adresse register */
0134 .equ DMA_DARH0, 0x790 /* destination adresse register */
0135 .equ DMA_DARL0, 0x792 /* destination adresse register */
0136 .equ DMA_BTCH0, 0x794 /* byte transfer register */
0137 .equ DMA_BTCL0, 0x796 /* byte transfer register */
0138 .equ DMA_MCR1, 0x7A0 /* module configuration register */
0139 .equ DMA_IR1, 0x7A4 /* Interrupt register */
0140 .equ DMA_CCR1, 0x7A8 /* Channel control register */
0141 .equ DMA_CSR1, 0x7AA /* Channel status register */
0142 .equ DMA_FCR1, 0x7AB /* Function code register */
0143 .equ DMA_SARH1, 0x7AC /* Source adresse register */
0144 .equ DMA_SARL1, 0x7AE /* Source adresse register */
0145 .equ DMA_DARH1, 0x7B0 /* destination adresse register */
0146 .equ DMA_DARL1, 0x7B2 /* destination adresse register */
0147 .equ DMA_BTCH1, 0x7B4 /* byte transfer register */
0148 .equ DMA_BTCL1, 0x7B6 /* byte transfer register */
