gen68340/include/m68340.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup m68k_gen68340
0005  *
0006  * @brief MC68430 definitions.
0007  */
0008
0009 /**********************************************************************
0010  *  MC68340 C Header File                                             *
0011  *                                                                    *
0012  *  Developed by         : Motorola                                   *
0013  *                         High Performance Embedded Systems Division *
0014  *                         Austin, TX                                 *
0015  *  Rectified by     : Geoffroy Montel
0016  *             g_montel@yahoo.com                 *
0017  *                                                                    *
0018  **********************************************************************/
0019
0020 typedef volatile unsigned char *  portb;  /* 8-bit port  */
0021 typedef volatile unsigned short * portw;  /* 16-bit port */
0022 typedef volatile unsigned int *   portl;  /* 32-bit port */
0023
0024 #define MBASE 0xEFFFF000             /* Module Base Address          */
0025                          /* not EFFFF000 due to a 68349
0026                     hardware incompatibility     */
0027
0028 #define MBAR   (*(portb) 0x0003FF00) /* Module Base Addr Reg         */
0029 #define MBAR1  (*(portb) 0x0003FF00) /* Module Base Addr Reg 1 (MSW) */
0030 #define MBAR2  (*(portb) 0x0003FF02) /* Module Base Addr Reg 2 (LSW) */
0031
0032 /* System Integration Module */
0033
0034 #define SIMMCR    (*(portw) (MBASE+0x0000)) /* SIM Module Config Reg    */
0035 #define SIMSYNCR  (*(portw) (MBASE+0x0004)) /* SIM Clock Synth Cont Reg */
0036 #define SIMAVR    (*(portb) (MBASE+0x0006)) /* SIM Autovector Reg       */
0037 #define SIMRSR    (*(portb) (MBASE+0x0007)) /* SIM Reset Status Reg     */
0038 #define SIMPORTA  (*(portb) (MBASE+0x0011)) /* SIM Port A Data Reg      */
0039 #define SIMDDRA   (*(portb) (MBASE+0x0013)) /* SIM Port A Data Dir Reg  */
0040 #define SIMPPRA1  (*(portb) (MBASE+0x0015)) /* SIM Port A Pin Asm 1 Reg */
0041 #define SIMPPRA2  (*(portb) (MBASE+0x0017)) /* SIM Port A Pin Asm 2 Reg */
0042 #define SIMPORTB  (*(portb) (MBASE+0x0019)) /* SIM Port B Data Reg      */
0043 #define SIMPORTB1 (*(portb) (MBASE+0x001B)) /* SIM Port B Data Reg      */
0044 #define SIMDDRB   (*(portb) (MBASE+0x001D)) /* SIM Port B Data Dir Reg  */
0045 #define SIMPPARB  (*(portb) (MBASE+0x001F)) /* SIM Port B Pin Asm Reg   */
0046 #define SIMSWIV   (*(portb) (MBASE+0x0020)) /* SIM SW Interrupt Vector  */
0047 #define SIMSYPCR  (*(portb) (MBASE+0x0021)) /* SIM System Prot Cont Reg */
0048 #define SIMPICR   (*(portw) (MBASE+0x0022)) /* SIM Period Intr Cont Reg */
0049 #define SIMPITR   (*(portw) (MBASE+0x0024)) /* SIM Period Intr Tmg Reg  */
0050 #define SIMSWSR   (*(portb) (MBASE+0x0027)) /* SIM Software Service Reg */
0051
0052 #define SIMCS0AM  (*(portl) (MBASE+0x0040)) /* SIM Chp Sel 0 Addr Msk   */
0053 #define SIMCS0AM1 (*(portw) (MBASE+0x0040)) /* SIM Chp Sel 0 Addr Msk 1 */
0054 #define SIMCS0AM2 (*(portw) (MBASE+0x0042)) /* SIM Chp Sel 0 Addr Msk 2 */
0055 #define SIMCS0BA  (*(portl) (MBASE+0x0044)) /* SIM Chp Sel 0 Base Addr  */
0056 #define SIMCS0BA1 (*(portw) (MBASE+0x0044)) /* SIM Chp Sel 0 Bas Addr 1 */
0057 #define SIMCS0BA2 (*(portw) (MBASE+0x0046)) /* SIM Chp Sel 0 Bas Addr 2 */
0058 #define SIMCS1AM  (*(portl) (MBASE+0x0048)) /* SIM Chp Sel 1 Adress Msk */
0059 #define SIMCS1AM1 (*(portw) (MBASE+0x0048)) /* SIM Chp Sel 1 Addr Msk 1 */
0060 #define SIMCS1AM2 (*(portw) (MBASE+0x004A)) /* SIM Chp Sel 1 Addr Msk 2 */
0061 #define SIMCS1BA  (*(portl) (MBASE+0x004C)) /* SIM Chp Sel 1 Base Addr  */
0062 #define SIMCS1BA1 (*(portw) (MBASE+0x004C)) /* SIM Chp Sel 1 Bas Addr 1 */
0063 #define SIMCS1BA2 (*(portw) (MBASE+0x004E)) /* SIM Chp Sel 1 Bas Addr 2 */
0064 #define SIMCS2AM  (*(portl) (MBASE+0x0050)) /* SIM Chp Sel 2 Addr Msk   */
0065 #define SIMCS2AM1 (*(portw) (MBASE+0x0050)) /* SIM Chp Sel 2 Addr Msk 1 */
0066 #define SIMCS2AM2 (*(portw) (MBASE+0x0052)) /* SIM Chp Sel 2 Addr Msk 2 */
0067 #define SIMCS2BA  (*(portl) (MBASE+0x0054)) /* SIM Chp Sel 2 Base Addr  */
0068 #define SIMCS2BA1 (*(portw) (MBASE+0x0054)) /* SIM Chp Sel 2 Bas Addr 1 */
0069 #define SIMCS2BA2 (*(portw) (MBASE+0x0056)) /* SIM Chp Sel 2 Bas Addr 2 */
0070 #define SIMCS3AM  (*(portl) (MBASE+0x0058)) /* SIM Chp Sel 3 Addr Msk   */
0071 #define SIMCS3AM1 (*(portw) (MBASE+0x0058)) /* SIM Chp Sel 3 Addr Msk 1 */
0072 #define SIMCS3AM2 (*(portw) (MBASE+0x005A)) /* SIM Chp Sel 3 Addr Msk 2 */
0073 #define SIMCS3BA  (*(portl) (MBASE+0x005C)) /* SIM Chp Sel 3 Base Addr  */
0074 #define SIMCS3BA1 (*(portw) (MBASE+0x005C)) /* SIM Chp Sel 3 Bas Addr 1 */
0075 #define SIMCS3BA2 (*(portw) (MBASE+0x005E)) /* SIM Chp Sel 3 Bas Addr 2 */
0076
0077 /* Dynamic Memory Access (DMA) Module */
0078
0079 #define DMAMCR1   (*(portw) (MBASE+0x0780)) /* DMA Module Config Reg 1  */
0080 #define DMAINTR1  (*(portw) (MBASE+0x0784)) /* DMA Interrupt Reg 1      */
0081 #define DMACCR1   (*(portw) (MBASE+0x0788)) /* DMA Channel Cont Reg 1   */
0082 #define DMACSR1   (*(portb) (MBASE+0x078A)) /* DMA Channel Status Reg 1 */
0083 #define DMAFCR1   (*(portb) (MBASE+0x078B)) /* DMA Function Code Reg 1  */
0084 #define DMASAR1   (*(portl) (MBASE+0x078C)) /* DMA DMA Src Addr Reg 1   */
0085 #define DMADAR1   (*(portl) (MBASE+0x0790)) /* DMA Dest Addr Reg 1      */
0086 #define DMABTC1   (*(portb) (MBASE+0x079l)) /* DMA Byte Trans Cnt Reg 1 */
0087
0088 #define DMAMCR2   (*(portw) (MBASE+0x07A0)) /* DMA Module Config Reg 2  */
0089 #define DMAINTR2  (*(portw) (MBASE+0x07A4)) /* DMA Interrupt Reg 2      */
0090 #define DMACCR2   (*(portw) (MBASE+0x07A8)) /* DMA Channel Cont Reg 2   */
0091 #define DMACSR2   (*(portb) (MBASE+0x07AA)) /* DMA Channel Status Reg 2 */
0092 #define DMAFCR2   (*(portb) (MBASE+0x07AB)) /* DMA Function Code Reg 1  */
0093 #define DMASAR2   (*(portl) (MBASE+0x07AC)) /* DMA Source  Addr Reg 2   */
0094 #define DMADAR2   (*(portl) (MBASE+0x07B0)) /* DMA Dest Addr Reg 2      */
0095 #define DMABTC2   (*(portb) (MBASE+0x07B4)) /* DMA Byte Trans Cnt Reg 2 */
0096
0097 /* Dual Serial Module */
0098
0099 #define DUMCRH    (*(portb) (MBASE+0x0700)) /* DUART Module Config Reg  */
0100 #define DUMCRL    (*(portb) (MBASE+0x0701)) /* DUART Module Config Reg  */
0101 #define DUILR     (*(portb) (MBASE+0x0704)) /* DUART Interrupt Level    */
0102 #define DUIVR     (*(portb) (MBASE+0x0705)) /* DUART Interrupt Vector   */
0103 #define DUMR1A    (*(portb) (MBASE+0x0710)) /* DUART Mode Reg 1A        */
0104 #define DUSRA     (*(portb) (MBASE+0x0711)) /* DUART Status Reg A       */
0105 #define DUCSRA    (*(portb) (MBASE+0x0711)) /* DUART Clock Sel Reg A    */
0106 #define DUCRA     (*(portb) (MBASE+0x0712)) /* DUART Command Reg A      */
0107 #define DURBA     (*(portb) (MBASE+0x0713)) /* DUART Receiver Buffer A  */
0108 #define DUTBA     (*(portb) (MBASE+0x0713)) /* DUART Transmitter Buff A */
0109 #define DUIPCR    (*(portb) (MBASE+0x0714)) /* DUART Input Port Chg Reg */
0110 #define DUACR     (*(portb) (MBASE+0x0714)) /* DUART Auxiliary Cont Reg */
0111 #define DUISR     (*(portb) (MBASE+0x0715)) /* DUART Interrupt Stat Reg */
0112 #define DUIER     (*(portb) (MBASE+0x0715)) /* DUART Interrupt Enb Reg  */
0113
0114 #define DUMR1B    (*(portb) (MBASE+0x0718)) /* DUART Mode Reg 1B        */
0115 #define DUSRB     (*(portb) (MBASE+0x0719)) /* DUART Status Reg B       */
0116 #define DUCSRB    (*(portb) (MBASE+0x0719)) /* DUART Clock Sel Reg B    */
0117 #define DUCRB     (*(portb) (MBASE+0x071A)) /* DUART Command Reg B      */
0118 #define DURBB     (*(portb) (MBASE+0x071B)) /* DUART Receiver Buffer B  */
0119 #define DUTBB     (*(portb) (MBASE+0x071B)) /* DUART Transmitter Buff B */
0120 #define DUIP      (*(portb) (MBASE+0x071D)) /* DUART Input Port Reg     */
0121 #define DUOPCR    (*(portb) (MBASE+0x071D)) /* DUART Outp Port Cnt Reg  */
0122 #define DUOPBS    (*(portb) (MBASE+0x071E)) /* DUART Outp Port Bit Set  */
0123 #define DUOPBR    (*(portb) (MBASE+0x071F)) /* DUART Outp Port Bit Rst  */
0124 #define DUMR2A    (*(portb) (MBASE+0x0720)) /* DUART Mode Reg 2A        */
0125 #define DUMR2B    (*(portb) (MBASE+0x0721)) /* DUART Mode Reg 2B        */
0126
0127 /* Dual Timer Module */
0128
0129 #define TMCR1    (*(portw) (MBASE+0x0600)) /* Timer Module Config Reg 1 */
0130 #define TIR1     (*(portw) (MBASE+0x0604)) /* Timer Interrupt Reg 1     */
0131 #define TCR1     (*(portw) (MBASE+0x0606)) /* Timer Control Reg 1       */
0132 #define TSR1     (*(portw) (MBASE+0x0608)) /* Timer Status Reg 1        */
0133 #define TCNTR1   (*(portw) (MBASE+0x060A)) /* Timer Counter Reg 1       */
0134 #define WPREL11  (*(portw) (MBASE+0x060C)) /* Timer Preload 1 Reg 1     */
0135 #define WPREL21  (*(portw) (MBASE+0x060E)) /* Timer Preload 2 Reg 1     */
0136 #define TCOM1    (*(portw) (MBASE+0x0610)) /* Timer Compare Reg 1       */
0137
0138 #define TMCR2    (*(portw) (MBASE+0x0640)) /* Timer Module Config Reg 2 */
0139 #define TIR2     (*(portw) (MBASE+0x0644)) /* Timer Interrupt Reg 2     */
0140 #define TCR2     (*(portw) (MBASE+0x0646)) /* Timer Control Reg 2       */
0141 #define TSR2     (*(portw) (MBASE+0x0648)) /* Timer Status Reg 2        */
0142 #define TCNTR2   (*(portw) (MBASE+0x064A)) /* Timer Counter Reg 2       */
0143 #define WPREL12  (*(portw) (MBASE+0x064C)) /* Timer Preload 1 Reg 2     */
0144 #define WPREL22  (*(portw) (MBASE+0x064E)) /* Timer Preload 2 Reg 2     */
0145 #define TCOM2    (*(portw) (MBASE+0x0650)) /* Timer Compare Reg 2       */