gen68340/include/m340uart.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup m68k_gen68340
0007  *
0008  * @brief UART console driver definitions.
0009  */
0010
0011 /*
0012  *  Header file for console driver
0013  *  defines for accessing M68340/68349 UART registers
0014  *
0015  *  Author:
0016  *  Geoffroy Montel
0017  *  France Telecom - CNET/DSM/TAM/CAT
0018  *  4, rue du Clos Courtel
0019  *  35512 CESSON-SEVIGNE
0020  *  FRANCE
0021  *
0022  *  e-mail: g_montel@yahoo.com
0023  *
0024  *
0025  *  COPYRIGHT (c) 1989-2008.
0026  *  On-Line Applications Research Corporation (OAR).
0027  *
0028  * Redistribution and use in source and binary forms, with or without
0029  * modification, are permitted provided that the following conditions
0030  * are met:
0031  * 1. Redistributions of source code must retain the above copyright
0032  *    notice, this list of conditions and the following disclaimer.
0033  * 2. Redistributions in binary form must reproduce the above copyright
0034  *    notice, this list of conditions and the following disclaimer in the
0035  *    documentation and/or other materials provided with the distribution.
0036  *
0037  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0038  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0039  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0040  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0041  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0042  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0043  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0044  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0045  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0046  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0047  * POSSIBILITY OF SUCH DAMAGE.
0048  */
0049
0050 #ifndef __m340uart_H__
0051 #define __m340uart_H__
0052
0053 #include <sys/types.h>
0054
0055 /* UART initialisation */
0056 #define UART_CHANNEL_A          0
0057 #define UART_CHANNEL_B          1
0058 #define UART_NUMBER_OF_CHANNELS     2
0059 #define UART_CONSOLE_NAME       "/dev/console"
0060 #define UART_RAW_IO_NAME        "/dev/tty1"
0061 #define UART_FIFO_FULL          0
0062 #define UART_CRR            1
0063 #define UART_INTERRUPTS         0
0064 #define UART_POLLING            1
0065 #define UART_TERMIOS_CONSOLE        0
0066 #define UART_TERMIOS_RAW        1
0067 #define UART_TERMIOS_MIN_DEFAULT    1
0068 #define UART_TERMIOS_TIME_DEFAULT   0
0069
0070 void Init_UART_Table(void);
0071
0072 typedef struct {
0073         uint8_t             enable;
0074         uint16_t            rx_buffer_size; /* NOT IMPLEMENTED */
0075         uint16_t            tx_buffer_size; /* NOT IMPLEMENTED */
0076            } uart_termios_config;
0077
0078 typedef struct { /* for one channel */
0079         uint8_t             enable;     /* use this channel */
0080         char            name[64];   /* use UART_CONSOLE_NAME for console purpose */
0081         uint8_t             parity_mode;    /* parity mode, see MR1 section for defines */
0082         uint8_t             bits_per_char;  /* bits per character, see MR1 section for defines  */
0083         float           rx_baudrate;    /* Rx baudrate */
0084         float           tx_baudrate;    /* Tx baudrate */
0085         uint8_t             rx_mode;    /* FIFO Full (UART_FIFO_FULL) or ChannelReceiverReady (UART_CRR) */
0086         uint8_t             mode;       /* use interrupts (UART_INTERRUPTS) or polling (UART_POLLING) */
0087         uart_termios_config termios;
0088            } uart_channel_config;
0089
0090 extern uart_channel_config      m340_uart_config[UART_NUMBER_OF_CHANNELS];
0091
0092 typedef  struct {
0093          int    set;    /* number of the m340 baud speed set */
0094          int    rcs;    /* RCS for the needed baud set */
0095          int    tcs;    /* TCS for the needed baud set */
0096         } t_baud_speed;
0097
0098 typedef  struct {
0099          t_baud_speed   baud_speed_table[2];
0100          short      nb;
0101         } t_baud_speed_table;
0102
0103 extern t_baud_speed_table
0104 Find_Right_m340_UART_Config(float ChannelA_ReceiverBaudRate, float ChannelA_TransmitterBaudRate, uint8_t         enableA,
0105                 float ChannelB_ReceiverBaudRate, float ChannelB_TransmitterBaudRate, uint8_t         enableB);
0106
0107 extern rtems_isr InterruptHandler (rtems_vector_number v);
0108
0109 extern int dbugRead (int minor);
0110 extern ssize_t dbugWrite (int minor, const char *buf, size_t len);
0111
0112 extern float m340_Baud_Rates_Table[16][2];
0113
0114 /*  SR */
0115 #define m340_Rx_RDY     1
0116 #define m340_FFULL      (1<<1)
0117 #define m340_Tx_RDY     (1<<2)
0118 #define m340_TxEMP      (1<<3)
0119 #define m340_OE         (1<<4)
0120 #define m340_PE         (1<<5)
0121 #define m340_FE         (1<<6)
0122 #define m340_RB         (1<<7)
0123
0124 /*  IER */
0125 #define m340_TxRDYA     1
0126 #define m340_RxRDYA     (1<<1)
0127 #define m340_TxRxRDYA       0x3
0128 #define m340_TxRDYB     (1<<4)
0129 #define m340_RxRDYB     (1<<5)
0130 #define m340_TxRxRDYB       0x30
0131
0132 /*  CR */
0133 #define m340_Reset_Error_Status 0x40
0134 #define m340_Reset_Receiver 0x20
0135 #define m340_Reset_Transmitter  0x30
0136 #define m340_Transmitter_Enable (1<<2)
0137 #define m340_Receiver_Enable    1
0138 #define m340_Transmitter_Disable (2<<2)
0139 #define m340_Receiver_Disable   2
0140
0141 /*  ACR */
0142 #define m340_BRG_Set1       0
0143 #define m340_BRG_Set2       (1<<7)
0144
0145 /*  OPCR */
0146 #define m340_OPCR_Gal       0x0
0147 #define m340_OPCR_Aux       0xFF
0148
0149 /*  ISR */
0150 #define m340_COS        (1<<7)
0151 #define m340_DBB        (1<<6)
0152 #define m340_XTAL_RDY       (1<<3)
0153 #define m340_DBA        (1<<2)
0154
0155 /*  MR1 */
0156 #define m340_RxRTS      (1<<7)
0157 #define m340_R_F        (1<<6)      /* character or block mode */
0158 #define m340_ERR        (1<<5)
0159 #define m340_RxRTX      (1<<7)
0160 #define m340_Even_Parity    0
0161 #define m340_Odd_Parity     (1<<2)
0162 #define m340_Low_Parity     (2<<2)
0163 #define m340_High_Parity    (3<<2)
0164 #define m340_No_Parity      (4<<2)
0165 #define m340_Data_Character (6<<2)
0166 #define m340_Address_Character  (7<<2)
0167 #define m340_5bpc       0x0
0168 #define m340_6bpc       0x1
0169 #define m340_7bpc       0x2
0170 #define m340_8bpc       0x3
0171
0172 /*  MR2 */
0173 #define m340_normal     (0<<6)
0174 #define m340_automatic_echo (1<<6)
0175 #define m340_local_loopback (2<<6)
0176 #define m340_remote_loopback    (3<<6)
0177 #define m340_TxRTS      (1<<5)
0178 #define m340_TxCTS      (1<<4)
0179
0180 /* Baud rates for Transmitter/Receiver */
0181 #define SCLK    1       /* put your own SCLK value here */
0182
0183 #endif