csb360/start/init5272.c

0001 /*
0002  *  CSB360 hardware startup routines
0003  *
0004  *  This is where the real hardware setup is done. A minimal stack
0005  *  has been provided by the start.S code. No normal C or RTEMS
0006  *  functions can be called from here.
0007  *
0008  *  This initialization code based on hardware settings of dBUG
0009  *  monitor. This must be changed if you like to run it immediately
0010  *  after reset.
0011  */
0012
0013 /*
0014  *  Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
0015  *  Author: Victor V. Vengerov <vvv@oktet.ru>
0016  *
0017  *  Based on work:
0018  *  Author:
0019  *    David Fiddes, D.J@fiddes.surfaid.org
0020  *    http://www.calm.hw.ac.uk/davidf/coldfire/
0021  *
0022  *  COPYRIGHT (c) 1989-1998.
0023  *  On-Line Applications Research Corporation (OAR).
0024  *
0025  *  The license and distribution terms for this file may be
0026  *  found in the file LICENSE in this distribution or at
0027  *  http://www.rtems.org/license/LICENSE.
0028  */
0029
0030 #include <bsp.h>
0031 #include <mcf5272/mcf5272.h>
0032
0033 /* externs */
0034 extern void clear_bss(void);
0035 extern void start_csb360(void);
0036 extern void INTERRUPT_VECTOR(void);
0037
0038 /* Set the pointers to the modules */
0039 sim_regs_t *g_sim_regs            = (void *) MCF5272_SIM_BASE(BSP_MBAR);
0040 intctrl_regs_t *g_intctrl_regs    = (void *) MCF5272_INT_BASE(BSP_MBAR);
0041 chipsel_regs_t *g_chipsel_regs    = (void *) MCF5272_CS_BASE(BSP_MBAR);
0042 gpio_regs_t *g_gpio_regs          = (void *) MCF5272_GPIO_BASE(BSP_MBAR);
0043 qspi_regs_t *g_qspi_regs          = (void *) MCF5272_QSPI_BASE(BSP_MBAR);
0044 pwm_regs_t *g_pwm_regs            = (void *) MCF5272_PWM_BASE(BSP_MBAR);
0045 dma_regs_t *g_dma_regs            = (void *) MCF5272_DMAC_BASE(BSP_MBAR);
0046 uart_regs_t *g_uart0_regs         = (void *) MCF5272_UART0_BASE(BSP_MBAR);
0047 uart_regs_t *g_uart1_regs         = (void *) MCF5272_UART1_BASE(BSP_MBAR);
0048 timer_regs_t *g_timer_regs        = (void *) MCF5272_TIMER_BASE(BSP_MBAR);
0049 plic_regs_t *g_plic_regs          = (void *) MCF5272_PLIC_BASE(BSP_MBAR);
0050 enet_regs_t *g_enet_regs          = (void *) MCF5272_ENET_BASE(BSP_MBAR);
0051 usb_regs_t *g_usb_regs            = (void *) MCF5272_USB_BASE(BSP_MBAR);
0052
0053 #define m68k_set_srambar( _rambar0 ) \
0054   __asm__ volatile (  "movec %0,%%rambar0\n\t" \
0055                   "nop\n\t" \
0056                   : : "d" (_rambar0) )
0057
0058 #define m68k_set_mbar( _mbar ) \
0059   __asm__ volatile (  "movec %0,%%mbar\n\t" \
0060                   "nop\n\t" \
0061                   : : "d" (_mbar) )
0062
0063 #define mcf5272_enable_cache() \
0064   m68k_set_cacr( MCF5272_CACR_CENB )
0065
0066
0067 #define mcf5272_disable_cache() \
0068   __asm__ volatile (  "nop\n\t"    \
0069                   "movec %0,%%cacr\n\t" \
0070                   "nop\n\t" \
0071                   "movec %0,%%cacr\n\t" \
0072                   "nop\n\t" \
0073                   : : "d" (MCF5272_CACR_CINV) )
0074
0075 /*
0076  * Initialize MCF5272 on-chip modules
0077  */
0078 void init5272(void)
0079 {
0080   /* Invalidate the cache - WARNING: It won't complete for 64 clocks */
0081   m68k_set_cacr(MCF5272_CACR_CINV);
0082
0083   /* Set Module Base Address register */
0084   m68k_set_mbar((BSP_MBAR & MCF5272_MBAR_BA) | MCF5272_MBAR_V);
0085
0086   /* Set RAM Base Address register */
0087   m68k_set_srambar((BSP_RAMBAR & MCF5272_RAMBAR_BA) | MCF5272_RAMBAR_V);
0088
0089   /* Set System Control Register:
0090    * Enet has highest priority, 16384 bus cycles before timeout
0091    */
0092   g_sim_regs->scr = (MCF5272_SCR_HWR_16384);
0093
0094   /* System Protection Register:
0095    * Enable Hardware watchdog timer.
0096    */
0097   g_sim_regs->spr = MCF5272_SPR_HWTEN;
0098
0099   /* Clear and mask all interrupts */
0100   g_intctrl_regs->icr1 = 0x88888888;
0101   g_intctrl_regs->icr2 = 0x88888888;
0102   g_intctrl_regs->icr3 = 0x88888888;
0103   g_intctrl_regs->icr4 = 0x88880000;
0104
0105   /* Copy the interrupt vector table to SRAM */
0106   {
0107     uint32_t *inttab = (uint32_t *)&INTERRUPT_VECTOR;
0108     uint32_t *intvec = (uint32_t *)BSP_RAMBAR;
0109     register int i;
0110     for (i = 0; i < 256; i++) {
0111     *(intvec++) = *(inttab++);
0112     }
0113   }
0114   m68k_set_vbr(BSP_RAMBAR);
0115
0116
0117   /*
0118    * Setup ACRs so that if cache turned on, periphal accesses
0119    * are not messed up.  (Non-cacheable, serialized)
0120    */
0121   m68k_set_acr0(MCF5272_ACR_BASE(BSP_MEM_ADDR_SDRAM)    |
0122         MCF5272_ACR_MASK(BSP_MEM_MASK_SDRAM)    |
0123         MCF5272_ACR_EN                          |
0124         MCF5272_ACR_SM_ANY);
0125
0126 /*
0127   m68k_set_acr1 (MCF5206E_ACR_BASE(BSP_MEM_ADDR_FLASH) |
0128          MCF5206E_ACR_MASK(BSP_MEM_MASK_FLASH) |
0129          MCF5206E_ACR_EN                       |
0130          MCF5206E_ACR_SM_ANY);
0131 */
0132
0133   /* Enable the caches */
0134   m68k_set_cacr(MCF5272_CACR_CENB |
0135         MCF5272_CACR_DCM);       /* Default is not cached */
0136
0137 /*
0138  * Copy data, clear BSS, switch stacks and call boot_card()
0139  */
0140 /*
0141 CopyDataClearBSSAndStart(BSP_MEM_SIZE_ESRAM - 0x400);
0142 */
0143   clear_bss();
0144   start_csb360();
0145
0146 }