csb360/include/bsp.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsM68kCSB3602
0005  *
0006  * @brief Global BSP definitions.
0007  */
0008
0009 /*
0010  * Board Support Package for CSB360 evaluation board
0011  * BSP definitions
0012  *
0013  * Copyright 2004 Cogent Computer Systems
0014  * Author: Jay Monkman <jtm@lopingdog.com>
0015  *
0016  * Derived from mcf5206elite BSP:
0017  * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
0018  * Author: Victor V. Vengerov <vvv@oktet.ru>
0019  *
0020  * The license and distribution terms for this file may be
0021  * found in the file LICENSE in this distribution or at
0022  *
0023  * http://www.rtems.org/license/LICENSE.
0024  */
0025
0026 #ifndef LIBBSP_M68K_CSB360_BSP_H
0027 #define LIBBSP_M68K_CSB360_BSP_H
0028
0029 /**
0030  * @defgroup RTEMSBSPsM68kCSB3602 CSB3602
0031  *
0032  * @ingroup RTEMSBSPsM68k
0033  *
0034  * @brief CSB3602 Board Support Package.
0035  *
0036  * @{
0037  */
0038
0039 #include <mcf5272/mcf5272.h>
0040
0041 /*** Board resources allocation ***/
0042 #define BSP_MEM_ADDR_SRAM 0x20000000
0043 #define BSP_MEM_SIZE_SRAM 4096
0044
0045 /* Location and size of sdram. Note this includes space used by
0046  * umon.
0047  */
0048 #define BSP_MEM_ADDR_SDRAM 0x00000000
0049 #define BSP_MEM_MASK_SDRAM 0x01ffffff
0050 #define BSP_MEM_SIZE_SDRAM (32 * 1024 * 1024)
0051
0052 /* Address to put SIM Modules */
0053 #define BSP_MBAR 0x10000000
0054
0055 /* Address to put SRAM */
0056 #define BSP_RAMBAR BSP_MEM_ADDR_SRAM
0057
0058 /* Interrupt Vectors */
0059 #define BSP_INTVEC_INT1   65
0060 #define BSP_INTVEC_INT2   66
0061 #define BSP_INTVEC_INT3   67
0062 #define BSP_INTVEC_INT4   68
0063 #define BSP_INTVEC_TMR0   69
0064 #define BSP_INTVEC_TMR1   70
0065 #define BSP_INTVEC_TMR2   71
0066 #define BSP_INTVEC_TMR3   72
0067 #define BSP_INTVEC_UART1  73
0068 #define BSP_INTVEC_UART2  74
0069 #define BSP_INTVEC_PLIP   75
0070 #define BSP_INTVEC_PLIA   76
0071 #define BSP_INTVEC_USB0   77
0072 #define BSP_INTVEC_USB1   78
0073 #define BSP_INTVEC_USB2   79
0074 #define BSP_INTVEC_USB3   80
0075 #define BSP_INTVEC_USB4   81
0076 #define BSP_INTVEC_USB5   82
0077 #define BSP_INTVEC_USB6   83
0078 #define BSP_INTVEC_USB7   84
0079 #define BSP_INTVEC_DMA    85
0080 #define BSP_INTVEC_ERX    86
0081 #define BSP_INTVEC_ETX    87
0082 #define BSP_INTVEC_ENTC   88
0083 #define BSP_INTVEC_QSPI   89
0084 #define BSP_INTVEC_INT5   90
0085 #define BSP_INTVEC_INT6   91
0086 #define BSP_INTVEC_SWTO   92
0087
0088 #define BSP_INTLVL_INT1   1
0089 #define BSP_INTLVL_INT2   1
0090 #define BSP_INTLVL_INT3   1
0091 #define BSP_INTLVL_INT4   1
0092 #define BSP_INTLVL_TMR0   1
0093 #define BSP_INTLVL_TMR1   1
0094 #define BSP_INTLVL_TMR2   1
0095 #define BSP_INTLVL_TMR3   1
0096 #define BSP_INTLVL_UART1  1
0097 #define BSP_INTLVL_UART2  1
0098 #define BSP_INTLVL_PLIP   1
0099 #define BSP_INTLVL_PLIA   1
0100 #define BSP_INTLVL_USB0   1
0101 #define BSP_INTLVL_USB1   1
0102 #define BSP_INTLVL_USB2   1
0103 #define BSP_INTLVL_USB3   1
0104 #define BSP_INTLVL_USB4   1
0105 #define BSP_INTLVL_USB5   1
0106 #define BSP_INTLVL_USB6   1
0107 #define BSP_INTLVL_USB7   1
0108 #define BSP_INTLVL_DMA    1
0109 #define BSP_INTLVL_ERX    1
0110 #define BSP_INTLVL_ETX    1
0111 #define BSP_INTLVL_ENTC   1
0112 #define BSP_INTLVL_QSPI   1
0113 #define BSP_INTLVL_INT5   1
0114 #define BSP_INTLVL_INT6   1
0115 #define BSP_INTLVL_SWTO   1
0116
0117
0118
0119 #ifndef ASM
0120
0121 #include <bspopts.h>
0122 #include <rtems.h>
0123 #include <bsp/default-initial-extension.h>
0124
0125 #ifdef __cplusplus
0126 extern "C" {
0127 #endif
0128
0129 struct rtems_bsdnet_ifconfig;
0130 extern int rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config);
0131 #define RTEMS_BSP_NETWORK_DRIVER_NAME   "eth0"
0132 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_enet_driver_attach
0133
0134 /* System frequency */
0135 #define BSP_SYSTEM_FREQUENCY (66 * 1000 * 1000)
0136
0137 /*
0138  *  Simple spin delay in microsecond units for device drivers.
0139  *  This is very dependent on the clock speed of the target.
0140  */
0141
0142 #define rtems_bsp_delay( microseconds ) \
0143   { register uint32_t _delay=(microseconds); \
0144     register uint32_t _tmp=123; \
0145     __asm__ volatile( "0: \
0146                      nbcd      %0 ; \
0147                      nbcd      %0 ; \
0148                      dbf       %1,0b" \
0149                   : "=d" (_tmp), "=d" (_delay) \
0150                   : "0"  (_tmp), "1"  (_delay) ); \
0151   }
0152
0153 /*
0154  * Real-Time Clock Driver Table Entry
0155  * NOTE: put this entry to the device driver table AFTER I2C bus driver!
0156  */
0157 #define RTC_DRIVER_TABLE_ENTRY \
0158     { rtc_initialize, NULL, NULL, NULL, NULL, NULL }
0159 extern rtems_device_driver rtc_initialize(
0160     rtems_device_major_number major,
0161     rtems_device_minor_number minor,
0162     void *arg
0163 );
0164
0165 /* miscellaneous stuff assumed to exist */
0166
0167 extern rtems_isr_entry M68Kvec[];   /* vector table address */
0168
0169 extern rtems_isr (*rtems_clock_hook)(rtems_vector_number);
0170
0171 /* functions */
0172
0173 rtems_isr_entry set_vector(
0174   rtems_isr_entry     handler,
0175   rtems_vector_number vector,
0176   int                 type
0177 );
0178
0179 /*
0180  * Prototypes for BSP methods which cross file boundaries
0181  */
0182 void init5272(void);
0183
0184 #ifdef __cplusplus
0185 }
0186 #endif
0187
0188 #endif /* ASM */
0189
0190 /** @} */
0191
0192 #endif