csb360/dev/timerisr.S

0001 /**
0002  * @file
0003  * @brief Handle MCF5272 TIMER2 interrupts.
0004  *
0005  * All code in this routine is pure overhead which can perturb the
0006  * accuracy of RTEMS' timing test suite.
0007  *
0008  * See also:    benchmark_timer_read()
0009  *
0010  * To reduce overhead this is best to be the "rawest" hardware interupt
0011  * handler you can write.  This should be the only interrupt which can
0012  * occur during the measured time period.
0013  *
0014  * An external counter, Timer_interrupts, is incremented.
0015  */
0016
0017 /*
0018  *  Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
0019  *  Author: Victor V. Vengerov <vvv@oktet.ru>
0020  *
0021  *  This file based on work:
0022  *  Author:
0023  *    David Fiddes, D.J@fiddes.surfaid.org
0024  *    http://www.calm.hw.ac.uk/davidf/coldfire/
0025  *
0026  *  COPYRIGHT (c) 1989-1998.
0027  *  On-Line Applications Research Corporation (OAR).
0028  *
0029  *  The license and distribution terms for this file may be
0030  *  found in the file LICENSE in this distribution or at
0031  *  http://www.rtems.org/license/LICENSE.
0032  */
0033
0034 #include <rtems/asm.h>
0035 #include <bsp.h>
0036
0037 BEGIN_CODE
0038     PUBLIC(timerisr)
0039 SYM(timerisr):
0040     move.l   a0, a7@-
0041     move.b   # (MCF5272_TER_REF + MCF5272_TER_CAP), (a0)
0042     addq.l   #1,SYM(Timer_interrupts) | increment timer value
0043     move.l   a7@+, a0
0044     rte
0045 END_CODE
0046 END