av5282/start/init5282.c

0001 /*
0002  *  This is where the real hardware setup is done. A minimal stack
0003  *  has been provided by the start.S code. No normal C or RTEMS
0004  *  functions can be called from here.
0005  *
0006  * This routine is pretty simple for the uC5282 because all the hard
0007  * work has been done by the bootstrap dBUG code.
0008  */
0009
0010 #include <bsp.h>
0011
0012 #define m68k_set_cacr(_cacr) \
0013     __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr))
0014 #define m68k_set_acr0(_acr0) \
0015     __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0))
0016 #define m68k_set_acr1(_acr1) \
0017     __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1))
0018 #define MM_SDRAM_BASE    (0x00000000)
0019
0020 /*
0021  * External methods used by this file
0022  */
0023 extern void CopyDataClearBSSAndStart (void);
0024 extern void INTERRUPT_VECTOR(void);
0025
0026 void Init5282 (void)
0027 {
0028     int x;
0029     int temp = 0;
0030
0031     /*Setup the GPIO Registers */
0032     MCF5282_GPIO_PBCDPAR = 0x80;
0033     MCF5282_GPIO_PEPAR = 0x5100;
0034     MCF5282_GPIO_PJPAR = 0xFF;
0035     MCF5282_GPIO_PASPAR =  0x0000;
0036     MCF5282_GPIO_PEHLPAR = 0xC0;
0037     MCF5282_GPIO_PUAPAR = 0x0F;
0038     MCF5282_QADC_DDRQB = 0x07;
0039     MCF5282_GPTA_GPTDDR = 0x0C;
0040     MCF5282_GPTA_GPTPORT = 0x4;
0041
0042     /*Setup the Chip Selects so CS0 is flash */
0043     MCF5282_CS0_CSAR =(0xff800000 & 0xffff0000)>>16;
0044     MCF5282_CS0_CSMR = 0x007f0001;
0045     MCF5282_CS0_CSCR =(((0xf)&0x0F)<<10)|(1<<8)|(0x80);
0046
0047   /*Setup the SDRAM  */
0048   for(x=0; x<20000; x++) {
0049     temp +=1;
0050   }
0051   MCF5282_SDRAMC_DCR  = 0x00000239;
0052   MCF5282_SDRAMC_DACR0 = 0x00001320;
0053   MCF5282_SDRAMC_DMR0 = (0x00FC0000) | (0x00000001);
0054   for(x=0; x<20000; x++) {
0055     temp +=1;
0056   }
0057   /* set ip ( bit 3 ) in dacr */
0058   MCF5282_SDRAMC_DACR0 |= (0x00000008) ;
0059   /* init precharge */
0060   *((short *)MM_SDRAM_BASE) = 0;
0061   /* set RE in dacr */
0062   MCF5282_SDRAMC_DACR0 |= (0x00008000);
0063   /* wait */
0064   for(x=0; x<20000; x++) {
0065     temp +=1;
0066   }
0067   /* issue IMRS */
0068   MCF5282_SDRAMC_DACR0 |= (0x00000040);
0069   *((short *)MM_SDRAM_BASE) = 0x0000;
0070   for(x=0; x<60000; x++) {
0071     temp +=1;
0072   }
0073   *((unsigned long*)MM_SDRAM_BASE)=0x12345678;
0074
0075     /* Copy the interrupt vector table to address 0x0 in SDRAM */
0076     {
0077         uint32_t *inttab = (uint32_t *)&INTERRUPT_VECTOR;
0078         uint32_t *intvec = (uint32_t *)0x0;
0079         register int i;
0080         for (i = 0; i < 256; i++) {
0081             *(intvec++) = *(inttab++);
0082         }
0083     }
0084     /*
0085      * Copy data, clear BSS and call boot_card()
0086      */
0087     CopyDataClearBSSAndStart ();
0088 }