av5282/start/bspstart.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  *  This routine does the bulk of the system initialisation.
0005  */
0006
0007 /*
0008  *  Author:
0009  *    David Fiddes, D.J@fiddes.surfaid.org
0010  *    http://www.calm.hw.ac.uk/davidf/coldfire/
0011  *
0012  *  COPYRIGHT (c) 1989-1998.
0013  *  On-Line Applications Research Corporation (OAR).
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #include <bsp.h>
0038 #include <bsp/bootcard.h>
0039 #include <string.h>
0040
0041 /*
0042  * Cacheable areas
0043  */
0044 #define SDRAM_BASE      0
0045 #define SDRAM_SIZE      (16*1024*1024)
0046 #define FLASH_BASE      0xFF800000
0047 #define FLASH_SIZE      (8*1024*1024)
0048
0049 void bsp_start( void )
0050 {
0051   /*
0052    * Invalidate the cache and disable it
0053    */
0054   m68k_set_acr0(0);
0055   m68k_set_acr1(0);
0056   m68k_set_cacr(MCF5XXX_CACR_CINV);
0057
0058   /*
0059    * Cache SDRAM and FLASH
0060    */
0061   m68k_set_acr0(
0062     MCF5XXX_ACR_AB(SDRAM_BASE)    |
0063     MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
0064     MCF5XXX_ACR_EN                |
0065     MCF5XXX_ACR_BWE               |
0066     MCF5XXX_ACR_SM_IGNORE
0067   );
0068
0069   /*
0070    * Enable the cache
0071    */
0072   mcf5xxx_initialize_cacr(
0073     MCF5XXX_CACR_CENB |
0074     MCF5XXX_CACR_DBWE |
0075     MCF5XXX_CACR_DCM
0076   );
0077 }
0078
0079 extern char _CPUClockSpeed[];
0080
0081 uint32_t get_CPU_clock_speed(void)
0082 {
0083   return( (uint32_t)_CPUClockSpeed);
0084 }