rtems/zilog/z8530.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @brief Information Related to a Zilog Z8530 SCC Chip
0007  *
0008  * This include file defines information related to a Zilog Z8530
0009  * SCC Chip.  It is a IO mapped part.
0010  */
0011
0012 /*
0013  *  COPYRIGHT (c) 1989-2011.
0014  *  On-Line Applications Research Corporation (OAR).
0015  *
0016  * Redistribution and use in source and binary forms, with or without
0017  * modification, are permitted provided that the following conditions
0018  * are met:
0019  * 1. Redistributions of source code must retain the above copyright
0020  *    notice, this list of conditions and the following disclaimer.
0021  * 2. Redistributions in binary form must reproduce the above copyright
0022  *    notice, this list of conditions and the following disclaimer in the
0023  *    documentation and/or other materials provided with the distribution.
0024  *
0025  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0026  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0027  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0028  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0029  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0030  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0031  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0032  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0033  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0034  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0035  * POSSIBILITY OF SUCH DAMAGE.
0036  */
0037
0038 #ifndef _RTEMS_ZILOG_Z8530_H
0039 #define _RTEMS_ZILOG_Z8530_H
0040
0041 #ifdef __cplusplus
0042 extern "C" {
0043 #endif
0044
0045 /* macros */
0046
0047 #define VOL8( ptr )   ((volatile uint8_t   *)(ptr))
0048
0049 #define Z8x30_STATE0 ( z8530 ) \
0050   { char *garbage; \
0051     (garbage) = *(VOL8(z8530)) \
0052   }
0053
0054 #define Z8x30_WRITE_CONTROL( z8530, reg, data ) \
0055    *(VOL8(z8530)) = (reg); \
0056    *(VOL8(z8530)) = (data)
0057
0058 #define Z8x30_READ_CONTROL( z8530, reg, data ) \
0059    *(VOL8(z8530)) = (reg); \
0060    (data) = *(VOL8(z8530))
0061
0062 #define Z8x30_WRITE_DATA( z8530, data ) \
0063    *(VOL8(z8530)) = (data);
0064
0065 #define Z8x30_READ_DATA( z8530, data ) \
0066    (data) = *(VOL8(z8530));
0067
0068
0069 /* RR_0 Bit Definitions */
0070
0071 #define RR_0_TX_BUFFER_EMPTY   0x04
0072 #define RR_0_RX_DATA_AVAILABLE 0x01
0073
0074 /* read registers */
0075
0076 #define RR_0       0x00
0077 #define RR_1       0x01
0078 #define RR_2       0x02
0079 #define RR_3       0x03
0080 #define RR_4       0x04
0081 #define RR_5       0x05
0082 #define RR_6       0x06
0083 #define RR_7       0x07
0084 #define RR_8       0x08
0085 #define RR_9       0x09
0086 #define RR_10      0x0A
0087 #define RR_11      0x0B
0088 #define RR_12      0x0C
0089 #define RR_13      0x0D
0090 #define RR_14      0x0E
0091 #define RR_15      0x0F
0092
0093 /* write registers */
0094
0095 #define WR_0       0x00
0096 #define WR_1       0x01
0097 #define WR_2       0x02
0098 #define WR_3       0x03
0099 #define WR_4       0x04
0100 #define WR_5       0x05
0101 #define WR_6       0x06
0102 #define WR_7       0x07
0103 #define WR_8       0x08
0104 #define WR_9       0x09
0105 #define WR_10      0x0A
0106 #define WR_11      0x0B
0107 #define WR_12      0x0C
0108 #define WR_13      0x0D
0109 #define WR_14      0x0E
0110 #define WR_15      0x0F
0111
0112 #ifdef __cplusplus
0113 }
0114 #endif
0115
0116 #endif