LXR |
|
|
|
|||
File indexing completed on 2025-05-11 08:23:43
0001 /* SPDX-License-Identifier: BSD-2-Clause */ 0002 0003 /** 0004 * @file 0005 * 0006 * @brief Zilog Z8036 Counter/Timer/IO Chip 0007 * 0008 * This include file defines information related to a Zilog Z8036 0009 * Counter/Timer/IO Chip. It is a memory mapped part. 0010 * 0011 * @note This file shares as much as possible with the include file 0012 * for the Z8536 via z8x36.h. 0013 */ 0014 0015 /* 0016 * COPYRIGHT (c) 1989-2011. 0017 * On-Line Applications Research Corporation (OAR). 0018 * 0019 * Redistribution and use in source and binary forms, with or without 0020 * modification, are permitted provided that the following conditions 0021 * are met: 0022 * 1. Redistributions of source code must retain the above copyright 0023 * notice, this list of conditions and the following disclaimer. 0024 * 2. Redistributions in binary form must reproduce the above copyright 0025 * notice, this list of conditions and the following disclaimer in the 0026 * documentation and/or other materials provided with the distribution. 0027 * 0028 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 0029 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 0030 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 0031 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 0032 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 0033 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 0034 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 0035 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 0036 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 0037 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 0038 * POSSIBILITY OF SUCH DAMAGE. 0039 */ 0040 0041 #ifndef _RTEMS_ZILOG_Z8036_H 0042 #define _RTEMS_ZILOG_Z8036_H 0043 0044 #ifdef __cplusplus 0045 extern "C" { 0046 #endif 0047 0048 /* macros */ 0049 0050 #define Z8036( ptr ) ((volatile struct z8036_map *)(ptr)) 0051 0052 #define Z8x36_STATE0 ( z8036 ) \ 0053 { /*char *garbage = *(Z8036(z8036))->???; */ } 0054 0055 0056 #define Z8x36_WRITE( z8036, reg, data ) \ 0057 (Z8036(z8036))->reg = (data) 0058 0059 0060 #define Z8x36_READ( z8036, reg, data ) \ 0061 (Z8036(z8036))->reg = (data) 0062 0063 /* structures */ 0064 0065 struct z8036_map { 0066 /* MAIN CONTROL REGISTERS (0x00-0x07) */ 0067 uint8_t MASTER_INTR; /* Master Interrupt Ctl Reg */ 0068 uint8_t MASTER_CFG; /* Master Configuration Ctl Reg */ 0069 uint8_t PORTA_VECTOR; /* Port A - Interrupt Vector */ 0070 uint8_t PORTB_VECTOR; /* Port B - Interrupt Vector */ 0071 uint8_t CNT_TMR_VECTOR; /* Counter/Timer Interrupt Vector */ 0072 uint8_t PORTC_DATA_POLARITY; /* Port C - Data Path Polarity */ 0073 uint8_t PORTC_DIRECTION; /* Port C - Data Direction */ 0074 uint8_t PORTC_SPECIAL_IO_CTL; /* Port C - Special IO Control */ 0075 /* MOST OFTEN ACCESSED REGISTERS (0x08 - 0x0f) */ 0076 uint8_t PORTA_CMD_STATUS; /* Port A - Command Status Reg */ 0077 uint8_t PORTB_CMD_STATUS; /* Port B - Command Status Reg */ 0078 uint8_t CT1_CMD_STATUS; /* Ctr/Timer 1 - Command Status Reg */ 0079 uint8_t CT2_CMD_STATUS; /* Ctr/Timer 2 - Command Status Reg */ 0080 uint8_t CT3_CMD_STATUS; /* Ctr/Timer 3 - Command Status Reg */ 0081 uint8_t PORTA_DATA; /* Port A - Data */ 0082 uint8_t PORTB_DATA; /* Port B - Data */ 0083 uint8_t PORTC_DATA; /* Port C - Data */ 0084 /* COUNTER/TIMER RELATED REGISTERS (0x10-0x1f) */ 0085 uint8_t CT1_CUR_CNT_MSB; /* Ctr/Timer 1 - Current Count (MSB) */ 0086 uint8_t CT1_CUR_CNT_LSB; /* Ctr/Timer 1 - Current Count (LSB) */ 0087 uint8_t CT2_CUR_CNT_MSB; /* Ctr/Timer 2 - Current Count (MSB) */ 0088 uint8_t CT2_CUR_CNT_LSB; /* Ctr/Timer 2 - Current Count (LSB) */ 0089 uint8_t CT3_CUR_CNT_MSB; /* Ctr/Timer 3 - Current Count (MSB) */ 0090 uint8_t CT3_CUR_CNT_LSB; /* Ctr/Timer 3 - Current Count (LSB) */ 0091 uint8_t CT1_TIME_CONST_MSB; /* Ctr/Timer 1 - Time Constant (MSB) */ 0092 uint8_t CT1_TIME_CONST_LSB; /* Ctr/Timer 1 - Time Constant (LSB) */ 0093 uint8_t CT2_TIME_CONST_MSB; /* Ctr/Timer 2 - Time Constant (MSB) */ 0094 uint8_t CT2_TIME_CONST_LSB; /* Ctr/Timer 2 - Time Constant (LSB) */ 0095 uint8_t CT3_TIME_CONST_MSB; /* Ctr/Timer 3 - Time Constant (MSB) */ 0096 uint8_t CT3_TIME_CONST_LSB; /* Ctr/Timer 3 - Time Constant (LSB) */ 0097 uint8_t CT1_MODE_SPEC; /* Ctr/Timer 1 - Mode Specification */ 0098 uint8_t CT2_MODE_SPEC; /* Ctr/Timer 2 - Mode Specification */ 0099 uint8_t CT3_MODE_SPEC; /* Ctr/Timer 3 - Mode Specification */ 0100 uint8_t CURRENT_VECTOR; /* Current Vector */ 0101 /* PORT A SPECIFICATION REGISTERS (0x20 -0x27) */ 0102 uint8_t PORTA_MODE; /* Port A - Mode Specification */ 0103 uint8_t PORTA_HANDSHAKE; /* Port A - Handshake Specification */ 0104 uint8_t PORTA_DATA_POLARITY; /* Port A - Data Path Polarity */ 0105 uint8_t PORTA_DIRECTION; /* Port A - Data Direction */ 0106 uint8_t PORTA_SPECIAL_IO_CTL; /* Port A - Special IO Control */ 0107 uint8_t PORTA_PATT_POLARITY; /* Port A - Pattern Polarity */ 0108 uint8_t PORTA_PATT_TRANS; /* Port A - Pattern Transition */ 0109 uint8_t PORTA_PATT_MASK; /* Port A - Pattern Mask */ 0110 /* PORT B SPECIFICATION REGISTERS (0x28-0x2f) */ 0111 uint8_t PORTB_MODE; /* Port B - Mode Specification */ 0112 uint8_t PORTB_HANDSHAKE; /* Port B - Handshake Specification */ 0113 uint8_t PORTB_DATA_POLARITY; /* Port B - Data Path Polarity */ 0114 uint8_t PORTB_DIRECTION; /* Port B - Data Direction */ 0115 uint8_t PORTB_SPECIAL_IO_CTL; /* Port B - Special IO Control */ 0116 uint8_t PORTB_PATT_POLARITY; /* Port B - Pattern Polarity */ 0117 uint8_t PORTB_PATT_TRANS; /* Port B - Pattern Transition */ 0118 uint8_t PORTB_PATT_MASK; /* Port B - Pattern Mask */ 0119 }; 0120 0121 #ifdef __cplusplus 0122 } 0123 #endif 0124 0125 #endif
| [ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
|
This page was automatically generated by the 2.3.7 LXR engine. The LXR team |
|