include/peripheral_maps/xilinx_zynqmp.h

0001 /**
0002  * @file
0003  * @ingroup RTEMSBSPsShared
0004  * @brief Xilinx Zynq Ultrascale+ MPSoC Peripheral memory map.
0005  */
0006
0007 /*
0008  * SPDX-License-Identifier: BSD-2-Clause
0009  *
0010  * Copyright (C) 2023 Reflex Aerospace GmbH
0011  *
0012  * Written by Philip Kirkpatrick <p.kirkpatrick@reflexaerospace.com>
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LIBBSP_SHARED_PERIPHERAL_MAPS_ZYNQMP
0037 #define LIBBSP_SHARED_PERIPHERAL_MAPS_ZYNQMP
0038
0039 /* Data derived from https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/PS-I/O-Peripherals-Registers */
0040
0041 /* LPD IO Peripherals */
0042 #define ZYNQMP_UART0 (0xFF000000)
0043 #define ZYNQMP_UART1 (0xFF010000)
0044 #define ZYNQMP_I2C0 (0xFF020000)
0045 #define ZYNQMP_I2C1 (0xFF030000)
0046 #define ZYNQMP_SPI0 (0xFF040000)
0047 #define ZYNQMP_SPI1 (0xFF050000)
0048 #define ZYNQMP_CAN0 (0xFF060000)
0049 #define ZYNQMP_CAN1 (0xFF070000)
0050 #define ZYNQMP_GPIO (0xFF0A0000)
0051 #define ZYNQMP_GEM0 (0xFF0B0000)
0052 #define ZYNQMP_GEM1 (0xFF0C0000)
0053 #define ZYNQMP_GEM2 (0xFF0D0000)
0054 #define ZYNQMP_GEM3 (0xFF0E0000)
0055 #define ZYNQMP_QSPI (0xFF0F0000)
0056 #define ZYNQMP_NAND (0xFF100000)
0057 #define ZYNQMP_SD0 (0xFF160000)
0058 #define ZYNQMP_SD1 (0xFF170000)
0059 #define ZYNQMP_IPI_MSG (0xFF990000)
0060 #define ZYNQMP_USB0 (0xFF9D0000)
0061 #define ZYNQMP_USB1 (0xFF9E0000)
0062 #define ZYNQMP_AMS (0xFFA50000)
0063 #define ZYNQMP_PSSYSMON (0xFFA50800)
0064 #define ZYNQMP_PLSYSMON (0xFFA50C00)
0065 #define ZYNQMP_CSU_SWDT (0xFFCB0000)
0066
0067 /* FPD IO Peripherals */
0068 #define ZYNQMP_SATA (0xFD0C0000)
0069 #define ZYNQMP_PCIE (0xFD0E0000)
0070 #define ZYNQMP_PCIE_IN (0xFD0E0800)
0071 #define ZYNQMP_PCIE_EG (0xFD0E0C00)
0072 #define ZYNQMP_PCIE_DMA (0xFD0F0000)
0073 #define ZYNQMP_SIOU (0xFD3D0000)
0074 #define ZYNQMP_GTR (0xFD400000)
0075 #define ZYNQMP_PCIE_ATTR (0xFD480000)
0076 #define ZYNQMP_DP (0xFD4A0000)
0077 #define ZYNQMP_GPU (0xFD4B0000)
0078 #define ZYNQMP_DP_DMA (0xFD4C0000)
0079
0080 /* LPD System Registers */
0081 #define ZYNQMP_IPI (0xFF300000)
0082 #define ZYNQMP_TTC0 (0xFF110000)
0083 #define ZYNQMP_TTC1 (0xFF120000)
0084 #define ZYNQMP_TTC2 (0xFF130000)
0085 #define ZYNQMP_TTC3 (0xFF140000)
0086 #define ZYNQMP_LPD_SWDT (0xFF150000)
0087 #define ZYNQMP_XPPU (0xFF980000)
0088 #define ZYNQMP_XPPU_SINK (0xFF9C0000)
0089 #define ZYNQMP_PL_LPD (0xFF9B0000)
0090 #define ZYNQMP_OCM (0xFFA00000)
0091 #define ZYNQMP_LPD_FPD (0xFFA10000)
0092 #define ZYNQMP_RTC (0xFFA60000)
0093 #define ZYNQMP_OCM_XMPU (0xFFA70000)
0094 #define ZYNQMP_LPD_DMA (0xFFA80000)
0095 #define ZYNQMP_CSU_DMA (0xFFC80000)
0096 #define ZYNQMP_CSU (0xFFCA0000)
0097 #define ZYNQMP_BBRAM (0xFFCD0000)
0098
0099 /* System Interrupt Table */
0100
0101 /* SPIs */
0102 #define ZYNQMP_IRQ_UART_0 53
0103 #define ZYNQMP_IRQ_UART_1 54
0104
0105 #define ZYNQMP_IRQ_TTC_0_0 68
0106 #define ZYNQMP_IRQ_TTC_0_1 69
0107 #define ZYNQMP_IRQ_TTC_0_2 70
0108 #define ZYNQMP_IRQ_TTC_1_0 71
0109 #define ZYNQMP_IRQ_TTC_1_1 72
0110 #define ZYNQMP_IRQ_TTC_1_2 73
0111 #define ZYNQMP_IRQ_TTC_2_0 74
0112 #define ZYNQMP_IRQ_TTC_2_1 75
0113 #define ZYNQMP_IRQ_TTC_2_2 76
0114 #define ZYNQMP_IRQ_TTC_3_0 77
0115 #define ZYNQMP_IRQ_TTC_3_1 78
0116 #define ZYNQMP_IRQ_TTC_3_2 79
0117
0118 #endif /* LIBBSP_SHARED_PERIPHERAL_MAPS_ZYNQMP */