include/grlib/spwtdp.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*  SPWTDP - SpaceWire Time Distribution Protocol. The driver provides
0004  *  device discovery and interrupt management.
0005  *
0006  *  COPYRIGHT (c) 2017.
0007  *  Cobham Gaisler AB
0008  *
0009  * Redistribution and use in source and binary forms, with or without
0010  * modification, are permitted provided that the following conditions
0011  * are met:
0012  * 1. Redistributions of source code must retain the above copyright
0013  *    notice, this list of conditions and the following disclaimer.
0014  * 2. Redistributions in binary form must reproduce the above copyright
0015  *    notice, this list of conditions and the following disclaimer in the
0016  *    documentation and/or other materials provided with the distribution.
0017  *
0018  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0019  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0020  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0021  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0022  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0023  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0024  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0025  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0026  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0027  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0028  * POSSIBILITY OF SUCH DAMAGE.
0029  *
0030  */
0031
0032 #ifndef __SPWTDP_H__
0033 #define __SPWTDP_H__
0034
0035 #ifdef __cplusplus
0036 extern "C" {
0037 #endif
0038
0039 #define SPWTDP_ERR_OK       0
0040 #define SPWTDP_ERR_EINVAL   -1
0041 #define SPWTDP_ERR_ERROR    -2
0042 #define SPWTDP_ERR_NOINIT   -3
0043
0044 /* Maximum number of SPWTDP devices supported by driver */
0045 #define SPWTDP_MAX 2
0046
0047 /* SPWTDP Register layout */
0048 struct spwtdp_regs {
0049     volatile unsigned int conf[4];       /* 0x000-0x00C */
0050     volatile unsigned int stat[4];       /* 0x010-0x01C */
0051     volatile unsigned int cmd_ctrl;      /* 0x020 */
0052     volatile unsigned int cmd_et[5];     /* 0x024-0x034 */
0053     volatile unsigned int resv1[2];      /* 0x038-0x03C */
0054     volatile unsigned int dat_ctrl;      /* 0x040 */
0055     volatile unsigned int dat_et[5];     /* 0x044-0x054 */
0056     volatile unsigned int resv2[2];      /* 0x058-0x05C */
0057     volatile unsigned int ts_rx_ctrl;    /* 0x060 */
0058     volatile unsigned int ts_rx_et[5];   /* 0x064-0x074 */
0059     volatile unsigned int resv3[2];      /* 0x078-0x07C */
0060     volatile unsigned int ts_tx_ctrl;    /* 0x080 */
0061     volatile unsigned int ts_tx_et[5];   /* 0x084-0x094 */
0062     volatile unsigned int resv4[2];      /* 0x098 */
0063     volatile unsigned int lat_ctrl;      /* 0x0A0 */
0064     volatile unsigned int lat_et[5];     /* 0x0A4-0x0B4 */
0065     volatile unsigned int resv5[2];      /* 0x0B8-0x0BC */
0066     volatile unsigned int ien;           /* 0x0C0 */
0067     volatile unsigned int ists;          /* 0x0C4 */
0068     volatile unsigned int dlycnt;        /* 0x0C8 */
0069     volatile unsigned int dissync;       /* 0x0CC */
0070     volatile unsigned int resv6[12];     /* 0x0D0-0x0FC */
0071     volatile unsigned int edmask[4];     /* 0x100-0x10C */
0072     struct {
0073         volatile unsigned int ctrl;          /* 0x110, 0x130, 0x150, 0x170 */
0074         volatile unsigned int et[5];         /* 0x114-0x124, 0x134-0x144, 0x154-0x164, 0x174-0x184,  */
0075         volatile unsigned int resv0[2];      /* 0x128-0x12C, 0x148-0x14C, 0x168-0x16C, 0x188-0x18C,  */
0076     } edat[4];                           /* 0x110-0x18C */
0077     volatile unsigned int resv7[4];      /* 0x190-0x19C */
0078     volatile unsigned int pulse[8];      /* 0x1A0-0x1BC */
0079     volatile unsigned int resv8[16];     /* 0x1C0-0x1FC */
0080 };
0081
0082 /*
0083  * Configuration register definitions
0084  */
0085 #define CONF0_JE    (0x1 << CONF0_JE_BIT)
0086 #define CONF0_ST    (0x1 << CONF0_ST_BIT)
0087 #define CONF0_EP    (0x1 << CONF0_EP_BIT)
0088 #define CONF0_ET    (0x1 << CONF0_ET_BIT)
0089 #define CONF0_SP    (0x1 << CONF0_SP_BIT)
0090 #define CONF0_SE    (0x1 << CONF0_SE_BIT)
0091 #define CONF0_LE    (0x1 << CONF0_LE_BIT)
0092 #define CONF0_AE    (0x1 << CONF0_AE_BIT)
0093 #define CONF0_MAP   (0x1f << CONF0_MAP_BIT)
0094 #define CONF0_TD    (0x1 << CONF0_TD_BIT)
0095 #define CONF0_MU    (0x1 << CONF0_MU_BIT)
0096 #define CONF0_SEL   (0x3 << CONF0_SEL_BIT)
0097 #define CONF0_ME    (0x1 << CONF0_ME_BIT)
0098 #define CONF0_RE    (0x1 << CONF0_RE_BIT)
0099 #define CONF0_TE    (0x1 << CONF0_TE_BIT)
0100 #define CONF0_RS    (0x1 << CONF0_RS_BIT)
0101
0102 #define CONF0_JE_BIT    24
0103 #define CONF0_ST_BIT    21
0104 #define CONF0_EP_BIT    20
0105 #define CONF0_ET_BIT    19
0106 #define CONF0_SP_BIT    18
0107 #define CONF0_SE_BIT    17
0108 #define CONF0_LE_BIT    16
0109 #define CONF0_AE_BIT    15
0110 #define CONF0_MAP_BIT   8
0111 #define CONF0_TD_BIT    7
0112 #define CONF0_MU_BIT    6
0113 #define CONF0_SEL_BIT   4
0114 #define CONF0_ME_BIT    3
0115 #define CONF0_RE_BIT    2
0116 #define CONF0_TE_BIT    1
0117 #define CONF0_RS_BIT    0
0118
0119 #define CONF1_FSINC (0x3fffffff << CONF1_FSINC_BIT)
0120
0121 #define CONF1_FSINC_BIT 0
0122
0123 #define CONF2_CV    (0xffffff << CONF2_CV_BIT)
0124 #define CONF2_ETINC (0xff << CONF2_ETINC_BIT)
0125
0126 #define CONF2_CV_BIT    8
0127 #define CONF2_ETINC_BIT 0
0128
0129 #define CONF3_OUTPORT   (0xf << CONF3_OUTPORT_BIT)
0130 #define CONF3_INPORT    (0xf << CONF3_INPORT_BIT)
0131 #define CONF3_STM   (0x3f << CONF3_STM_BIT)
0132 #define CONF3_DI64R (0x1 << CONF3_DI64R_BIT)
0133 #define CONF3_DI64T (0x1 << CONF3_DI64T_BIT)
0134 #define CONF3_DI64  (0x1 << CONF3_DI64_BIT)
0135 #define CONF3_DI    (0x1 << CONF3_DI_BIT)
0136 #define CONF3_INRX  (0x1f << CONF3_INRX_BIT)
0137 #define CONF3_INTX  (0x1f << CONF3_INTX_BIT)
0138
0139 #define CONF3_OUTPORT_BIT 28
0140 #define CONF3_INPORT_BIT 24
0141 #define CONF3_STM_BIT   16
0142 #define CONF3_DI64R_BIT 13
0143 #define CONF3_DI64T_BIT 12
0144 #define CONF3_DI64_BIT  11
0145 #define CONF3_DI_BIT    10
0146 #define CONF3_INRX_BIT  5
0147 #define CONF3_INTX_BIT  0
0148
0149 /*
0150  * Control register definitions
0151  */
0152 #define CTRL_NC     (0x1 << CTRL_NC_BIT)
0153 #define CTRL_IS     (0x1 << CTRL_IS_BIT)
0154 #define CTRL_SPWTC  (0xff << CTRL_SPWTC_BIT)
0155 #define CTRL_CPF    (0xffff << CTRL_CPF_BIT)
0156
0157 #define CTRL_NC_BIT 31
0158 #define CTRL_IS_BIT 30
0159 #define CTRL_SPWTC_BIT  16
0160 #define CTRL_CPF_BIT    0
0161
0162 /*
0163  * Interrupt register definition
0164  */
0165 #define SPWTDP_IRQ_S        (0x1 << SPWTDP_IRQ_S_BIT)
0166 #define SPWTDP_IRQ_TR       (0x1 << SPWTDP_IRQ_TR_BIT)
0167 #define SPWTDP_IRQ_TM       (0x1 << SPWTDP_IRQ_TM_BIT)
0168 #define SPWTDP_IRQ_TT       (0x1 << SPWTDP_IRQ_TT_BIT)
0169 #define SPWTDP_IRQ_DIR      (0x1 << SPWTDP_IRQ_DIR_BIT)
0170 #define SPWTDP_IRQ_DIT      (0x1 << SPWTDP_IRQ_DIT_BIT)
0171 #define SPWTDP_IRQ_EDI0     (0x1 << SPWTDP_IRQ_EDI0_BIT)
0172 #define SPWTDP_IRQ_EDI1     (0x1 << SPWTDP_IRQ_EDI1_BIT)
0173 #define SPWTDP_IRQ_EDI2     (0x1 << SPWTDP_IRQ_EDI2_BIT)
0174 #define SPWTDP_IRQ_EDI3     (0x1 << SPWTDP_IRQ_EDI3_BIT)
0175 #define SPWTDP_IRQ_SET      (0x1 << SPWTDP_IRQ_SET_BIT)
0176 #define SPWTDP_IRQ_P0       (0x1 << SPWTDP_IRQ_P0_BIT)
0177 #define SPWTDP_IRQ_P1       (0x1 << SPWTDP_IRQ_P1_BIT)
0178 #define SPWTDP_IRQ_P2       (0x1 << SPWTDP_IRQ_P2_BIT)
0179 #define SPWTDP_IRQ_P3       (0x1 << SPWTDP_IRQ_P3_BIT)
0180 #define SPWTDP_IRQ_P4       (0x1 << SPWTDP_IRQ_P4_BIT)
0181 #define SPWTDP_IRQ_P5       (0x1 << SPWTDP_IRQ_P5_BIT)
0182 #define SPWTDP_IRQ_P6       (0x1 << SPWTDP_IRQ_P6_BIT)
0183 #define SPWTDP_IRQ_P7       (0x1 << SPWTDP_IRQ_P7_BIT)
0184 #define SPWTDP_IRQ_NCTC     (0x1 << SPWTDP_IRQ_NCTC_BIT)
0185 #define SPWTDP_IRQ_WCLEAR   \
0186     (SPWTDP_IRQ_S | SPWTDP_IRQ_TR | SPWTDP_IRQ_TM | \
0187      SPWTDP_IRQ_TT | SPWTDP_IRQ_DIR | SPWTDP_IRQ_DIT | SPWTDP_IRQ_EDI0 | \
0188      SPWTDP_IRQ_EDI1 | SPWTDP_IRQ_EDI2 | SPWTDP_IRQ_EDI3 | SPWTDP_IRQ_SET |\
0189      SPWTDP_IRQ_P0 | SPWTDP_IRQ_P1 | SPWTDP_IRQ_P2 | SPWTDP_IRQ_P3 | \
0190      SPWTDP_IRQ_P4 | SPWTDP_IRQ_P5 | SPWTDP_IRQ_P6 | SPWTDP_IRQ_P7 | \
0191      SPWTDP_IRQ_NCTC)
0192 #define SPWTDP_IRQ_ALL      (SPWTDP_IRQ_WCLEAR)
0193
0194 #define SPWTDP_IRQ_S_BIT 0
0195 #define SPWTDP_IRQ_TR_BIT 1
0196 #define SPWTDP_IRQ_TM_BIT 2
0197 #define SPWTDP_IRQ_TT_BIT 3
0198 #define SPWTDP_IRQ_DIR_BIT 4
0199 #define SPWTDP_IRQ_DIT_BIT 5
0200 #define SPWTDP_IRQ_EDI0_BIT 6
0201 #define SPWTDP_IRQ_EDI1_BIT 7
0202 #define SPWTDP_IRQ_EDI2_BIT 8
0203 #define SPWTDP_IRQ_EDI3_BIT 9
0204 #define SPWTDP_IRQ_SET_BIT 10
0205 #define SPWTDP_IRQ_P0_BIT 11
0206 #define SPWTDP_IRQ_P1_BIT 12
0207 #define SPWTDP_IRQ_P2_BIT 13
0208 #define SPWTDP_IRQ_P3_BIT 14
0209 #define SPWTDP_IRQ_P4_BIT 15
0210 #define SPWTDP_IRQ_P5_BIT 16
0211 #define SPWTDP_IRQ_P6_BIT 17
0212 #define SPWTDP_IRQ_P7_BIT 18
0213 #define SPWTDP_IRQ_NCTC_BIT 19
0214
0215 /* Register the SPWTDP Driver to the Driver Manager */
0216 void spwtdp_register_drv(void);
0217
0218 /* Open a SPWTDP device by registration order index. A SPWTDP device can only by
0219  * opened once. The handle returned must be used as the input parameter 'spwtdp'
0220  * in the rest of the calls in the function interface.
0221  */
0222 extern void *spwtdp_open(int dev_no);
0223
0224 /* Close a previously opened SPWTDP device */
0225 extern int spwtdp_close(void *spwtdp);
0226
0227 /* Reset SPWTDP Core */
0228 extern int spwtdp_reset(void *spwtdp);
0229
0230 /* Setup the frequency configuration registers */
0231 extern int spwtdp_freq_setup(void *spwtdp, uint32_t fsinc, uint32_t cv,
0232                  uint8_t etinc);
0233
0234 /* Unmask Interrupts at Interrupt controller */
0235 extern int spwtdp_interrupt_unmask(void *spwtdp, uint32_t irqmask);
0236
0237 /* Mask Interrupts at Interrupt controller */
0238 extern int spwtdp_interrupt_mask(void *spwtdp, uint32_t irqmask);
0239
0240 /* Function ISR callback prototype
0241  *
0242  * ists    - Interrupt STatus register of the SPWTDP core read by ISR
0243  * data    - Custom data provided by user
0244  */
0245 typedef void (*spwtdp_isr_t)(unsigned int ists, void *data);
0246
0247 /* Register an Interrupt handler and custom data, the function call is
0248  * removed by calling unregister function.
0249  */
0250 extern int spwtdp_isr_register(void *spwtdp, spwtdp_isr_t isr, void *data);
0251
0252 /* Unregister an Interrupt handler */
0253 extern int spwtdp_isr_unregister(void *spwtdp);
0254
0255 /* Get and clear interrupt status */
0256 extern int spwtdp_interrupt_status(void *spwtdp, uint32_t *sts,
0257                    uint32_t clrmask);
0258
0259 /* Setup Initiator and target */
0260 #define SPWTDP_TDP_ENABLE CONF0_TD
0261 #define SPWTDP_TDP_DISABLE 0
0262 #define SPWTDP_LATENCY_ENABLE CONF0_LE
0263 #define SPWTDP_LATENCY_DISABLE 0
0264 #define SPWTDP_EXTET_INC_POLARITY_RISING CONF0_EP
0265 #define SPWTDP_EXTET_INC_POLARITY_FALLING 0
0266 #define SPWTDP_EXTET_INC_ENABLE CONF0_ET
0267 #define SPWTDP_EXTET_INC_DISABLE 0
0268 #define SPWTDP_EXTET_POLARITY_RISING CONF0_SP
0269 #define SPWTDP_EXTET_POLARITY_FALLING 0
0270 #define SPWTDP_EXTET_ENABLE CONF0_SE
0271 #define SPWTDP_EXTET_DISABLE 0
0272 #define SPWTDP_TARGET_SPWSYNC_ENABLE CONF0_ST
0273 #define SPWTDP_TARGET_SPWSYNC_DISABLE 0
0274 #define SPWTDP_TARGET_JITTERC_ENABLE CONF0_JE
0275 #define SPWTDP_TARGET_JITTERC_DISABLE 0
0276 #define SPWTDP_TARGET_MITIGATION_ENABLE CONF0_ME
0277 #define SPWTDP_TARGET_MITIGATION_DISABLE 0
0278 extern int spwtdp_initiator_conf(void *spwtdp, uint8_t mapping,
0279                  uint32_t options);
0280 extern int spwtdp_target_conf(void *spwtdp, uint8_t mapping, uint32_t options);
0281
0282 /* Setup Initiator and target dist interrupts */
0283 extern int spwtdp_initiator_int_conf(void *spwtdp, uint8_t stm, uint8_t inrx,
0284                      uint8_t intx);
0285 #define SPWTDP_TARGET_DISTINT_INTACK CONF3_DI
0286 #define SPWTDP_TARGET_DISTINT_INT 0
0287 extern int spwtdp_target_int_conf(void *spwtdp, uint8_t inrx, uint8_t intx,
0288                   uint32_t options);
0289
0290 /* Enable Initiator and target */
0291 extern int spwtdp_initiator_enable(void *spwtdp);
0292 extern int spwtdp_target_enable(void *spwtdp);
0293
0294 /* Disable Initiator and target */
0295 extern int spwtdp_initiator_disable(void *spwtdp);
0296 extern int spwtdp_target_disable(void *spwtdp);
0297
0298 /* Get and clear status */
0299 extern int spwtdp_status(void *spwtdp, uint32_t *sts, uint32_t clrmask);
0300
0301 /* Define time struct */
0302 /* Length of the max data sample (136 bits), aligned to the next 32-bit word
0303  * (160 bits=20 byte=5 words)
0304  */
0305 #define SPWTDP_TIME_DATA_LENGTH 20
0306 struct spwtdp_time_t {
0307     uint8_t data[SPWTDP_TIME_DATA_LENGTH];
0308     uint32_t preamble;
0309 };
0310 typedef struct spwtdp_time_t spwtdp_time_t;
0311
0312 /* Get datation elapsed time */
0313 extern int spwtdp_dat_et_get(void *spwtdp, spwtdp_time_t * val);
0314 extern int spwtdp_tsrx_et_get(void *spwtdp, spwtdp_time_t * val);
0315 extern int spwtdp_tstx_et_get(void *spwtdp, spwtdp_time_t * val);
0316 extern int spwtdp_lat_et_get(void *spwtdp, spwtdp_time_t * val);
0317 extern int spwtdp_cmd_et_get(void *spwtdp, spwtdp_time_t * val);
0318
0319 /* Configure TSTX */
0320 extern int spwtdp_initiator_tstx_conf(void *spwtdp, uint8_t tstc);
0321
0322 /* Manage control register */
0323 extern int spwtdp_initiator_cmd_et_set(void *spwtdp, spwtdp_time_t val);
0324 extern int spwtdp_initiator_cmd_spwtc_set(void *spwtdp, uint8_t spwtc);
0325 #define SPWTDP_TARGET_CTRL_NEWCOMMAND_ENABLE CTRL_NC
0326 #define SPWTDP_TARGET_CTRL_NEWCOMMAND_DISABLE 0
0327 #define SPWTDP_TARGET_CTRL_INIT CTRL_IS
0328 #define SPWTDP_TARGET_CTRL_SYNC 0
0329 extern int spwtdp_target_cmd_conf(void *spwtdp, uint8_t spwtc, uint16_t cpf,
0330                   uint32_t options);
0331
0332 /* Get precision */
0333 extern int spwtdp_precision_get(void *spwtdp, uint8_t *fine, uint8_t *coarse);
0334
0335 #ifdef __cplusplus
0336 }
0337 #endif
0338
0339 #endif