include/grlib/spwtdp-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRLIBSPWTDP
0007  *
0008  * @brief This header file defines the SPWTDP register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/spwtdp-header */
0054
0055 #ifndef _GRLIB_SPWTDP_REGS_H
0056 #define _GRLIB_SPWTDP_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/spwtdp */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRLIBSPWTDP SPWTDP
0068  *
0069  * @ingroup RTEMSDeviceGRLIB
0070  *
0071  * @brief This group contains the SPWTDP interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRLIBSPWTDPCONF0 Configuration 0 (CONF0)
0078  *
0079  * @brief This group contains register bit definitions.
0080  *
0081  * @{
0082  */
0083
0084 #define SPWTDP_CONF0_JE 0x1000000U
0085
0086 #define SPWTDP_CONF0_ST 0x200000U
0087
0088 #define SPWTDP_CONF0_EP 0x100000U
0089
0090 #define SPWTDP_CONF0_ET 0x80000U
0091
0092 #define SPWTDP_CONF0_SP 0x40000U
0093
0094 #define SPWTDP_CONF0_SE 0x20000U
0095
0096 #define SPWTDP_CONF0_LE 0x10000U
0097
0098 #define SPWTDP_CONF0_AE 0x8000U
0099
0100 #define SPWTDP_CONF0_MAPPING_SHIFT 8
0101 #define SPWTDP_CONF0_MAPPING_MASK 0x1f00U
0102 #define SPWTDP_CONF0_MAPPING_GET( _reg ) \
0103   ( ( ( _reg ) & SPWTDP_CONF0_MAPPING_MASK ) >> \
0104     SPWTDP_CONF0_MAPPING_SHIFT )
0105 #define SPWTDP_CONF0_MAPPING_SET( _reg, _val ) \
0106   ( ( ( _reg ) & ~SPWTDP_CONF0_MAPPING_MASK ) | \
0107     ( ( ( _val ) << SPWTDP_CONF0_MAPPING_SHIFT ) & \
0108       SPWTDP_CONF0_MAPPING_MASK ) )
0109 #define SPWTDP_CONF0_MAPPING( _val ) \
0110   ( ( ( _val ) << SPWTDP_CONF0_MAPPING_SHIFT ) & \
0111     SPWTDP_CONF0_MAPPING_MASK )
0112
0113 #define SPWTDP_CONF0_TD 0x80U
0114
0115 #define SPWTDP_CONF0_MU 0x40U
0116
0117 #define SPWTDP_CONF0_SEL_SHIFT 4
0118 #define SPWTDP_CONF0_SEL_MASK 0x30U
0119 #define SPWTDP_CONF0_SEL_GET( _reg ) \
0120   ( ( ( _reg ) & SPWTDP_CONF0_SEL_MASK ) >> \
0121     SPWTDP_CONF0_SEL_SHIFT )
0122 #define SPWTDP_CONF0_SEL_SET( _reg, _val ) \
0123   ( ( ( _reg ) & ~SPWTDP_CONF0_SEL_MASK ) | \
0124     ( ( ( _val ) << SPWTDP_CONF0_SEL_SHIFT ) & \
0125       SPWTDP_CONF0_SEL_MASK ) )
0126 #define SPWTDP_CONF0_SEL( _val ) \
0127   ( ( ( _val ) << SPWTDP_CONF0_SEL_SHIFT ) & \
0128     SPWTDP_CONF0_SEL_MASK )
0129
0130 #define SPWTDP_CONF0_ME 0x8U
0131
0132 #define SPWTDP_CONF0_RE 0x4U
0133
0134 #define SPWTDP_CONF0_TE 0x2U
0135
0136 #define SPWTDP_CONF0_RS 0x1U
0137
0138 /** @} */
0139
0140 /**
0141  * @defgroup RTEMSDeviceGRLIBSPWTDPCONF3 Configuration 3 (CONF3)
0142  *
0143  * @brief This group contains register bit definitions.
0144  *
0145  * @{
0146  */
0147
0148 #define SPWTDP_CONF3_STM_SHIFT 16
0149 #define SPWTDP_CONF3_STM_MASK 0x3f0000U
0150 #define SPWTDP_CONF3_STM_GET( _reg ) \
0151   ( ( ( _reg ) & SPWTDP_CONF3_STM_MASK ) >> \
0152     SPWTDP_CONF3_STM_SHIFT )
0153 #define SPWTDP_CONF3_STM_SET( _reg, _val ) \
0154   ( ( ( _reg ) & ~SPWTDP_CONF3_STM_MASK ) | \
0155     ( ( ( _val ) << SPWTDP_CONF3_STM_SHIFT ) & \
0156       SPWTDP_CONF3_STM_MASK ) )
0157 #define SPWTDP_CONF3_STM( _val ) \
0158   ( ( ( _val ) << SPWTDP_CONF3_STM_SHIFT ) & \
0159     SPWTDP_CONF3_STM_MASK )
0160
0161 #define SPWTDP_CONF3_DI64R 0x2000U
0162
0163 #define SPWTDP_CONF3_DI64T 0x1000U
0164
0165 #define SPWTDP_CONF3_DI64 0x800U
0166
0167 #define SPWTDP_CONF3_DI 0x400U
0168
0169 #define SPWTDP_CONF3_INRX_SHIFT 5
0170 #define SPWTDP_CONF3_INRX_MASK 0x3e0U
0171 #define SPWTDP_CONF3_INRX_GET( _reg ) \
0172   ( ( ( _reg ) & SPWTDP_CONF3_INRX_MASK ) >> \
0173     SPWTDP_CONF3_INRX_SHIFT )
0174 #define SPWTDP_CONF3_INRX_SET( _reg, _val ) \
0175   ( ( ( _reg ) & ~SPWTDP_CONF3_INRX_MASK ) | \
0176     ( ( ( _val ) << SPWTDP_CONF3_INRX_SHIFT ) & \
0177       SPWTDP_CONF3_INRX_MASK ) )
0178 #define SPWTDP_CONF3_INRX( _val ) \
0179   ( ( ( _val ) << SPWTDP_CONF3_INRX_SHIFT ) & \
0180     SPWTDP_CONF3_INRX_MASK )
0181
0182 #define SPWTDP_CONF3_INTX_SHIFT 0
0183 #define SPWTDP_CONF3_INTX_MASK 0x1fU
0184 #define SPWTDP_CONF3_INTX_GET( _reg ) \
0185   ( ( ( _reg ) & SPWTDP_CONF3_INTX_MASK ) >> \
0186     SPWTDP_CONF3_INTX_SHIFT )
0187 #define SPWTDP_CONF3_INTX_SET( _reg, _val ) \
0188   ( ( ( _reg ) & ~SPWTDP_CONF3_INTX_MASK ) | \
0189     ( ( ( _val ) << SPWTDP_CONF3_INTX_SHIFT ) & \
0190       SPWTDP_CONF3_INTX_MASK ) )
0191 #define SPWTDP_CONF3_INTX( _val ) \
0192   ( ( ( _val ) << SPWTDP_CONF3_INTX_SHIFT ) & \
0193     SPWTDP_CONF3_INTX_MASK )
0194
0195 /** @} */
0196
0197 /**
0198  * @defgroup RTEMSDeviceGRLIBSPWTDPCTRL Control (CTRL)
0199  *
0200  * @brief This group contains register bit definitions.
0201  *
0202  * @{
0203  */
0204
0205 #define SPWTDP_CTRL_NC 0x80000000U
0206
0207 #define SPWTDP_CTRL_IS 0x40000000U
0208
0209 #define SPWTDP_CTRL_SPWTC_SHIFT 16
0210 #define SPWTDP_CTRL_SPWTC_MASK 0xff0000U
0211 #define SPWTDP_CTRL_SPWTC_GET( _reg ) \
0212   ( ( ( _reg ) & SPWTDP_CTRL_SPWTC_MASK ) >> \
0213     SPWTDP_CTRL_SPWTC_SHIFT )
0214 #define SPWTDP_CTRL_SPWTC_SET( _reg, _val ) \
0215   ( ( ( _reg ) & ~SPWTDP_CTRL_SPWTC_MASK ) | \
0216     ( ( ( _val ) << SPWTDP_CTRL_SPWTC_SHIFT ) & \
0217       SPWTDP_CTRL_SPWTC_MASK ) )
0218 #define SPWTDP_CTRL_SPWTC( _val ) \
0219   ( ( ( _val ) << SPWTDP_CTRL_SPWTC_SHIFT ) & \
0220     SPWTDP_CTRL_SPWTC_MASK )
0221
0222 #define SPWTDP_CTRL_CPF_SHIFT 0
0223 #define SPWTDP_CTRL_CPF_MASK 0xffffU
0224 #define SPWTDP_CTRL_CPF_GET( _reg ) \
0225   ( ( ( _reg ) & SPWTDP_CTRL_CPF_MASK ) >> \
0226     SPWTDP_CTRL_CPF_SHIFT )
0227 #define SPWTDP_CTRL_CPF_SET( _reg, _val ) \
0228   ( ( ( _reg ) & ~SPWTDP_CTRL_CPF_MASK ) | \
0229     ( ( ( _val ) << SPWTDP_CTRL_CPF_SHIFT ) & \
0230       SPWTDP_CTRL_CPF_MASK ) )
0231 #define SPWTDP_CTRL_CPF( _val ) \
0232   ( ( ( _val ) << SPWTDP_CTRL_CPF_SHIFT ) & \
0233     SPWTDP_CTRL_CPF_MASK )
0234
0235 /** @} */
0236
0237 /**
0238  * @defgroup RTEMSDeviceGRLIBSPWTDPCET0 Command Elapsed Time 0 (CET0)
0239  *
0240  * @brief This group contains register bit definitions.
0241  *
0242  * @{
0243  */
0244
0245 #define SPWTDP_CET0_CET0_SHIFT 0
0246 #define SPWTDP_CET0_CET0_MASK 0xffffffffU
0247 #define SPWTDP_CET0_CET0_GET( _reg ) \
0248   ( ( ( _reg ) & SPWTDP_CET0_CET0_MASK ) >> \
0249     SPWTDP_CET0_CET0_SHIFT )
0250 #define SPWTDP_CET0_CET0_SET( _reg, _val ) \
0251   ( ( ( _reg ) & ~SPWTDP_CET0_CET0_MASK ) | \
0252     ( ( ( _val ) << SPWTDP_CET0_CET0_SHIFT ) & \
0253       SPWTDP_CET0_CET0_MASK ) )
0254 #define SPWTDP_CET0_CET0( _val ) \
0255   ( ( ( _val ) << SPWTDP_CET0_CET0_SHIFT ) & \
0256     SPWTDP_CET0_CET0_MASK )
0257
0258 /** @} */
0259
0260 /**
0261  * @defgroup RTEMSDeviceGRLIBSPWTDPCET1 Command Elapsed Time 1 (CET1)
0262  *
0263  * @brief This group contains register bit definitions.
0264  *
0265  * @{
0266  */
0267
0268 #define SPWTDP_CET1_CET1_SHIFT 0
0269 #define SPWTDP_CET1_CET1_MASK 0xffffffffU
0270 #define SPWTDP_CET1_CET1_GET( _reg ) \
0271   ( ( ( _reg ) & SPWTDP_CET1_CET1_MASK ) >> \
0272     SPWTDP_CET1_CET1_SHIFT )
0273 #define SPWTDP_CET1_CET1_SET( _reg, _val ) \
0274   ( ( ( _reg ) & ~SPWTDP_CET1_CET1_MASK ) | \
0275     ( ( ( _val ) << SPWTDP_CET1_CET1_SHIFT ) & \
0276       SPWTDP_CET1_CET1_MASK ) )
0277 #define SPWTDP_CET1_CET1( _val ) \
0278   ( ( ( _val ) << SPWTDP_CET1_CET1_SHIFT ) & \
0279     SPWTDP_CET1_CET1_MASK )
0280
0281 /** @} */
0282
0283 /**
0284  * @defgroup RTEMSDeviceGRLIBSPWTDPCET2 Command Elapsed Time 2 (CET2)
0285  *
0286  * @brief This group contains register bit definitions.
0287  *
0288  * @{
0289  */
0290
0291 #define SPWTDP_CET2_CET2_SHIFT 0
0292 #define SPWTDP_CET2_CET2_MASK 0xffffffffU
0293 #define SPWTDP_CET2_CET2_GET( _reg ) \
0294   ( ( ( _reg ) & SPWTDP_CET2_CET2_MASK ) >> \
0295     SPWTDP_CET2_CET2_SHIFT )
0296 #define SPWTDP_CET2_CET2_SET( _reg, _val ) \
0297   ( ( ( _reg ) & ~SPWTDP_CET2_CET2_MASK ) | \
0298     ( ( ( _val ) << SPWTDP_CET2_CET2_SHIFT ) & \
0299       SPWTDP_CET2_CET2_MASK ) )
0300 #define SPWTDP_CET2_CET2( _val ) \
0301   ( ( ( _val ) << SPWTDP_CET2_CET2_SHIFT ) & \
0302     SPWTDP_CET2_CET2_MASK )
0303
0304 /** @} */
0305
0306 /**
0307  * @defgroup RTEMSDeviceGRLIBSPWTDPCET3 Command Elapsed Time 3 (CET3)
0308  *
0309  * @brief This group contains register bit definitions.
0310  *
0311  * @{
0312  */
0313
0314 #define SPWTDP_CET3_CET3_SHIFT 0
0315 #define SPWTDP_CET3_CET3_MASK 0xffffffffU
0316 #define SPWTDP_CET3_CET3_GET( _reg ) \
0317   ( ( ( _reg ) & SPWTDP_CET3_CET3_MASK ) >> \
0318     SPWTDP_CET3_CET3_SHIFT )
0319 #define SPWTDP_CET3_CET3_SET( _reg, _val ) \
0320   ( ( ( _reg ) & ~SPWTDP_CET3_CET3_MASK ) | \
0321     ( ( ( _val ) << SPWTDP_CET3_CET3_SHIFT ) & \
0322       SPWTDP_CET3_CET3_MASK ) )
0323 #define SPWTDP_CET3_CET3( _val ) \
0324   ( ( ( _val ) << SPWTDP_CET3_CET3_SHIFT ) & \
0325     SPWTDP_CET3_CET3_MASK )
0326
0327 /** @} */
0328
0329 /**
0330  * @defgroup RTEMSDeviceGRLIBSPWTDPCET4 Command Elapsed Time 4 (CET4)
0331  *
0332  * @brief This group contains register bit definitions.
0333  *
0334  * @{
0335  */
0336
0337 #define SPWTDP_CET4_CET4_SHIFT 24
0338 #define SPWTDP_CET4_CET4_MASK 0xff000000U
0339 #define SPWTDP_CET4_CET4_GET( _reg ) \
0340   ( ( ( _reg ) & SPWTDP_CET4_CET4_MASK ) >> \
0341     SPWTDP_CET4_CET4_SHIFT )
0342 #define SPWTDP_CET4_CET4_SET( _reg, _val ) \
0343   ( ( ( _reg ) & ~SPWTDP_CET4_CET4_MASK ) | \
0344     ( ( ( _val ) << SPWTDP_CET4_CET4_SHIFT ) & \
0345       SPWTDP_CET4_CET4_MASK ) )
0346 #define SPWTDP_CET4_CET4( _val ) \
0347   ( ( ( _val ) << SPWTDP_CET4_CET4_SHIFT ) & \
0348     SPWTDP_CET4_CET4_MASK )
0349
0350 /** @} */
0351
0352 /**
0353  * @defgroup RTEMSDeviceGRLIBSPWTDPDPF Datation Preamble Field (DPF)
0354  *
0355  * @brief This group contains register bit definitions.
0356  *
0357  * @{
0358  */
0359
0360 #define SPWTDP_DPF_DPF_SHIFT 0
0361 #define SPWTDP_DPF_DPF_MASK 0xffffU
0362 #define SPWTDP_DPF_DPF_GET( _reg ) \
0363   ( ( ( _reg ) & SPWTDP_DPF_DPF_MASK ) >> \
0364     SPWTDP_DPF_DPF_SHIFT )
0365 #define SPWTDP_DPF_DPF_SET( _reg, _val ) \
0366   ( ( ( _reg ) & ~SPWTDP_DPF_DPF_MASK ) | \
0367     ( ( ( _val ) << SPWTDP_DPF_DPF_SHIFT ) & \
0368       SPWTDP_DPF_DPF_MASK ) )
0369 #define SPWTDP_DPF_DPF( _val ) \
0370   ( ( ( _val ) << SPWTDP_DPF_DPF_SHIFT ) & \
0371     SPWTDP_DPF_DPF_MASK )
0372
0373 /** @} */
0374
0375 /**
0376  * @defgroup RTEMSDeviceGRLIBSPWTDPDET0 Datation Elapsed Time 0 (DET0)
0377  *
0378  * @brief This group contains register bit definitions.
0379  *
0380  * @{
0381  */
0382
0383 #define SPWTDP_DET0_DET0_SHIFT 0
0384 #define SPWTDP_DET0_DET0_MASK 0xffffffffU
0385 #define SPWTDP_DET0_DET0_GET( _reg ) \
0386   ( ( ( _reg ) & SPWTDP_DET0_DET0_MASK ) >> \
0387     SPWTDP_DET0_DET0_SHIFT )
0388 #define SPWTDP_DET0_DET0_SET( _reg, _val ) \
0389   ( ( ( _reg ) & ~SPWTDP_DET0_DET0_MASK ) | \
0390     ( ( ( _val ) << SPWTDP_DET0_DET0_SHIFT ) & \
0391       SPWTDP_DET0_DET0_MASK ) )
0392 #define SPWTDP_DET0_DET0( _val ) \
0393   ( ( ( _val ) << SPWTDP_DET0_DET0_SHIFT ) & \
0394     SPWTDP_DET0_DET0_MASK )
0395
0396 /** @} */
0397
0398 /**
0399  * @defgroup RTEMSDeviceGRLIBSPWTDPDET1 Datation Elapsed Time 1 (DET1)
0400  *
0401  * @brief This group contains register bit definitions.
0402  *
0403  * @{
0404  */
0405
0406 #define SPWTDP_DET1_DET1_SHIFT 0
0407 #define SPWTDP_DET1_DET1_MASK 0xffffffffU
0408 #define SPWTDP_DET1_DET1_GET( _reg ) \
0409   ( ( ( _reg ) & SPWTDP_DET1_DET1_MASK ) >> \
0410     SPWTDP_DET1_DET1_SHIFT )
0411 #define SPWTDP_DET1_DET1_SET( _reg, _val ) \
0412   ( ( ( _reg ) & ~SPWTDP_DET1_DET1_MASK ) | \
0413     ( ( ( _val ) << SPWTDP_DET1_DET1_SHIFT ) & \
0414       SPWTDP_DET1_DET1_MASK ) )
0415 #define SPWTDP_DET1_DET1( _val ) \
0416   ( ( ( _val ) << SPWTDP_DET1_DET1_SHIFT ) & \
0417     SPWTDP_DET1_DET1_MASK )
0418
0419 /** @} */
0420
0421 /**
0422  * @defgroup RTEMSDeviceGRLIBSPWTDPDET2 Datation Elapsed Time 2 (DET2)
0423  *
0424  * @brief This group contains register bit definitions.
0425  *
0426  * @{
0427  */
0428
0429 #define SPWTDP_DET2_DET2_SHIFT 0
0430 #define SPWTDP_DET2_DET2_MASK 0xffffffffU
0431 #define SPWTDP_DET2_DET2_GET( _reg ) \
0432   ( ( ( _reg ) & SPWTDP_DET2_DET2_MASK ) >> \
0433     SPWTDP_DET2_DET2_SHIFT )
0434 #define SPWTDP_DET2_DET2_SET( _reg, _val ) \
0435   ( ( ( _reg ) & ~SPWTDP_DET2_DET2_MASK ) | \
0436     ( ( ( _val ) << SPWTDP_DET2_DET2_SHIFT ) & \
0437       SPWTDP_DET2_DET2_MASK ) )
0438 #define SPWTDP_DET2_DET2( _val ) \
0439   ( ( ( _val ) << SPWTDP_DET2_DET2_SHIFT ) & \
0440     SPWTDP_DET2_DET2_MASK )
0441
0442 /** @} */
0443
0444 /**
0445  * @defgroup RTEMSDeviceGRLIBSPWTDPDET3 Datation Elapsed Time 3 (DET3)
0446  *
0447  * @brief This group contains register bit definitions.
0448  *
0449  * @{
0450  */
0451
0452 #define SPWTDP_DET3_DET3_SHIFT 0
0453 #define SPWTDP_DET3_DET3_MASK 0xffffffffU
0454 #define SPWTDP_DET3_DET3_GET( _reg ) \
0455   ( ( ( _reg ) & SPWTDP_DET3_DET3_MASK ) >> \
0456     SPWTDP_DET3_DET3_SHIFT )
0457 #define SPWTDP_DET3_DET3_SET( _reg, _val ) \
0458   ( ( ( _reg ) & ~SPWTDP_DET3_DET3_MASK ) | \
0459     ( ( ( _val ) << SPWTDP_DET3_DET3_SHIFT ) & \
0460       SPWTDP_DET3_DET3_MASK ) )
0461 #define SPWTDP_DET3_DET3( _val ) \
0462   ( ( ( _val ) << SPWTDP_DET3_DET3_SHIFT ) & \
0463     SPWTDP_DET3_DET3_MASK )
0464
0465 /** @} */
0466
0467 /**
0468  * @defgroup RTEMSDeviceGRLIBSPWTDPDET4 Datation Elapsed Time 4 (DET4)
0469  *
0470  * @brief This group contains register bit definitions.
0471  *
0472  * @{
0473  */
0474
0475 #define SPWTDP_DET4_DET4_SHIFT 24
0476 #define SPWTDP_DET4_DET4_MASK 0xff000000U
0477 #define SPWTDP_DET4_DET4_GET( _reg ) \
0478   ( ( ( _reg ) & SPWTDP_DET4_DET4_MASK ) >> \
0479     SPWTDP_DET4_DET4_SHIFT )
0480 #define SPWTDP_DET4_DET4_SET( _reg, _val ) \
0481   ( ( ( _reg ) & ~SPWTDP_DET4_DET4_MASK ) | \
0482     ( ( ( _val ) << SPWTDP_DET4_DET4_SHIFT ) & \
0483       SPWTDP_DET4_DET4_MASK ) )
0484 #define SPWTDP_DET4_DET4( _val ) \
0485   ( ( ( _val ) << SPWTDP_DET4_DET4_SHIFT ) & \
0486     SPWTDP_DET4_DET4_MASK )
0487
0488 /** @} */
0489
0490 /**
0491  * @defgroup RTEMSDeviceGRLIBSPWTDPTRPFRX Time-Stamp Preamble Field Rx (TRPFRX)
0492  *
0493  * @brief This group contains register bit definitions.
0494  *
0495  * @{
0496  */
0497
0498 #define SPWTDP_TRPFRX_TRPF_SHIFT 0
0499 #define SPWTDP_TRPFRX_TRPF_MASK 0xffffU
0500 #define SPWTDP_TRPFRX_TRPF_GET( _reg ) \
0501   ( ( ( _reg ) & SPWTDP_TRPFRX_TRPF_MASK ) >> \
0502     SPWTDP_TRPFRX_TRPF_SHIFT )
0503 #define SPWTDP_TRPFRX_TRPF_SET( _reg, _val ) \
0504   ( ( ( _reg ) & ~SPWTDP_TRPFRX_TRPF_MASK ) | \
0505     ( ( ( _val ) << SPWTDP_TRPFRX_TRPF_SHIFT ) & \
0506       SPWTDP_TRPFRX_TRPF_MASK ) )
0507 #define SPWTDP_TRPFRX_TRPF( _val ) \
0508   ( ( ( _val ) << SPWTDP_TRPFRX_TRPF_SHIFT ) & \
0509     SPWTDP_TRPFRX_TRPF_MASK )
0510
0511 /** @} */
0512
0513 /**
0514  * @defgroup RTEMSDeviceGRLIBSPWTDPTR0 Time Stamp Elapsed Time 0 Rx (TR0)
0515  *
0516  * @brief This group contains register bit definitions.
0517  *
0518  * @{
0519  */
0520
0521 #define SPWTDP_TR0_TR0_SHIFT 0
0522 #define SPWTDP_TR0_TR0_MASK 0xffffffffU
0523 #define SPWTDP_TR0_TR0_GET( _reg ) \
0524   ( ( ( _reg ) & SPWTDP_TR0_TR0_MASK ) >> \
0525     SPWTDP_TR0_TR0_SHIFT )
0526 #define SPWTDP_TR0_TR0_SET( _reg, _val ) \
0527   ( ( ( _reg ) & ~SPWTDP_TR0_TR0_MASK ) | \
0528     ( ( ( _val ) << SPWTDP_TR0_TR0_SHIFT ) & \
0529       SPWTDP_TR0_TR0_MASK ) )
0530 #define SPWTDP_TR0_TR0( _val ) \
0531   ( ( ( _val ) << SPWTDP_TR0_TR0_SHIFT ) & \
0532     SPWTDP_TR0_TR0_MASK )
0533
0534 /** @} */
0535
0536 /**
0537  * @defgroup RTEMSDeviceGRLIBSPWTDPTR1 Time Stamp Elapsed Time 1 Rx (TR1)
0538  *
0539  * @brief This group contains register bit definitions.
0540  *
0541  * @{
0542  */
0543
0544 #define SPWTDP_TR1_TR1_SHIFT 0
0545 #define SPWTDP_TR1_TR1_MASK 0xffffffffU
0546 #define SPWTDP_TR1_TR1_GET( _reg ) \
0547   ( ( ( _reg ) & SPWTDP_TR1_TR1_MASK ) >> \
0548     SPWTDP_TR1_TR1_SHIFT )
0549 #define SPWTDP_TR1_TR1_SET( _reg, _val ) \
0550   ( ( ( _reg ) & ~SPWTDP_TR1_TR1_MASK ) | \
0551     ( ( ( _val ) << SPWTDP_TR1_TR1_SHIFT ) & \
0552       SPWTDP_TR1_TR1_MASK ) )
0553 #define SPWTDP_TR1_TR1( _val ) \
0554   ( ( ( _val ) << SPWTDP_TR1_TR1_SHIFT ) & \
0555     SPWTDP_TR1_TR1_MASK )
0556
0557 /** @} */
0558
0559 /**
0560  * @defgroup RTEMSDeviceGRLIBSPWTDPTR2 Time Stamp Elapsed Time 2 Rx (TR2)
0561  *
0562  * @brief This group contains register bit definitions.
0563  *
0564  * @{
0565  */
0566
0567 #define SPWTDP_TR2_TR2_SHIFT 0
0568 #define SPWTDP_TR2_TR2_MASK 0xffffffffU
0569 #define SPWTDP_TR2_TR2_GET( _reg ) \
0570   ( ( ( _reg ) & SPWTDP_TR2_TR2_MASK ) >> \
0571     SPWTDP_TR2_TR2_SHIFT )
0572 #define SPWTDP_TR2_TR2_SET( _reg, _val ) \
0573   ( ( ( _reg ) & ~SPWTDP_TR2_TR2_MASK ) | \
0574     ( ( ( _val ) << SPWTDP_TR2_TR2_SHIFT ) & \
0575       SPWTDP_TR2_TR2_MASK ) )
0576 #define SPWTDP_TR2_TR2( _val ) \
0577   ( ( ( _val ) << SPWTDP_TR2_TR2_SHIFT ) & \
0578     SPWTDP_TR2_TR2_MASK )
0579
0580 /** @} */
0581
0582 /**
0583  * @defgroup RTEMSDeviceGRLIBSPWTDPTR3 Time Stamp Elapsed Time 3 Rx (TR3)
0584  *
0585  * @brief This group contains register bit definitions.
0586  *
0587  * @{
0588  */
0589
0590 #define SPWTDP_TR3_TR3_SHIFT 0
0591 #define SPWTDP_TR3_TR3_MASK 0xffffffffU
0592 #define SPWTDP_TR3_TR3_GET( _reg ) \
0593   ( ( ( _reg ) & SPWTDP_TR3_TR3_MASK ) >> \
0594     SPWTDP_TR3_TR3_SHIFT )
0595 #define SPWTDP_TR3_TR3_SET( _reg, _val ) \
0596   ( ( ( _reg ) & ~SPWTDP_TR3_TR3_MASK ) | \
0597     ( ( ( _val ) << SPWTDP_TR3_TR3_SHIFT ) & \
0598       SPWTDP_TR3_TR3_MASK ) )
0599 #define SPWTDP_TR3_TR3( _val ) \
0600   ( ( ( _val ) << SPWTDP_TR3_TR3_SHIFT ) & \
0601     SPWTDP_TR3_TR3_MASK )
0602
0603 /** @} */
0604
0605 /**
0606  * @defgroup RTEMSDeviceGRLIBSPWTDPTR4 Time Stamp Elapsed Time 4 Rx (TR4)
0607  *
0608  * @brief This group contains register bit definitions.
0609  *
0610  * @{
0611  */
0612
0613 #define SPWTDP_TR4_TR4_SHIFT 24
0614 #define SPWTDP_TR4_TR4_MASK 0xff000000U
0615 #define SPWTDP_TR4_TR4_GET( _reg ) \
0616   ( ( ( _reg ) & SPWTDP_TR4_TR4_MASK ) >> \
0617     SPWTDP_TR4_TR4_SHIFT )
0618 #define SPWTDP_TR4_TR4_SET( _reg, _val ) \
0619   ( ( ( _reg ) & ~SPWTDP_TR4_TR4_MASK ) | \
0620     ( ( ( _val ) << SPWTDP_TR4_TR4_SHIFT ) & \
0621       SPWTDP_TR4_TR4_MASK ) )
0622 #define SPWTDP_TR4_TR4( _val ) \
0623   ( ( ( _val ) << SPWTDP_TR4_TR4_SHIFT ) & \
0624     SPWTDP_TR4_TR4_MASK )
0625
0626 /** @} */
0627
0628 /**
0629  * @defgroup RTEMSDeviceGRLIBSPWTDPTTPFTX \
0630  *   Time-Stamp SpaceWire Time-Code and Preamble Field Tx (TTPFTX)
0631  *
0632  * @brief This group contains register bit definitions.
0633  *
0634  * @{
0635  */
0636
0637 #define SPWTDP_TTPFTX_TSTC_SHIFT 24
0638 #define SPWTDP_TTPFTX_TSTC_MASK 0xff000000U
0639 #define SPWTDP_TTPFTX_TSTC_GET( _reg ) \
0640   ( ( ( _reg ) & SPWTDP_TTPFTX_TSTC_MASK ) >> \
0641     SPWTDP_TTPFTX_TSTC_SHIFT )
0642 #define SPWTDP_TTPFTX_TSTC_SET( _reg, _val ) \
0643   ( ( ( _reg ) & ~SPWTDP_TTPFTX_TSTC_MASK ) | \
0644     ( ( ( _val ) << SPWTDP_TTPFTX_TSTC_SHIFT ) & \
0645       SPWTDP_TTPFTX_TSTC_MASK ) )
0646 #define SPWTDP_TTPFTX_TSTC( _val ) \
0647   ( ( ( _val ) << SPWTDP_TTPFTX_TSTC_SHIFT ) & \
0648     SPWTDP_TTPFTX_TSTC_MASK )
0649
0650 #define SPWTDP_TTPFTX_TTPF_SHIFT 0
0651 #define SPWTDP_TTPFTX_TTPF_MASK 0xffffU
0652 #define SPWTDP_TTPFTX_TTPF_GET( _reg ) \
0653   ( ( ( _reg ) & SPWTDP_TTPFTX_TTPF_MASK ) >> \
0654     SPWTDP_TTPFTX_TTPF_SHIFT )
0655 #define SPWTDP_TTPFTX_TTPF_SET( _reg, _val ) \
0656   ( ( ( _reg ) & ~SPWTDP_TTPFTX_TTPF_MASK ) | \
0657     ( ( ( _val ) << SPWTDP_TTPFTX_TTPF_SHIFT ) & \
0658       SPWTDP_TTPFTX_TTPF_MASK ) )
0659 #define SPWTDP_TTPFTX_TTPF( _val ) \
0660   ( ( ( _val ) << SPWTDP_TTPFTX_TTPF_SHIFT ) & \
0661     SPWTDP_TTPFTX_TTPF_MASK )
0662
0663 /** @} */
0664
0665 /**
0666  * @defgroup RTEMSDeviceGRLIBSPWTDPTT0 Time Stamp Elapsed Time 0 Tx (TT0)
0667  *
0668  * @brief This group contains register bit definitions.
0669  *
0670  * @{
0671  */
0672
0673 #define SPWTDP_TT0_TT0_SHIFT 0
0674 #define SPWTDP_TT0_TT0_MASK 0xffffffffU
0675 #define SPWTDP_TT0_TT0_GET( _reg ) \
0676   ( ( ( _reg ) & SPWTDP_TT0_TT0_MASK ) >> \
0677     SPWTDP_TT0_TT0_SHIFT )
0678 #define SPWTDP_TT0_TT0_SET( _reg, _val ) \
0679   ( ( ( _reg ) & ~SPWTDP_TT0_TT0_MASK ) | \
0680     ( ( ( _val ) << SPWTDP_TT0_TT0_SHIFT ) & \
0681       SPWTDP_TT0_TT0_MASK ) )
0682 #define SPWTDP_TT0_TT0( _val ) \
0683   ( ( ( _val ) << SPWTDP_TT0_TT0_SHIFT ) & \
0684     SPWTDP_TT0_TT0_MASK )
0685
0686 /** @} */
0687
0688 /**
0689  * @defgroup RTEMSDeviceGRLIBSPWTDPTT1 Time Stamp Elapsed Time 1 Tx (TT1)
0690  *
0691  * @brief This group contains register bit definitions.
0692  *
0693  * @{
0694  */
0695
0696 #define SPWTDP_TT1_TT1_SHIFT 0
0697 #define SPWTDP_TT1_TT1_MASK 0xffffffffU
0698 #define SPWTDP_TT1_TT1_GET( _reg ) \
0699   ( ( ( _reg ) & SPWTDP_TT1_TT1_MASK ) >> \
0700     SPWTDP_TT1_TT1_SHIFT )
0701 #define SPWTDP_TT1_TT1_SET( _reg, _val ) \
0702   ( ( ( _reg ) & ~SPWTDP_TT1_TT1_MASK ) | \
0703     ( ( ( _val ) << SPWTDP_TT1_TT1_SHIFT ) & \
0704       SPWTDP_TT1_TT1_MASK ) )
0705 #define SPWTDP_TT1_TT1( _val ) \
0706   ( ( ( _val ) << SPWTDP_TT1_TT1_SHIFT ) & \
0707     SPWTDP_TT1_TT1_MASK )
0708
0709 /** @} */
0710
0711 /**
0712  * @defgroup RTEMSDeviceGRLIBSPWTDPTT2 Time Stamp Elapsed Time 2 Tx (TT2)
0713  *
0714  * @brief This group contains register bit definitions.
0715  *
0716  * @{
0717  */
0718
0719 #define SPWTDP_TT2_TT2_SHIFT 0
0720 #define SPWTDP_TT2_TT2_MASK 0xffffffffU
0721 #define SPWTDP_TT2_TT2_GET( _reg ) \
0722   ( ( ( _reg ) & SPWTDP_TT2_TT2_MASK ) >> \
0723     SPWTDP_TT2_TT2_SHIFT )
0724 #define SPWTDP_TT2_TT2_SET( _reg, _val ) \
0725   ( ( ( _reg ) & ~SPWTDP_TT2_TT2_MASK ) | \
0726     ( ( ( _val ) << SPWTDP_TT2_TT2_SHIFT ) & \
0727       SPWTDP_TT2_TT2_MASK ) )
0728 #define SPWTDP_TT2_TT2( _val ) \
0729   ( ( ( _val ) << SPWTDP_TT2_TT2_SHIFT ) & \
0730     SPWTDP_TT2_TT2_MASK )
0731
0732 /** @} */
0733
0734 /**
0735  * @defgroup RTEMSDeviceGRLIBSPWTDPTT3 Time Stamp Elapsed Time 3 Tx (TT3)
0736  *
0737  * @brief This group contains register bit definitions.
0738  *
0739  * @{
0740  */
0741
0742 #define SPWTDP_TT3_TT3_SHIFT 0
0743 #define SPWTDP_TT3_TT3_MASK 0xffffffffU
0744 #define SPWTDP_TT3_TT3_GET( _reg ) \
0745   ( ( ( _reg ) & SPWTDP_TT3_TT3_MASK ) >> \
0746     SPWTDP_TT3_TT3_SHIFT )
0747 #define SPWTDP_TT3_TT3_SET( _reg, _val ) \
0748   ( ( ( _reg ) & ~SPWTDP_TT3_TT3_MASK ) | \
0749     ( ( ( _val ) << SPWTDP_TT3_TT3_SHIFT ) & \
0750       SPWTDP_TT3_TT3_MASK ) )
0751 #define SPWTDP_TT3_TT3( _val ) \
0752   ( ( ( _val ) << SPWTDP_TT3_TT3_SHIFT ) & \
0753     SPWTDP_TT3_TT3_MASK )
0754
0755 /** @} */
0756
0757 /**
0758  * @defgroup RTEMSDeviceGRLIBSPWTDPTT4 Time Stamp Elapsed Time 4 Tx (TT4)
0759  *
0760  * @brief This group contains register bit definitions.
0761  *
0762  * @{
0763  */
0764
0765 #define SPWTDP_TT4_TT4_SHIFT 24
0766 #define SPWTDP_TT4_TT4_MASK 0xff000000U
0767 #define SPWTDP_TT4_TT4_GET( _reg ) \
0768   ( ( ( _reg ) & SPWTDP_TT4_TT4_MASK ) >> \
0769     SPWTDP_TT4_TT4_SHIFT )
0770 #define SPWTDP_TT4_TT4_SET( _reg, _val ) \
0771   ( ( ( _reg ) & ~SPWTDP_TT4_TT4_MASK ) | \
0772     ( ( ( _val ) << SPWTDP_TT4_TT4_SHIFT ) & \
0773       SPWTDP_TT4_TT4_MASK ) )
0774 #define SPWTDP_TT4_TT4( _val ) \
0775   ( ( ( _val ) << SPWTDP_TT4_TT4_SHIFT ) & \
0776     SPWTDP_TT4_TT4_MASK )
0777
0778 /** @} */
0779
0780 /**
0781  * @defgroup RTEMSDeviceGRLIBSPWTDPLPF Latency Preamble Field (LPF)
0782  *
0783  * @brief This group contains register bit definitions.
0784  *
0785  * @{
0786  */
0787
0788 #define SPWTDP_LPF_LPF_SHIFT 0
0789 #define SPWTDP_LPF_LPF_MASK 0xffffU
0790 #define SPWTDP_LPF_LPF_GET( _reg ) \
0791   ( ( ( _reg ) & SPWTDP_LPF_LPF_MASK ) >> \
0792     SPWTDP_LPF_LPF_SHIFT )
0793 #define SPWTDP_LPF_LPF_SET( _reg, _val ) \
0794   ( ( ( _reg ) & ~SPWTDP_LPF_LPF_MASK ) | \
0795     ( ( ( _val ) << SPWTDP_LPF_LPF_SHIFT ) & \
0796       SPWTDP_LPF_LPF_MASK ) )
0797 #define SPWTDP_LPF_LPF( _val ) \
0798   ( ( ( _val ) << SPWTDP_LPF_LPF_SHIFT ) & \
0799     SPWTDP_LPF_LPF_MASK )
0800
0801 /** @} */
0802
0803 /**
0804  * @defgroup RTEMSDeviceGRLIBSPWTDPIE Interrupt Enable (IE)
0805  *
0806  * @brief This group contains register bit definitions.
0807  *
0808  * @{
0809  */
0810
0811 #define SPWTDP_IE_NCTCE 0x80000U
0812
0813 #define SPWTDP_IE_SETE 0x400U
0814
0815 #define SPWTDP_IE_EDIE3 0x200U
0816
0817 #define SPWTDP_IE_EDIE2 0x100U
0818
0819 #define SPWTDP_IE_EDIE1 0x80U
0820
0821 #define SPWTDP_IE_EDIE0 0x40U
0822
0823 #define SPWTDP_IE_DITE 0x20U
0824
0825 #define SPWTDP_IE_DIRE 0x10U
0826
0827 #define SPWTDP_IE_TTE 0x8U
0828
0829 #define SPWTDP_IE_TME 0x4U
0830
0831 #define SPWTDP_IE_TRE 0x2U
0832
0833 #define SPWTDP_IE_SE 0x1U
0834
0835 /** @} */
0836
0837 /**
0838  * @defgroup RTEMSDeviceGRLIBSPWTDPDC Delay Count (DC)
0839  *
0840  * @brief This group contains register bit definitions.
0841  *
0842  * @{
0843  */
0844
0845 #define SPWTDP_DC_DC_SHIFT 0
0846 #define SPWTDP_DC_DC_MASK 0x7fffU
0847 #define SPWTDP_DC_DC_GET( _reg ) \
0848   ( ( ( _reg ) & SPWTDP_DC_DC_MASK ) >> \
0849     SPWTDP_DC_DC_SHIFT )
0850 #define SPWTDP_DC_DC_SET( _reg, _val ) \
0851   ( ( ( _reg ) & ~SPWTDP_DC_DC_MASK ) | \
0852     ( ( ( _val ) << SPWTDP_DC_DC_SHIFT ) & \
0853       SPWTDP_DC_DC_MASK ) )
0854 #define SPWTDP_DC_DC( _val ) \
0855   ( ( ( _val ) << SPWTDP_DC_DC_SHIFT ) & \
0856     SPWTDP_DC_DC_MASK )
0857
0858 /** @} */
0859
0860 /**
0861  * @defgroup RTEMSDeviceGRLIBSPWTDPDS Disable Sync (DS)
0862  *
0863  * @brief This group contains register bit definitions.
0864  *
0865  * @{
0866  */
0867
0868 #define SPWTDP_DS_EN 0x80000000U
0869
0870 #define SPWTDP_DS_CD_SHIFT 0
0871 #define SPWTDP_DS_CD_MASK 0xffffffU
0872 #define SPWTDP_DS_CD_GET( _reg ) \
0873   ( ( ( _reg ) & SPWTDP_DS_CD_MASK ) >> \
0874     SPWTDP_DS_CD_SHIFT )
0875 #define SPWTDP_DS_CD_SET( _reg, _val ) \
0876   ( ( ( _reg ) & ~SPWTDP_DS_CD_MASK ) | \
0877     ( ( ( _val ) << SPWTDP_DS_CD_SHIFT ) & \
0878       SPWTDP_DS_CD_MASK ) )
0879 #define SPWTDP_DS_CD( _val ) \
0880   ( ( ( _val ) << SPWTDP_DS_CD_SHIFT ) & \
0881     SPWTDP_DS_CD_MASK )
0882
0883 /** @} */
0884
0885 /**
0886  * @defgroup RTEMSDeviceGRLIBSPWTDPEDM0 External Datation 0 Mask (EDM0)
0887  *
0888  * @brief This group contains register bit definitions.
0889  *
0890  * @{
0891  */
0892
0893 #define SPWTDP_EDM0_EDM0_SHIFT 0
0894 #define SPWTDP_EDM0_EDM0_MASK 0xffffffffU
0895 #define SPWTDP_EDM0_EDM0_GET( _reg ) \
0896   ( ( ( _reg ) & SPWTDP_EDM0_EDM0_MASK ) >> \
0897     SPWTDP_EDM0_EDM0_SHIFT )
0898 #define SPWTDP_EDM0_EDM0_SET( _reg, _val ) \
0899   ( ( ( _reg ) & ~SPWTDP_EDM0_EDM0_MASK ) | \
0900     ( ( ( _val ) << SPWTDP_EDM0_EDM0_SHIFT ) & \
0901       SPWTDP_EDM0_EDM0_MASK ) )
0902 #define SPWTDP_EDM0_EDM0( _val ) \
0903   ( ( ( _val ) << SPWTDP_EDM0_EDM0_SHIFT ) & \
0904     SPWTDP_EDM0_EDM0_MASK )
0905
0906 /** @} */
0907
0908 /**
0909  * @defgroup RTEMSDeviceGRLIBSPWTDPEDPF0 \
0910  *   External Datation 0 Preamble Field (EDPF0)
0911  *
0912  * @brief This group contains register bit definitions.
0913  *
0914  * @{
0915  */
0916
0917 #define SPWTDP_EDPF0_EDPF0_SHIFT 0
0918 #define SPWTDP_EDPF0_EDPF0_MASK 0xffffU
0919 #define SPWTDP_EDPF0_EDPF0_GET( _reg ) \
0920   ( ( ( _reg ) & SPWTDP_EDPF0_EDPF0_MASK ) >> \
0921     SPWTDP_EDPF0_EDPF0_SHIFT )
0922 #define SPWTDP_EDPF0_EDPF0_SET( _reg, _val ) \
0923   ( ( ( _reg ) & ~SPWTDP_EDPF0_EDPF0_MASK ) | \
0924     ( ( ( _val ) << SPWTDP_EDPF0_EDPF0_SHIFT ) & \
0925       SPWTDP_EDPF0_EDPF0_MASK ) )
0926 #define SPWTDP_EDPF0_EDPF0( _val ) \
0927   ( ( ( _val ) << SPWTDP_EDPF0_EDPF0_SHIFT ) & \
0928     SPWTDP_EDPF0_EDPF0_MASK )
0929
0930 /** @} */
0931
0932 /**
0933  * @defgroup RTEMSDeviceGRLIBSPWTDPED0ET0 \
0934  *   External Datation 0 Elapsed Time 0 (ED0ET0)
0935  *
0936  * @brief This group contains register bit definitions.
0937  *
0938  * @{
0939  */
0940
0941 #define SPWTDP_ED0ET0_ED0ET0_SHIFT 0
0942 #define SPWTDP_ED0ET0_ED0ET0_MASK 0xffffffffU
0943 #define SPWTDP_ED0ET0_ED0ET0_GET( _reg ) \
0944   ( ( ( _reg ) & SPWTDP_ED0ET0_ED0ET0_MASK ) >> \
0945     SPWTDP_ED0ET0_ED0ET0_SHIFT )
0946 #define SPWTDP_ED0ET0_ED0ET0_SET( _reg, _val ) \
0947   ( ( ( _reg ) & ~SPWTDP_ED0ET0_ED0ET0_MASK ) | \
0948     ( ( ( _val ) << SPWTDP_ED0ET0_ED0ET0_SHIFT ) & \
0949       SPWTDP_ED0ET0_ED0ET0_MASK ) )
0950 #define SPWTDP_ED0ET0_ED0ET0( _val ) \
0951   ( ( ( _val ) << SPWTDP_ED0ET0_ED0ET0_SHIFT ) & \
0952     SPWTDP_ED0ET0_ED0ET0_MASK )
0953
0954 /** @} */
0955
0956 /**
0957  * @defgroup RTEMSDeviceGRLIBSPWTDPED0ET1 \
0958  *   External Datation 0 Elapsed Time 1 (ED0ET1)
0959  *
0960  * @brief This group contains register bit definitions.
0961  *
0962  * @{
0963  */
0964
0965 #define SPWTDP_ED0ET1_ED0ET1_SHIFT 0
0966 #define SPWTDP_ED0ET1_ED0ET1_MASK 0xffffffffU
0967 #define SPWTDP_ED0ET1_ED0ET1_GET( _reg ) \
0968   ( ( ( _reg ) & SPWTDP_ED0ET1_ED0ET1_MASK ) >> \
0969     SPWTDP_ED0ET1_ED0ET1_SHIFT )
0970 #define SPWTDP_ED0ET1_ED0ET1_SET( _reg, _val ) \
0971   ( ( ( _reg ) & ~SPWTDP_ED0ET1_ED0ET1_MASK ) | \
0972     ( ( ( _val ) << SPWTDP_ED0ET1_ED0ET1_SHIFT ) & \
0973       SPWTDP_ED0ET1_ED0ET1_MASK ) )
0974 #define SPWTDP_ED0ET1_ED0ET1( _val ) \
0975   ( ( ( _val ) << SPWTDP_ED0ET1_ED0ET1_SHIFT ) & \
0976     SPWTDP_ED0ET1_ED0ET1_MASK )
0977
0978 /** @} */
0979
0980 /**
0981  * @defgroup RTEMSDeviceGRLIBSPWTDPED0ET2 \
0982  *   External Datation 0 Elapsed Time 2 (ED0ET2)
0983  *
0984  * @brief This group contains register bit definitions.
0985  *
0986  * @{
0987  */
0988
0989 #define SPWTDP_ED0ET2_ED0ET2_SHIFT 0
0990 #define SPWTDP_ED0ET2_ED0ET2_MASK 0xffffffffU
0991 #define SPWTDP_ED0ET2_ED0ET2_GET( _reg ) \
0992   ( ( ( _reg ) & SPWTDP_ED0ET2_ED0ET2_MASK ) >> \
0993     SPWTDP_ED0ET2_ED0ET2_SHIFT )
0994 #define SPWTDP_ED0ET2_ED0ET2_SET( _reg, _val ) \
0995   ( ( ( _reg ) & ~SPWTDP_ED0ET2_ED0ET2_MASK ) | \
0996     ( ( ( _val ) << SPWTDP_ED0ET2_ED0ET2_SHIFT ) & \
0997       SPWTDP_ED0ET2_ED0ET2_MASK ) )
0998 #define SPWTDP_ED0ET2_ED0ET2( _val ) \
0999   ( ( ( _val ) << SPWTDP_ED0ET2_ED0ET2_SHIFT ) & \
1000     SPWTDP_ED0ET2_ED0ET2_MASK )
1001
1002 /** @} */
1003
1004 /**
1005  * @defgroup RTEMSDeviceGRLIBSPWTDPED0ET3 \
1006  *   External Datation 0 Elapsed Time 3 (ED0ET3)
1007  *
1008  * @brief This group contains register bit definitions.
1009  *
1010  * @{
1011  */
1012
1013 #define SPWTDP_ED0ET3_ED0ET3_SHIFT 0
1014 #define SPWTDP_ED0ET3_ED0ET3_MASK 0xffffffffU
1015 #define SPWTDP_ED0ET3_ED0ET3_GET( _reg ) \
1016   ( ( ( _reg ) & SPWTDP_ED0ET3_ED0ET3_MASK ) >> \
1017     SPWTDP_ED0ET3_ED0ET3_SHIFT )
1018 #define SPWTDP_ED0ET3_ED0ET3_SET( _reg, _val ) \
1019   ( ( ( _reg ) & ~SPWTDP_ED0ET3_ED0ET3_MASK ) | \
1020     ( ( ( _val ) << SPWTDP_ED0ET3_ED0ET3_SHIFT ) & \
1021       SPWTDP_ED0ET3_ED0ET3_MASK ) )
1022 #define SPWTDP_ED0ET3_ED0ET3( _val ) \
1023   ( ( ( _val ) << SPWTDP_ED0ET3_ED0ET3_SHIFT ) & \
1024     SPWTDP_ED0ET3_ED0ET3_MASK )
1025
1026 /** @} */
1027
1028 /**
1029  * @defgroup RTEMSDeviceGRLIBSPWTDPED0ET4 \
1030  *   External Datation 0 Elapsed Time 4 (ED0ET4)
1031  *
1032  * @brief This group contains register bit definitions.
1033  *
1034  * @{
1035  */
1036
1037 #define SPWTDP_ED0ET4_ED0ET4_SHIFT 24
1038 #define SPWTDP_ED0ET4_ED0ET4_MASK 0xff000000U
1039 #define SPWTDP_ED0ET4_ED0ET4_GET( _reg ) \
1040   ( ( ( _reg ) & SPWTDP_ED0ET4_ED0ET4_MASK ) >> \
1041     SPWTDP_ED0ET4_ED0ET4_SHIFT )
1042 #define SPWTDP_ED0ET4_ED0ET4_SET( _reg, _val ) \
1043   ( ( ( _reg ) & ~SPWTDP_ED0ET4_ED0ET4_MASK ) | \
1044     ( ( ( _val ) << SPWTDP_ED0ET4_ED0ET4_SHIFT ) & \
1045       SPWTDP_ED0ET4_ED0ET4_MASK ) )
1046 #define SPWTDP_ED0ET4_ED0ET4( _val ) \
1047   ( ( ( _val ) << SPWTDP_ED0ET4_ED0ET4_SHIFT ) & \
1048     SPWTDP_ED0ET4_ED0ET4_MASK )
1049
1050 /** @} */
1051
1052 /**
1053  * @brief This structure defines the SPWTDP register block memory map.
1054  */
1055 typedef struct spwtdp {
1056   /**
1057    * @brief See @ref RTEMSDeviceGRLIBSPWTDPCONF0.
1058    */
1059   uint32_t conf0;
1060
1061   uint32_t reserved_4_c[ 2 ];
1062
1063   /**
1064    * @brief See @ref RTEMSDeviceGRLIBSPWTDPCONF3.
1065    */
1066   uint32_t conf3;
1067
1068   uint32_t reserved_10_20[ 4 ];
1069
1070   /**
1071    * @brief See @ref RTEMSDeviceGRLIBSPWTDPCTRL.
1072    */
1073   uint32_t ctrl;
1074
1075   /**
1076    * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET0.
1077    */
1078   uint32_t cet0;
1079
1080   /**
1081    * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET1.
1082    */
1083   uint32_t cet1;
1084
1085   /**
1086    * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET2.
1087    */
1088   uint32_t cet2;
1089
1090   /**
1091    * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET3.
1092    */
1093   uint32_t cet3;
1094
1095   /**
1096    * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET4.
1097    */
1098   uint32_t cet4;
1099
1100   uint32_t reserved_38_40[ 2 ];
1101
1102   /**
1103    * @brief See @ref RTEMSDeviceGRLIBSPWTDPDPF.
1104    */
1105   uint32_t dpf;
1106
1107   /**
1108    * @brief See @ref RTEMSDeviceGRLIBSPWTDPDET0.
1109    */
1110   uint32_t det0;
1111
1112   /**
1113    * @brief See @ref RTEMSDeviceGRLIBSPWTDPDET1.
1114    */
1115   uint32_t det1;
1116
1117   /**
1118    * @brief See @ref RTEMSDeviceGRLIBSPWTDPDET2.
1119    */
1120   uint32_t det2;
1121
1122   /**
1123    * @brief See @ref RTEMSDeviceGRLIBSPWTDPDET3.
1124    */
1125   uint32_t det3;
1126
1127   /**
1128    * @brief See @ref RTEMSDeviceGRLIBSPWTDPDET4.
1129    */
1130   uint32_t det4;
1131
1132   uint32_t reserved_58_60[ 2 ];
1133
1134   /**
1135    * @brief See @ref RTEMSDeviceGRLIBSPWTDPTRPFRX.
1136    */
1137   uint32_t trpfrx;
1138
1139   /**
1140    * @brief See @ref RTEMSDeviceGRLIBSPWTDPTR0.
1141    */
1142   uint32_t tr0;
1143
1144   /**
1145    * @brief See @ref RTEMSDeviceGRLIBSPWTDPTR1.
1146    */
1147   uint32_t tr1;
1148
1149   /**
1150    * @brief See @ref RTEMSDeviceGRLIBSPWTDPTR2.
1151    */
1152   uint32_t tr2;
1153
1154   /**
1155    * @brief See @ref RTEMSDeviceGRLIBSPWTDPTR3.
1156    */
1157   uint32_t tr3;
1158
1159   /**
1160    * @brief See @ref RTEMSDeviceGRLIBSPWTDPTR4.
1161    */
1162   uint32_t tr4;
1163
1164   uint32_t reserved_78_80[ 2 ];
1165
1166   /**
1167    * @brief See @ref RTEMSDeviceGRLIBSPWTDPTTPFTX.
1168    */
1169   uint32_t ttpftx;
1170
1171   /**
1172    * @brief See @ref RTEMSDeviceGRLIBSPWTDPTT0.
1173    */
1174   uint32_t tt0;
1175
1176   /**
1177    * @brief See @ref RTEMSDeviceGRLIBSPWTDPTT1.
1178    */
1179   uint32_t tt1;
1180
1181   /**
1182    * @brief See @ref RTEMSDeviceGRLIBSPWTDPTT2.
1183    */
1184   uint32_t tt2;
1185
1186   /**
1187    * @brief See @ref RTEMSDeviceGRLIBSPWTDPTT3.
1188    */
1189   uint32_t tt3;
1190
1191   /**
1192    * @brief See @ref RTEMSDeviceGRLIBSPWTDPTT4.
1193    */
1194   uint32_t tt4;
1195
1196   uint32_t reserved_98_a0[ 2 ];
1197
1198   /**
1199    * @brief See @ref RTEMSDeviceGRLIBSPWTDPLPF.
1200    */
1201   uint32_t lpf;
1202
1203   uint32_t reserved_a4_c0[ 7 ];
1204
1205   /**
1206    * @brief See @ref RTEMSDeviceGRLIBSPWTDPIE.
1207    */
1208   uint32_t ie;
1209
1210   uint32_t reserved_c4_c8;
1211
1212   /**
1213    * @brief See @ref RTEMSDeviceGRLIBSPWTDPDC.
1214    */
1215   uint32_t dc;
1216
1217   /**
1218    * @brief See @ref RTEMSDeviceGRLIBSPWTDPDS.
1219    */
1220   uint32_t ds;
1221
1222   uint32_t reserved_d0_100[ 12 ];
1223
1224   /**
1225    * @brief See @ref RTEMSDeviceGRLIBSPWTDPEDM0.
1226    */
1227   uint32_t edm0;
1228
1229   uint32_t reserved_104_110[ 3 ];
1230
1231   /**
1232    * @brief See @ref RTEMSDeviceGRLIBSPWTDPEDPF0.
1233    */
1234   uint32_t edpf0;
1235
1236   /**
1237    * @brief See @ref RTEMSDeviceGRLIBSPWTDPED0ET0.
1238    */
1239   uint32_t ed0et0;
1240
1241   /**
1242    * @brief See @ref RTEMSDeviceGRLIBSPWTDPED0ET1.
1243    */
1244   uint32_t ed0et1;
1245
1246   /**
1247    * @brief See @ref RTEMSDeviceGRLIBSPWTDPED0ET2.
1248    */
1249   uint32_t ed0et2;
1250
1251   /**
1252    * @brief See @ref RTEMSDeviceGRLIBSPWTDPED0ET3.
1253    */
1254   uint32_t ed0et3;
1255
1256   /**
1257    * @brief See @ref RTEMSDeviceGRLIBSPWTDPED0ET4.
1258    */
1259   uint32_t ed0et4;
1260 } spwtdp;
1261
1262 /** @} */
1263
1264 #ifdef __cplusplus
1265 }
1266 #endif
1267
1268 #endif /* _GRLIB_SPWTDP_REGS_H */