include/grlib/spictrl-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRLIBSPICTRL
0007  *
0008  * @brief This header file defines the SPICTRL register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/spictrl-header */
0054
0055 #ifndef _GRLIB_SPICTRL_REGS_H
0056 #define _GRLIB_SPICTRL_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/spictrl */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRLIBSPICTRL SPICTRL
0068  *
0069  * @ingroup RTEMSDeviceGRLIB
0070  *
0071  * @brief This group contains the SPICTRL interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRLIBSPICTRLCAP Capability register (CAP)
0078  *
0079  * @brief This group contains register bit definitions.
0080  *
0081  * @{
0082  */
0083
0084 #define SPICTRL_CAP_SSSZ_SHIFT 24
0085 #define SPICTRL_CAP_SSSZ_MASK 0xff000000U
0086 #define SPICTRL_CAP_SSSZ_GET( _reg ) \
0087   ( ( ( _reg ) & SPICTRL_CAP_SSSZ_MASK ) >> \
0088     SPICTRL_CAP_SSSZ_SHIFT )
0089 #define SPICTRL_CAP_SSSZ_SET( _reg, _val ) \
0090   ( ( ( _reg ) & ~SPICTRL_CAP_SSSZ_MASK ) | \
0091     ( ( ( _val ) << SPICTRL_CAP_SSSZ_SHIFT ) & \
0092       SPICTRL_CAP_SSSZ_MASK ) )
0093 #define SPICTRL_CAP_SSSZ( _val ) \
0094   ( ( ( _val ) << SPICTRL_CAP_SSSZ_SHIFT ) & \
0095     SPICTRL_CAP_SSSZ_MASK )
0096
0097 #define SPICTRL_CAP_MAXWLEN_SHIFT 20
0098 #define SPICTRL_CAP_MAXWLEN_MASK 0xf00000U
0099 #define SPICTRL_CAP_MAXWLEN_GET( _reg ) \
0100   ( ( ( _reg ) & SPICTRL_CAP_MAXWLEN_MASK ) >> \
0101     SPICTRL_CAP_MAXWLEN_SHIFT )
0102 #define SPICTRL_CAP_MAXWLEN_SET( _reg, _val ) \
0103   ( ( ( _reg ) & ~SPICTRL_CAP_MAXWLEN_MASK ) | \
0104     ( ( ( _val ) << SPICTRL_CAP_MAXWLEN_SHIFT ) & \
0105       SPICTRL_CAP_MAXWLEN_MASK ) )
0106 #define SPICTRL_CAP_MAXWLEN( _val ) \
0107   ( ( ( _val ) << SPICTRL_CAP_MAXWLEN_SHIFT ) & \
0108     SPICTRL_CAP_MAXWLEN_MASK )
0109
0110 #define SPICTRL_CAP_TWEN 0x80000U
0111
0112 #define SPICTRL_CAP_AMODE 0x40000U
0113
0114 #define SPICTRL_CAP_ASELA 0x20000U
0115
0116 #define SPICTRL_CAP_SSEN 0x10000U
0117
0118 #define SPICTRL_CAP_FDEPTH_SHIFT 8
0119 #define SPICTRL_CAP_FDEPTH_MASK 0xff00U
0120 #define SPICTRL_CAP_FDEPTH_GET( _reg ) \
0121   ( ( ( _reg ) & SPICTRL_CAP_FDEPTH_MASK ) >> \
0122     SPICTRL_CAP_FDEPTH_SHIFT )
0123 #define SPICTRL_CAP_FDEPTH_SET( _reg, _val ) \
0124   ( ( ( _reg ) & ~SPICTRL_CAP_FDEPTH_MASK ) | \
0125     ( ( ( _val ) << SPICTRL_CAP_FDEPTH_SHIFT ) & \
0126       SPICTRL_CAP_FDEPTH_MASK ) )
0127 #define SPICTRL_CAP_FDEPTH( _val ) \
0128   ( ( ( _val ) << SPICTRL_CAP_FDEPTH_SHIFT ) & \
0129     SPICTRL_CAP_FDEPTH_MASK )
0130
0131 #define SPICTRL_CAP_SR 0x80U
0132
0133 #define SPICTRL_CAP_FT_SHIFT 5
0134 #define SPICTRL_CAP_FT_MASK 0x60U
0135 #define SPICTRL_CAP_FT_GET( _reg ) \
0136   ( ( ( _reg ) & SPICTRL_CAP_FT_MASK ) >> \
0137     SPICTRL_CAP_FT_SHIFT )
0138 #define SPICTRL_CAP_FT_SET( _reg, _val ) \
0139   ( ( ( _reg ) & ~SPICTRL_CAP_FT_MASK ) | \
0140     ( ( ( _val ) << SPICTRL_CAP_FT_SHIFT ) & \
0141       SPICTRL_CAP_FT_MASK ) )
0142 #define SPICTRL_CAP_FT( _val ) \
0143   ( ( ( _val ) << SPICTRL_CAP_FT_SHIFT ) & \
0144     SPICTRL_CAP_FT_MASK )
0145
0146 #define SPICTRL_CAP_REV_SHIFT 0
0147 #define SPICTRL_CAP_REV_MASK 0x1fU
0148 #define SPICTRL_CAP_REV_GET( _reg ) \
0149   ( ( ( _reg ) & SPICTRL_CAP_REV_MASK ) >> \
0150     SPICTRL_CAP_REV_SHIFT )
0151 #define SPICTRL_CAP_REV_SET( _reg, _val ) \
0152   ( ( ( _reg ) & ~SPICTRL_CAP_REV_MASK ) | \
0153     ( ( ( _val ) << SPICTRL_CAP_REV_SHIFT ) & \
0154       SPICTRL_CAP_REV_MASK ) )
0155 #define SPICTRL_CAP_REV( _val ) \
0156   ( ( ( _val ) << SPICTRL_CAP_REV_SHIFT ) & \
0157     SPICTRL_CAP_REV_MASK )
0158
0159 /** @} */
0160
0161 /**
0162  * @defgroup RTEMSDeviceGRLIBSPICTRLMODE Mode register (MODE)
0163  *
0164  * @brief This group contains register bit definitions.
0165  *
0166  * @{
0167  */
0168
0169 #define SPICTRL_MODE_LOOP 0x40000000U
0170
0171 #define SPICTRL_MODE_CPOL 0x20000000U
0172
0173 #define SPICTRL_MODE_CPHA 0x10000000U
0174
0175 #define SPICTRL_MODE_DIV_16 0x8000000U
0176
0177 #define SPICTRL_MODE_REV 0x4000000U
0178
0179 #define SPICTRL_MODE_MX 0x2000000U
0180
0181 #define SPICTRL_MODE_EN 0x1000000U
0182
0183 #define SPICTRL_MODE_LEN_SHIFT 20
0184 #define SPICTRL_MODE_LEN_MASK 0xf00000U
0185 #define SPICTRL_MODE_LEN_GET( _reg ) \
0186   ( ( ( _reg ) & SPICTRL_MODE_LEN_MASK ) >> \
0187     SPICTRL_MODE_LEN_SHIFT )
0188 #define SPICTRL_MODE_LEN_SET( _reg, _val ) \
0189   ( ( ( _reg ) & ~SPICTRL_MODE_LEN_MASK ) | \
0190     ( ( ( _val ) << SPICTRL_MODE_LEN_SHIFT ) & \
0191       SPICTRL_MODE_LEN_MASK ) )
0192 #define SPICTRL_MODE_LEN( _val ) \
0193   ( ( ( _val ) << SPICTRL_MODE_LEN_SHIFT ) & \
0194     SPICTRL_MODE_LEN_MASK )
0195
0196 #define SPICTRL_MODE_PM_SHIFT 16
0197 #define SPICTRL_MODE_PM_MASK 0xf0000U
0198 #define SPICTRL_MODE_PM_GET( _reg ) \
0199   ( ( ( _reg ) & SPICTRL_MODE_PM_MASK ) >> \
0200     SPICTRL_MODE_PM_SHIFT )
0201 #define SPICTRL_MODE_PM_SET( _reg, _val ) \
0202   ( ( ( _reg ) & ~SPICTRL_MODE_PM_MASK ) | \
0203     ( ( ( _val ) << SPICTRL_MODE_PM_SHIFT ) & \
0204       SPICTRL_MODE_PM_MASK ) )
0205 #define SPICTRL_MODE_PM( _val ) \
0206   ( ( ( _val ) << SPICTRL_MODE_PM_SHIFT ) & \
0207     SPICTRL_MODE_PM_MASK )
0208
0209 #define SPICTRL_MODE_TWEN 0x8000U
0210
0211 #define SPICTRL_MODE_ASEL 0x4000U
0212
0213 #define SPICTRL_MODE_FACT 0x2000U
0214
0215 #define SPICTRL_MODE_OD 0x1000U
0216
0217 #define SPICTRL_MODE_CG_SHIFT 7
0218 #define SPICTRL_MODE_CG_MASK 0xf80U
0219 #define SPICTRL_MODE_CG_GET( _reg ) \
0220   ( ( ( _reg ) & SPICTRL_MODE_CG_MASK ) >> \
0221     SPICTRL_MODE_CG_SHIFT )
0222 #define SPICTRL_MODE_CG_SET( _reg, _val ) \
0223   ( ( ( _reg ) & ~SPICTRL_MODE_CG_MASK ) | \
0224     ( ( ( _val ) << SPICTRL_MODE_CG_SHIFT ) & \
0225       SPICTRL_MODE_CG_MASK ) )
0226 #define SPICTRL_MODE_CG( _val ) \
0227   ( ( ( _val ) << SPICTRL_MODE_CG_SHIFT ) & \
0228     SPICTRL_MODE_CG_MASK )
0229
0230 #define SPICTRL_MODE_ASELDEL_SHIFT 5
0231 #define SPICTRL_MODE_ASELDEL_MASK 0x60U
0232 #define SPICTRL_MODE_ASELDEL_GET( _reg ) \
0233   ( ( ( _reg ) & SPICTRL_MODE_ASELDEL_MASK ) >> \
0234     SPICTRL_MODE_ASELDEL_SHIFT )
0235 #define SPICTRL_MODE_ASELDEL_SET( _reg, _val ) \
0236   ( ( ( _reg ) & ~SPICTRL_MODE_ASELDEL_MASK ) | \
0237     ( ( ( _val ) << SPICTRL_MODE_ASELDEL_SHIFT ) & \
0238       SPICTRL_MODE_ASELDEL_MASK ) )
0239 #define SPICTRL_MODE_ASELDEL( _val ) \
0240   ( ( ( _val ) << SPICTRL_MODE_ASELDEL_SHIFT ) & \
0241     SPICTRL_MODE_ASELDEL_MASK )
0242
0243 #define SPICTRL_MODE_TAC 0x10U
0244
0245 #define SPICTRL_MODE_TTO 0x8U
0246
0247 #define SPICTRL_MODE_IGSEL 0x4U
0248
0249 #define SPICTRL_MODE_CITE 0x2U
0250
0251 /** @} */
0252
0253 /**
0254  * @defgroup RTEMSDeviceGRLIBSPICTRLEVENT Event register (EVENT)
0255  *
0256  * @brief This group contains register bit definitions.
0257  *
0258  * @{
0259  */
0260
0261 #define SPICTRL_EVENT_TIP 0x80000000U
0262
0263 #define SPICTRL_EVENT_LT 0x4000U
0264
0265 #define SPICTRL_EVENT_OV 0x1000U
0266
0267 #define SPICTRL_EVENT_UN 0x800U
0268
0269 #define SPICTRL_EVENT_MME 0x400U
0270
0271 #define SPICTRL_EVENT_NE 0x200U
0272
0273 #define SPICTRL_EVENT_NF 0x100U
0274
0275 /** @} */
0276
0277 /**
0278  * @defgroup RTEMSDeviceGRLIBSPICTRLMASK Mask register (MASK)
0279  *
0280  * @brief This group contains register bit definitions.
0281  *
0282  * @{
0283  */
0284
0285 #define SPICTRL_MASK_TIPE 0x80000000U
0286
0287 #define SPICTRL_MASK_LTE 0x4000U
0288
0289 #define SPICTRL_MASK_OVE 0x1000U
0290
0291 #define SPICTRL_MASK_UNE 0x800U
0292
0293 #define SPICTRL_MASK_MMEE 0x400U
0294
0295 #define SPICTRL_MASK_NEEE 0x200U
0296
0297 #define SPICTRL_MASK_NFE 0x100U
0298
0299 /** @} */
0300
0301 /**
0302  * @defgroup RTEMSDeviceGRLIBSPICTRLCMD Command register (CMD)
0303  *
0304  * @brief This group contains register bit definitions.
0305  *
0306  * @{
0307  */
0308
0309 #define SPICTRL_CMD_LST 0x400000U
0310
0311 /** @} */
0312
0313 /**
0314  * @defgroup RTEMSDeviceGRLIBSPICTRLTX Transmit register (TX)
0315  *
0316  * @brief This group contains register bit definitions.
0317  *
0318  * @{
0319  */
0320
0321 #define SPICTRL_TX_TDATA_SHIFT 0
0322 #define SPICTRL_TX_TDATA_MASK 0xffffffffU
0323 #define SPICTRL_TX_TDATA_GET( _reg ) \
0324   ( ( ( _reg ) & SPICTRL_TX_TDATA_MASK ) >> \
0325     SPICTRL_TX_TDATA_SHIFT )
0326 #define SPICTRL_TX_TDATA_SET( _reg, _val ) \
0327   ( ( ( _reg ) & ~SPICTRL_TX_TDATA_MASK ) | \
0328     ( ( ( _val ) << SPICTRL_TX_TDATA_SHIFT ) & \
0329       SPICTRL_TX_TDATA_MASK ) )
0330 #define SPICTRL_TX_TDATA( _val ) \
0331   ( ( ( _val ) << SPICTRL_TX_TDATA_SHIFT ) & \
0332     SPICTRL_TX_TDATA_MASK )
0333
0334 /** @} */
0335
0336 /**
0337  * @defgroup RTEMSDeviceGRLIBSPICTRLRX Receive register (RX)
0338  *
0339  * @brief This group contains register bit definitions.
0340  *
0341  * @{
0342  */
0343
0344 #define SPICTRL_RX_RDATA_SHIFT 0
0345 #define SPICTRL_RX_RDATA_MASK 0xffffffffU
0346 #define SPICTRL_RX_RDATA_GET( _reg ) \
0347   ( ( ( _reg ) & SPICTRL_RX_RDATA_MASK ) >> \
0348     SPICTRL_RX_RDATA_SHIFT )
0349 #define SPICTRL_RX_RDATA_SET( _reg, _val ) \
0350   ( ( ( _reg ) & ~SPICTRL_RX_RDATA_MASK ) | \
0351     ( ( ( _val ) << SPICTRL_RX_RDATA_SHIFT ) & \
0352       SPICTRL_RX_RDATA_MASK ) )
0353 #define SPICTRL_RX_RDATA( _val ) \
0354   ( ( ( _val ) << SPICTRL_RX_RDATA_SHIFT ) & \
0355     SPICTRL_RX_RDATA_MASK )
0356
0357 /** @} */
0358
0359 /**
0360  * @defgroup RTEMSDeviceGRLIBSPICTRLSLVSEL Slave select register (SLVSEL)
0361  *
0362  * @brief This group contains register bit definitions.
0363  *
0364  * @{
0365  */
0366
0367 #define SPICTRL_SLVSEL_SLVSEL_SHIFT 0
0368 #define SPICTRL_SLVSEL_SLVSEL_MASK 0x3U
0369 #define SPICTRL_SLVSEL_SLVSEL_GET( _reg ) \
0370   ( ( ( _reg ) & SPICTRL_SLVSEL_SLVSEL_MASK ) >> \
0371     SPICTRL_SLVSEL_SLVSEL_SHIFT )
0372 #define SPICTRL_SLVSEL_SLVSEL_SET( _reg, _val ) \
0373   ( ( ( _reg ) & ~SPICTRL_SLVSEL_SLVSEL_MASK ) | \
0374     ( ( ( _val ) << SPICTRL_SLVSEL_SLVSEL_SHIFT ) & \
0375       SPICTRL_SLVSEL_SLVSEL_MASK ) )
0376 #define SPICTRL_SLVSEL_SLVSEL( _val ) \
0377   ( ( ( _val ) << SPICTRL_SLVSEL_SLVSEL_SHIFT ) & \
0378     SPICTRL_SLVSEL_SLVSEL_MASK )
0379
0380 /** @} */
0381
0382 /**
0383  * @defgroup RTEMSDeviceGRLIBSPICTRLASLVSEL \
0384  *   Automatic slave select register (ASLVSEL)
0385  *
0386  * @brief This group contains register bit definitions.
0387  *
0388  * @{
0389  */
0390
0391 #define SPICTRL_ASLVSEL_ASLVSEL_SHIFT 0
0392 #define SPICTRL_ASLVSEL_ASLVSEL_MASK 0x3U
0393 #define SPICTRL_ASLVSEL_ASLVSEL_GET( _reg ) \
0394   ( ( ( _reg ) & SPICTRL_ASLVSEL_ASLVSEL_MASK ) >> \
0395     SPICTRL_ASLVSEL_ASLVSEL_SHIFT )
0396 #define SPICTRL_ASLVSEL_ASLVSEL_SET( _reg, _val ) \
0397   ( ( ( _reg ) & ~SPICTRL_ASLVSEL_ASLVSEL_MASK ) | \
0398     ( ( ( _val ) << SPICTRL_ASLVSEL_ASLVSEL_SHIFT ) & \
0399       SPICTRL_ASLVSEL_ASLVSEL_MASK ) )
0400 #define SPICTRL_ASLVSEL_ASLVSEL( _val ) \
0401   ( ( ( _val ) << SPICTRL_ASLVSEL_ASLVSEL_SHIFT ) & \
0402     SPICTRL_ASLVSEL_ASLVSEL_MASK )
0403
0404 /** @} */
0405
0406 /**
0407  * @brief This structure defines the SPICTRL register block memory map.
0408  */
0409 typedef struct spictrl {
0410   /**
0411    * @brief See @ref RTEMSDeviceGRLIBSPICTRLCAP.
0412    */
0413   uint32_t cap;
0414
0415   uint32_t reserved_4_20[ 7 ];
0416
0417   /**
0418    * @brief See @ref RTEMSDeviceGRLIBSPICTRLMODE.
0419    */
0420   uint32_t mode;
0421
0422   /**
0423    * @brief See @ref RTEMSDeviceGRLIBSPICTRLEVENT.
0424    */
0425   uint32_t event;
0426
0427   /**
0428    * @brief See @ref RTEMSDeviceGRLIBSPICTRLMASK.
0429    */
0430   uint32_t mask;
0431
0432   /**
0433    * @brief See @ref RTEMSDeviceGRLIBSPICTRLCMD.
0434    */
0435   uint32_t cmd;
0436
0437   /**
0438    * @brief See @ref RTEMSDeviceGRLIBSPICTRLTX.
0439    */
0440   uint32_t tx;
0441
0442   /**
0443    * @brief See @ref RTEMSDeviceGRLIBSPICTRLRX.
0444    */
0445   uint32_t rx;
0446
0447   /**
0448    * @brief See @ref RTEMSDeviceGRLIBSPICTRLSLVSEL.
0449    */
0450   uint32_t slvsel;
0451
0452   /**
0453    * @brief See @ref RTEMSDeviceGRLIBSPICTRLASLVSEL.
0454    */
0455   uint32_t aslvsel;
0456 } spictrl;
0457
0458 /** @} */
0459
0460 #ifdef __cplusplus
0461 }
0462 #endif
0463
0464 #endif /* _GRLIB_SPICTRL_REGS_H */