include/grlib/mmctrl-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRLIBMMCTRL
0007  *
0008  * @brief This header file defines the MMCTRL register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/mmctrl-header */
0054
0055 #ifndef _GRLIB_MMCTRL_REGS_H
0056 #define _GRLIB_MMCTRL_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/mmctrl */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRLIBMMCTRL MMCTRL
0068  *
0069  * @ingroup RTEMSDeviceGRLIB
0070  *
0071  * @brief This group contains the MMCTRL interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRLIBMMCTRLSDCFG1 \
0078  *   SDRAM configuration register 1 (SDCFG1)
0079  *
0080  * @brief This group contains register bit definitions.
0081  *
0082  * @{
0083  */
0084
0085 #define MMCTRL_SDCFG1_RF 0x80000000U
0086
0087 #define MMCTRL_SDCFG1_TRP 0x40000000U
0088
0089 #define MMCTRL_SDCFG1_TRFC_SHIFT 27
0090 #define MMCTRL_SDCFG1_TRFC_MASK 0x38000000U
0091 #define MMCTRL_SDCFG1_TRFC_GET( _reg ) \
0092   ( ( ( _reg ) & MMCTRL_SDCFG1_TRFC_MASK ) >> \
0093     MMCTRL_SDCFG1_TRFC_SHIFT )
0094 #define MMCTRL_SDCFG1_TRFC_SET( _reg, _val ) \
0095   ( ( ( _reg ) & ~MMCTRL_SDCFG1_TRFC_MASK ) | \
0096     ( ( ( _val ) << MMCTRL_SDCFG1_TRFC_SHIFT ) & \
0097       MMCTRL_SDCFG1_TRFC_MASK ) )
0098 #define MMCTRL_SDCFG1_TRFC( _val ) \
0099   ( ( ( _val ) << MMCTRL_SDCFG1_TRFC_SHIFT ) & \
0100     MMCTRL_SDCFG1_TRFC_MASK )
0101
0102 #define MMCTRL_SDCFG1_TC 0x4000000U
0103
0104 #define MMCTRL_SDCFG1_BANKSZ_SHIFT 23
0105 #define MMCTRL_SDCFG1_BANKSZ_MASK 0x3800000U
0106 #define MMCTRL_SDCFG1_BANKSZ_GET( _reg ) \
0107   ( ( ( _reg ) & MMCTRL_SDCFG1_BANKSZ_MASK ) >> \
0108     MMCTRL_SDCFG1_BANKSZ_SHIFT )
0109 #define MMCTRL_SDCFG1_BANKSZ_SET( _reg, _val ) \
0110   ( ( ( _reg ) & ~MMCTRL_SDCFG1_BANKSZ_MASK ) | \
0111     ( ( ( _val ) << MMCTRL_SDCFG1_BANKSZ_SHIFT ) & \
0112       MMCTRL_SDCFG1_BANKSZ_MASK ) )
0113 #define MMCTRL_SDCFG1_BANKSZ( _val ) \
0114   ( ( ( _val ) << MMCTRL_SDCFG1_BANKSZ_SHIFT ) & \
0115     MMCTRL_SDCFG1_BANKSZ_MASK )
0116
0117 #define MMCTRL_SDCFG1_COLSZ_SHIFT 21
0118 #define MMCTRL_SDCFG1_COLSZ_MASK 0x600000U
0119 #define MMCTRL_SDCFG1_COLSZ_GET( _reg ) \
0120   ( ( ( _reg ) & MMCTRL_SDCFG1_COLSZ_MASK ) >> \
0121     MMCTRL_SDCFG1_COLSZ_SHIFT )
0122 #define MMCTRL_SDCFG1_COLSZ_SET( _reg, _val ) \
0123   ( ( ( _reg ) & ~MMCTRL_SDCFG1_COLSZ_MASK ) | \
0124     ( ( ( _val ) << MMCTRL_SDCFG1_COLSZ_SHIFT ) & \
0125       MMCTRL_SDCFG1_COLSZ_MASK ) )
0126 #define MMCTRL_SDCFG1_COLSZ( _val ) \
0127   ( ( ( _val ) << MMCTRL_SDCFG1_COLSZ_SHIFT ) & \
0128     MMCTRL_SDCFG1_COLSZ_MASK )
0129
0130 #define MMCTRL_SDCFG1_COMMAND_SHIFT 18
0131 #define MMCTRL_SDCFG1_COMMAND_MASK 0x1c0000U
0132 #define MMCTRL_SDCFG1_COMMAND_GET( _reg ) \
0133   ( ( ( _reg ) & MMCTRL_SDCFG1_COMMAND_MASK ) >> \
0134     MMCTRL_SDCFG1_COMMAND_SHIFT )
0135 #define MMCTRL_SDCFG1_COMMAND_SET( _reg, _val ) \
0136   ( ( ( _reg ) & ~MMCTRL_SDCFG1_COMMAND_MASK ) | \
0137     ( ( ( _val ) << MMCTRL_SDCFG1_COMMAND_SHIFT ) & \
0138       MMCTRL_SDCFG1_COMMAND_MASK ) )
0139 #define MMCTRL_SDCFG1_COMMAND( _val ) \
0140   ( ( ( _val ) << MMCTRL_SDCFG1_COMMAND_SHIFT ) & \
0141     MMCTRL_SDCFG1_COMMAND_MASK )
0142
0143 #define MMCTRL_SDCFG1_MS 0x10000U
0144
0145 #define MMCTRL_SDCFG1_64 0x8000U
0146
0147 #define MMCTRL_SDCFG1_RFLOAD_SHIFT 0
0148 #define MMCTRL_SDCFG1_RFLOAD_MASK 0x7fffU
0149 #define MMCTRL_SDCFG1_RFLOAD_GET( _reg ) \
0150   ( ( ( _reg ) & MMCTRL_SDCFG1_RFLOAD_MASK ) >> \
0151     MMCTRL_SDCFG1_RFLOAD_SHIFT )
0152 #define MMCTRL_SDCFG1_RFLOAD_SET( _reg, _val ) \
0153   ( ( ( _reg ) & ~MMCTRL_SDCFG1_RFLOAD_MASK ) | \
0154     ( ( ( _val ) << MMCTRL_SDCFG1_RFLOAD_SHIFT ) & \
0155       MMCTRL_SDCFG1_RFLOAD_MASK ) )
0156 #define MMCTRL_SDCFG1_RFLOAD( _val ) \
0157   ( ( ( _val ) << MMCTRL_SDCFG1_RFLOAD_SHIFT ) & \
0158     MMCTRL_SDCFG1_RFLOAD_MASK )
0159
0160 /** @} */
0161
0162 /**
0163  * @defgroup RTEMSDeviceGRLIBMMCTRLSDCFG2 \
0164  *   SDRAM configuration register 2 (SDCFG2)
0165  *
0166  * @brief This group contains register bit definitions.
0167  *
0168  * @{
0169  */
0170
0171 #define MMCTRL_SDCFG2_CE 0x40000000U
0172
0173 #define MMCTRL_SDCFG2_EN2T 0x8000U
0174
0175 #define MMCTRL_SDCFG2_DCS 0x4000U
0176
0177 #define MMCTRL_SDCFG2_BPARK 0x2000U
0178
0179 /** @} */
0180
0181 /**
0182  * @defgroup RTEMSDeviceGRLIBMMCTRLMUXCFG Mux configuration register (MUXCFG)
0183  *
0184  * @brief This group contains register bit definitions.
0185  *
0186  * @{
0187  */
0188
0189 #define MMCTRL_MUXCFG_ERRLOC_SHIFT 20
0190 #define MMCTRL_MUXCFG_ERRLOC_MASK 0xfff00000U
0191 #define MMCTRL_MUXCFG_ERRLOC_GET( _reg ) \
0192   ( ( ( _reg ) & MMCTRL_MUXCFG_ERRLOC_MASK ) >> \
0193     MMCTRL_MUXCFG_ERRLOC_SHIFT )
0194 #define MMCTRL_MUXCFG_ERRLOC_SET( _reg, _val ) \
0195   ( ( ( _reg ) & ~MMCTRL_MUXCFG_ERRLOC_MASK ) | \
0196     ( ( ( _val ) << MMCTRL_MUXCFG_ERRLOC_SHIFT ) & \
0197       MMCTRL_MUXCFG_ERRLOC_MASK ) )
0198 #define MMCTRL_MUXCFG_ERRLOC( _val ) \
0199   ( ( ( _val ) << MMCTRL_MUXCFG_ERRLOC_SHIFT ) & \
0200     MMCTRL_MUXCFG_ERRLOC_MASK )
0201
0202 #define MMCTRL_MUXCFG_DDERR 0x80000U
0203
0204 #define MMCTRL_MUXCFG_DWIDTH_SHIFT 16
0205 #define MMCTRL_MUXCFG_DWIDTH_MASK 0x70000U
0206 #define MMCTRL_MUXCFG_DWIDTH_GET( _reg ) \
0207   ( ( ( _reg ) & MMCTRL_MUXCFG_DWIDTH_MASK ) >> \
0208     MMCTRL_MUXCFG_DWIDTH_SHIFT )
0209 #define MMCTRL_MUXCFG_DWIDTH_SET( _reg, _val ) \
0210   ( ( ( _reg ) & ~MMCTRL_MUXCFG_DWIDTH_MASK ) | \
0211     ( ( ( _val ) << MMCTRL_MUXCFG_DWIDTH_SHIFT ) & \
0212       MMCTRL_MUXCFG_DWIDTH_MASK ) )
0213 #define MMCTRL_MUXCFG_DWIDTH( _val ) \
0214   ( ( ( _val ) << MMCTRL_MUXCFG_DWIDTH_SHIFT ) & \
0215     MMCTRL_MUXCFG_DWIDTH_MASK )
0216
0217 #define MMCTRL_MUXCFG_BEID_SHIFT 12
0218 #define MMCTRL_MUXCFG_BEID_MASK 0xf000U
0219 #define MMCTRL_MUXCFG_BEID_GET( _reg ) \
0220   ( ( ( _reg ) & MMCTRL_MUXCFG_BEID_MASK ) >> \
0221     MMCTRL_MUXCFG_BEID_SHIFT )
0222 #define MMCTRL_MUXCFG_BEID_SET( _reg, _val ) \
0223   ( ( ( _reg ) & ~MMCTRL_MUXCFG_BEID_MASK ) | \
0224     ( ( ( _val ) << MMCTRL_MUXCFG_BEID_SHIFT ) & \
0225       MMCTRL_MUXCFG_BEID_MASK ) )
0226 #define MMCTRL_MUXCFG_BEID( _val ) \
0227   ( ( ( _val ) << MMCTRL_MUXCFG_BEID_SHIFT ) & \
0228     MMCTRL_MUXCFG_BEID_MASK )
0229
0230 #define MMCTRL_MUXCFG_DATAMUX_SHIFT 5
0231 #define MMCTRL_MUXCFG_DATAMUX_MASK 0xe0U
0232 #define MMCTRL_MUXCFG_DATAMUX_GET( _reg ) \
0233   ( ( ( _reg ) & MMCTRL_MUXCFG_DATAMUX_MASK ) >> \
0234     MMCTRL_MUXCFG_DATAMUX_SHIFT )
0235 #define MMCTRL_MUXCFG_DATAMUX_SET( _reg, _val ) \
0236   ( ( ( _reg ) & ~MMCTRL_MUXCFG_DATAMUX_MASK ) | \
0237     ( ( ( _val ) << MMCTRL_MUXCFG_DATAMUX_SHIFT ) & \
0238       MMCTRL_MUXCFG_DATAMUX_MASK ) )
0239 #define MMCTRL_MUXCFG_DATAMUX( _val ) \
0240   ( ( ( _val ) << MMCTRL_MUXCFG_DATAMUX_SHIFT ) & \
0241     MMCTRL_MUXCFG_DATAMUX_MASK )
0242
0243 #define MMCTRL_MUXCFG_CEN 0x10U
0244
0245 #define MMCTRL_MUXCFG_BAUPD 0x8U
0246
0247 #define MMCTRL_MUXCFG_BAEN 0x4U
0248
0249 #define MMCTRL_MUXCFG_CODE 0x2U
0250
0251 #define MMCTRL_MUXCFG_EDEN 0x1U
0252
0253 /** @} */
0254
0255 /**
0256  * @defgroup RTEMSDeviceGRLIBMMCTRLFTDA FT diagnostic address register (FTDA)
0257  *
0258  * @brief This group contains register bit definitions.
0259  *
0260  * @{
0261  */
0262
0263 #define MMCTRL_FTDA_FTDA_SHIFT 2
0264 #define MMCTRL_FTDA_FTDA_MASK 0xfffffffcU
0265 #define MMCTRL_FTDA_FTDA_GET( _reg ) \
0266   ( ( ( _reg ) & MMCTRL_FTDA_FTDA_MASK ) >> \
0267     MMCTRL_FTDA_FTDA_SHIFT )
0268 #define MMCTRL_FTDA_FTDA_SET( _reg, _val ) \
0269   ( ( ( _reg ) & ~MMCTRL_FTDA_FTDA_MASK ) | \
0270     ( ( ( _val ) << MMCTRL_FTDA_FTDA_SHIFT ) & \
0271       MMCTRL_FTDA_FTDA_MASK ) )
0272 #define MMCTRL_FTDA_FTDA( _val ) \
0273   ( ( ( _val ) << MMCTRL_FTDA_FTDA_SHIFT ) & \
0274     MMCTRL_FTDA_FTDA_MASK )
0275
0276 /** @} */
0277
0278 /**
0279  * @defgroup RTEMSDeviceGRLIBMMCTRLFTDC FT diagnostic checkbits register (FTDC)
0280  *
0281  * @brief This group contains register bit definitions.
0282  *
0283  * @{
0284  */
0285
0286 #define MMCTRL_FTDC_CBD_SHIFT 24
0287 #define MMCTRL_FTDC_CBD_MASK 0xff000000U
0288 #define MMCTRL_FTDC_CBD_GET( _reg ) \
0289   ( ( ( _reg ) & MMCTRL_FTDC_CBD_MASK ) >> \
0290     MMCTRL_FTDC_CBD_SHIFT )
0291 #define MMCTRL_FTDC_CBD_SET( _reg, _val ) \
0292   ( ( ( _reg ) & ~MMCTRL_FTDC_CBD_MASK ) | \
0293     ( ( ( _val ) << MMCTRL_FTDC_CBD_SHIFT ) & \
0294       MMCTRL_FTDC_CBD_MASK ) )
0295 #define MMCTRL_FTDC_CBD( _val ) \
0296   ( ( ( _val ) << MMCTRL_FTDC_CBD_SHIFT ) & \
0297     MMCTRL_FTDC_CBD_MASK )
0298
0299 #define MMCTRL_FTDC_CBC_SHIFT 16
0300 #define MMCTRL_FTDC_CBC_MASK 0xff0000U
0301 #define MMCTRL_FTDC_CBC_GET( _reg ) \
0302   ( ( ( _reg ) & MMCTRL_FTDC_CBC_MASK ) >> \
0303     MMCTRL_FTDC_CBC_SHIFT )
0304 #define MMCTRL_FTDC_CBC_SET( _reg, _val ) \
0305   ( ( ( _reg ) & ~MMCTRL_FTDC_CBC_MASK ) | \
0306     ( ( ( _val ) << MMCTRL_FTDC_CBC_SHIFT ) & \
0307       MMCTRL_FTDC_CBC_MASK ) )
0308 #define MMCTRL_FTDC_CBC( _val ) \
0309   ( ( ( _val ) << MMCTRL_FTDC_CBC_SHIFT ) & \
0310     MMCTRL_FTDC_CBC_MASK )
0311
0312 #define MMCTRL_FTDC_CBB_SHIFT 8
0313 #define MMCTRL_FTDC_CBB_MASK 0xff00U
0314 #define MMCTRL_FTDC_CBB_GET( _reg ) \
0315   ( ( ( _reg ) & MMCTRL_FTDC_CBB_MASK ) >> \
0316     MMCTRL_FTDC_CBB_SHIFT )
0317 #define MMCTRL_FTDC_CBB_SET( _reg, _val ) \
0318   ( ( ( _reg ) & ~MMCTRL_FTDC_CBB_MASK ) | \
0319     ( ( ( _val ) << MMCTRL_FTDC_CBB_SHIFT ) & \
0320       MMCTRL_FTDC_CBB_MASK ) )
0321 #define MMCTRL_FTDC_CBB( _val ) \
0322   ( ( ( _val ) << MMCTRL_FTDC_CBB_SHIFT ) & \
0323     MMCTRL_FTDC_CBB_MASK )
0324
0325 #define MMCTRL_FTDC_CBA_SHIFT 0
0326 #define MMCTRL_FTDC_CBA_MASK 0xffU
0327 #define MMCTRL_FTDC_CBA_GET( _reg ) \
0328   ( ( ( _reg ) & MMCTRL_FTDC_CBA_MASK ) >> \
0329     MMCTRL_FTDC_CBA_SHIFT )
0330 #define MMCTRL_FTDC_CBA_SET( _reg, _val ) \
0331   ( ( ( _reg ) & ~MMCTRL_FTDC_CBA_MASK ) | \
0332     ( ( ( _val ) << MMCTRL_FTDC_CBA_SHIFT ) & \
0333       MMCTRL_FTDC_CBA_MASK ) )
0334 #define MMCTRL_FTDC_CBA( _val ) \
0335   ( ( ( _val ) << MMCTRL_FTDC_CBA_SHIFT ) & \
0336     MMCTRL_FTDC_CBA_MASK )
0337
0338 /** @} */
0339
0340 /**
0341  * @defgroup RTEMSDeviceGRLIBMMCTRLFTDD FT diagnostic data register (FTDD)
0342  *
0343  * @brief This group contains register bit definitions.
0344  *
0345  * @{
0346  */
0347
0348 #define MMCTRL_FTDD_DATA_SHIFT 0
0349 #define MMCTRL_FTDD_DATA_MASK 0xffffffffU
0350 #define MMCTRL_FTDD_DATA_GET( _reg ) \
0351   ( ( ( _reg ) & MMCTRL_FTDD_DATA_MASK ) >> \
0352     MMCTRL_FTDD_DATA_SHIFT )
0353 #define MMCTRL_FTDD_DATA_SET( _reg, _val ) \
0354   ( ( ( _reg ) & ~MMCTRL_FTDD_DATA_MASK ) | \
0355     ( ( ( _val ) << MMCTRL_FTDD_DATA_SHIFT ) & \
0356       MMCTRL_FTDD_DATA_MASK ) )
0357 #define MMCTRL_FTDD_DATA( _val ) \
0358   ( ( ( _val ) << MMCTRL_FTDD_DATA_SHIFT ) & \
0359     MMCTRL_FTDD_DATA_MASK )
0360
0361 /** @} */
0362
0363 /**
0364  * @defgroup RTEMSDeviceGRLIBMMCTRLFTBND FT boundary address register (FTBND)
0365  *
0366  * @brief This group contains register bit definitions.
0367  *
0368  * @{
0369  */
0370
0371 #define MMCTRL_FTBND_FTBND_31_3_SHIFT 3
0372 #define MMCTRL_FTBND_FTBND_31_3_MASK 0xfffffff8U
0373 #define MMCTRL_FTBND_FTBND_31_3_GET( _reg ) \
0374   ( ( ( _reg ) & MMCTRL_FTBND_FTBND_31_3_MASK ) >> \
0375     MMCTRL_FTBND_FTBND_31_3_SHIFT )
0376 #define MMCTRL_FTBND_FTBND_31_3_SET( _reg, _val ) \
0377   ( ( ( _reg ) & ~MMCTRL_FTBND_FTBND_31_3_MASK ) | \
0378     ( ( ( _val ) << MMCTRL_FTBND_FTBND_31_3_SHIFT ) & \
0379       MMCTRL_FTBND_FTBND_31_3_MASK ) )
0380 #define MMCTRL_FTBND_FTBND_31_3( _val ) \
0381   ( ( ( _val ) << MMCTRL_FTBND_FTBND_31_3_SHIFT ) & \
0382     MMCTRL_FTBND_FTBND_31_3_MASK )
0383
0384 /** @} */
0385
0386 /**
0387  * @brief This structure defines the MMCTRL register block memory map.
0388  */
0389 typedef struct mmctrl {
0390   /**
0391    * @brief See @ref RTEMSDeviceGRLIBMMCTRLSDCFG1.
0392    */
0393   uint32_t sdcfg1;
0394
0395   /**
0396    * @brief See @ref RTEMSDeviceGRLIBMMCTRLSDCFG2.
0397    */
0398   uint32_t sdcfg2;
0399
0400   uint32_t reserved_8_20[ 6 ];
0401
0402   /**
0403    * @brief See @ref RTEMSDeviceGRLIBMMCTRLMUXCFG.
0404    */
0405   uint32_t muxcfg;
0406
0407   /**
0408    * @brief See @ref RTEMSDeviceGRLIBMMCTRLFTDA.
0409    */
0410   uint32_t ftda;
0411
0412   /**
0413    * @brief See @ref RTEMSDeviceGRLIBMMCTRLFTDC.
0414    */
0415   uint32_t ftdc;
0416
0417   /**
0418    * @brief See @ref RTEMSDeviceGRLIBMMCTRLFTDD.
0419    */
0420   uint32_t ftdd;
0421
0422   /**
0423    * @brief See @ref RTEMSDeviceGRLIBMMCTRLFTBND.
0424    */
0425   uint32_t ftbnd;
0426 } mmctrl;
0427
0428 /** @} */
0429
0430 #ifdef __cplusplus
0431 }
0432 #endif
0433
0434 #endif /* _GRLIB_MMCTRL_REGS_H */