include/grlib/memscrub-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRLIBMEMSCRUB
0007  *
0008  * @brief This header file defines the MEMSCRUB register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/memscrub-header */
0054
0055 #ifndef _GRLIB_MEMSCRUB_REGS_H
0056 #define _GRLIB_MEMSCRUB_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/memscrub */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRLIBMEMSCRUB MEMSCRUB
0068  *
0069  * @ingroup RTEMSDeviceGRLIB
0070  *
0071  * @brief This group contains the MEMSCRUB interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRLIBMEMSCRUBAHBS AHB Status register (AHBS)
0078  *
0079  * @brief This group contains register bit definitions.
0080  *
0081  * @{
0082  */
0083
0084 #define MEMSCRUB_AHBS_CECNT_SHIFT 22
0085 #define MEMSCRUB_AHBS_CECNT_MASK 0xffc00000U
0086 #define MEMSCRUB_AHBS_CECNT_GET( _reg ) \
0087   ( ( ( _reg ) & MEMSCRUB_AHBS_CECNT_MASK ) >> \
0088     MEMSCRUB_AHBS_CECNT_SHIFT )
0089 #define MEMSCRUB_AHBS_CECNT_SET( _reg, _val ) \
0090   ( ( ( _reg ) & ~MEMSCRUB_AHBS_CECNT_MASK ) | \
0091     ( ( ( _val ) << MEMSCRUB_AHBS_CECNT_SHIFT ) & \
0092       MEMSCRUB_AHBS_CECNT_MASK ) )
0093 #define MEMSCRUB_AHBS_CECNT( _val ) \
0094   ( ( ( _val ) << MEMSCRUB_AHBS_CECNT_SHIFT ) & \
0095     MEMSCRUB_AHBS_CECNT_MASK )
0096
0097 #define MEMSCRUB_AHBS_UECNT_SHIFT 14
0098 #define MEMSCRUB_AHBS_UECNT_MASK 0x3fc000U
0099 #define MEMSCRUB_AHBS_UECNT_GET( _reg ) \
0100   ( ( ( _reg ) & MEMSCRUB_AHBS_UECNT_MASK ) >> \
0101     MEMSCRUB_AHBS_UECNT_SHIFT )
0102 #define MEMSCRUB_AHBS_UECNT_SET( _reg, _val ) \
0103   ( ( ( _reg ) & ~MEMSCRUB_AHBS_UECNT_MASK ) | \
0104     ( ( ( _val ) << MEMSCRUB_AHBS_UECNT_SHIFT ) & \
0105       MEMSCRUB_AHBS_UECNT_MASK ) )
0106 #define MEMSCRUB_AHBS_UECNT( _val ) \
0107   ( ( ( _val ) << MEMSCRUB_AHBS_UECNT_SHIFT ) & \
0108     MEMSCRUB_AHBS_UECNT_MASK )
0109
0110 #define MEMSCRUB_AHBS_DONE 0x2000U
0111
0112 #define MEMSCRUB_AHBS_SEC 0x800U
0113
0114 #define MEMSCRUB_AHBS_SBC 0x400U
0115
0116 #define MEMSCRUB_AHBS_CE 0x200U
0117
0118 #define MEMSCRUB_AHBS_NE 0x100U
0119
0120 #define MEMSCRUB_AHBS_HWRITE 0x80U
0121
0122 #define MEMSCRUB_AHBS_HMASTER_SHIFT 3
0123 #define MEMSCRUB_AHBS_HMASTER_MASK 0x78U
0124 #define MEMSCRUB_AHBS_HMASTER_GET( _reg ) \
0125   ( ( ( _reg ) & MEMSCRUB_AHBS_HMASTER_MASK ) >> \
0126     MEMSCRUB_AHBS_HMASTER_SHIFT )
0127 #define MEMSCRUB_AHBS_HMASTER_SET( _reg, _val ) \
0128   ( ( ( _reg ) & ~MEMSCRUB_AHBS_HMASTER_MASK ) | \
0129     ( ( ( _val ) << MEMSCRUB_AHBS_HMASTER_SHIFT ) & \
0130       MEMSCRUB_AHBS_HMASTER_MASK ) )
0131 #define MEMSCRUB_AHBS_HMASTER( _val ) \
0132   ( ( ( _val ) << MEMSCRUB_AHBS_HMASTER_SHIFT ) & \
0133     MEMSCRUB_AHBS_HMASTER_MASK )
0134
0135 #define MEMSCRUB_AHBS_HSIZE_SHIFT 0
0136 #define MEMSCRUB_AHBS_HSIZE_MASK 0x7U
0137 #define MEMSCRUB_AHBS_HSIZE_GET( _reg ) \
0138   ( ( ( _reg ) & MEMSCRUB_AHBS_HSIZE_MASK ) >> \
0139     MEMSCRUB_AHBS_HSIZE_SHIFT )
0140 #define MEMSCRUB_AHBS_HSIZE_SET( _reg, _val ) \
0141   ( ( ( _reg ) & ~MEMSCRUB_AHBS_HSIZE_MASK ) | \
0142     ( ( ( _val ) << MEMSCRUB_AHBS_HSIZE_SHIFT ) & \
0143       MEMSCRUB_AHBS_HSIZE_MASK ) )
0144 #define MEMSCRUB_AHBS_HSIZE( _val ) \
0145   ( ( ( _val ) << MEMSCRUB_AHBS_HSIZE_SHIFT ) & \
0146     MEMSCRUB_AHBS_HSIZE_MASK )
0147
0148 /** @} */
0149
0150 /**
0151  * @defgroup RTEMSDeviceGRLIBMEMSCRUBAHBFAR \
0152  *   AHB Failing Address Register (AHBFAR)
0153  *
0154  * @brief This group contains register bit definitions.
0155  *
0156  * @{
0157  */
0158
0159 #define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT 0
0160 #define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK 0xffffffffU
0161 #define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_GET( _reg ) \
0162   ( ( ( _reg ) & MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK ) >> \
0163     MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT )
0164 #define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SET( _reg, _val ) \
0165   ( ( ( _reg ) & ~MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK ) | \
0166     ( ( ( _val ) << MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT ) & \
0167       MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK ) )
0168 #define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS( _val ) \
0169   ( ( ( _val ) << MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT ) & \
0170     MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK )
0171
0172 /** @} */
0173
0174 /**
0175  * @defgroup RTEMSDeviceGRLIBMEMSCRUBAHBERC \
0176  *   AHB Error configuration register (AHBERC)
0177  *
0178  * @brief This group contains register bit definitions.
0179  *
0180  * @{
0181  */
0182
0183 #define MEMSCRUB_AHBERC_CECNTT_SHIFT 22
0184 #define MEMSCRUB_AHBERC_CECNTT_MASK 0xffc00000U
0185 #define MEMSCRUB_AHBERC_CECNTT_GET( _reg ) \
0186   ( ( ( _reg ) & MEMSCRUB_AHBERC_CECNTT_MASK ) >> \
0187     MEMSCRUB_AHBERC_CECNTT_SHIFT )
0188 #define MEMSCRUB_AHBERC_CECNTT_SET( _reg, _val ) \
0189   ( ( ( _reg ) & ~MEMSCRUB_AHBERC_CECNTT_MASK ) | \
0190     ( ( ( _val ) << MEMSCRUB_AHBERC_CECNTT_SHIFT ) & \
0191       MEMSCRUB_AHBERC_CECNTT_MASK ) )
0192 #define MEMSCRUB_AHBERC_CECNTT( _val ) \
0193   ( ( ( _val ) << MEMSCRUB_AHBERC_CECNTT_SHIFT ) & \
0194     MEMSCRUB_AHBERC_CECNTT_MASK )
0195
0196 #define MEMSCRUB_AHBERC_UECNTT_SHIFT 14
0197 #define MEMSCRUB_AHBERC_UECNTT_MASK 0x3fc000U
0198 #define MEMSCRUB_AHBERC_UECNTT_GET( _reg ) \
0199   ( ( ( _reg ) & MEMSCRUB_AHBERC_UECNTT_MASK ) >> \
0200     MEMSCRUB_AHBERC_UECNTT_SHIFT )
0201 #define MEMSCRUB_AHBERC_UECNTT_SET( _reg, _val ) \
0202   ( ( ( _reg ) & ~MEMSCRUB_AHBERC_UECNTT_MASK ) | \
0203     ( ( ( _val ) << MEMSCRUB_AHBERC_UECNTT_SHIFT ) & \
0204       MEMSCRUB_AHBERC_UECNTT_MASK ) )
0205 #define MEMSCRUB_AHBERC_UECNTT( _val ) \
0206   ( ( ( _val ) << MEMSCRUB_AHBERC_UECNTT_SHIFT ) & \
0207     MEMSCRUB_AHBERC_UECNTT_MASK )
0208
0209 #define MEMSCRUB_AHBERC_CECTE 0x2U
0210
0211 #define MEMSCRUB_AHBERC_UECTE 0x1U
0212
0213 /** @} */
0214
0215 /**
0216  * @defgroup RTEMSDeviceGRLIBMEMSCRUBSTAT Status register (STAT)
0217  *
0218  * @brief This group contains register bit definitions.
0219  *
0220  * @{
0221  */
0222
0223 #define MEMSCRUB_STAT_RUNCOUNT_SHIFT 22
0224 #define MEMSCRUB_STAT_RUNCOUNT_MASK 0xffc00000U
0225 #define MEMSCRUB_STAT_RUNCOUNT_GET( _reg ) \
0226   ( ( ( _reg ) & MEMSCRUB_STAT_RUNCOUNT_MASK ) >> \
0227     MEMSCRUB_STAT_RUNCOUNT_SHIFT )
0228 #define MEMSCRUB_STAT_RUNCOUNT_SET( _reg, _val ) \
0229   ( ( ( _reg ) & ~MEMSCRUB_STAT_RUNCOUNT_MASK ) | \
0230     ( ( ( _val ) << MEMSCRUB_STAT_RUNCOUNT_SHIFT ) & \
0231       MEMSCRUB_STAT_RUNCOUNT_MASK ) )
0232 #define MEMSCRUB_STAT_RUNCOUNT( _val ) \
0233   ( ( ( _val ) << MEMSCRUB_STAT_RUNCOUNT_SHIFT ) & \
0234     MEMSCRUB_STAT_RUNCOUNT_MASK )
0235
0236 #define MEMSCRUB_STAT_BLKCOUNT_SHIFT 14
0237 #define MEMSCRUB_STAT_BLKCOUNT_MASK 0x3fc000U
0238 #define MEMSCRUB_STAT_BLKCOUNT_GET( _reg ) \
0239   ( ( ( _reg ) & MEMSCRUB_STAT_BLKCOUNT_MASK ) >> \
0240     MEMSCRUB_STAT_BLKCOUNT_SHIFT )
0241 #define MEMSCRUB_STAT_BLKCOUNT_SET( _reg, _val ) \
0242   ( ( ( _reg ) & ~MEMSCRUB_STAT_BLKCOUNT_MASK ) | \
0243     ( ( ( _val ) << MEMSCRUB_STAT_BLKCOUNT_SHIFT ) & \
0244       MEMSCRUB_STAT_BLKCOUNT_MASK ) )
0245 #define MEMSCRUB_STAT_BLKCOUNT( _val ) \
0246   ( ( ( _val ) << MEMSCRUB_STAT_BLKCOUNT_SHIFT ) & \
0247     MEMSCRUB_STAT_BLKCOUNT_MASK )
0248
0249 #define MEMSCRUB_STAT_DONE 0x2000U
0250
0251 #define MEMSCRUB_STAT_BURSTLEN_SHIFT 1
0252 #define MEMSCRUB_STAT_BURSTLEN_MASK 0x1eU
0253 #define MEMSCRUB_STAT_BURSTLEN_GET( _reg ) \
0254   ( ( ( _reg ) & MEMSCRUB_STAT_BURSTLEN_MASK ) >> \
0255     MEMSCRUB_STAT_BURSTLEN_SHIFT )
0256 #define MEMSCRUB_STAT_BURSTLEN_SET( _reg, _val ) \
0257   ( ( ( _reg ) & ~MEMSCRUB_STAT_BURSTLEN_MASK ) | \
0258     ( ( ( _val ) << MEMSCRUB_STAT_BURSTLEN_SHIFT ) & \
0259       MEMSCRUB_STAT_BURSTLEN_MASK ) )
0260 #define MEMSCRUB_STAT_BURSTLEN( _val ) \
0261   ( ( ( _val ) << MEMSCRUB_STAT_BURSTLEN_SHIFT ) & \
0262     MEMSCRUB_STAT_BURSTLEN_MASK )
0263
0264 #define MEMSCRUB_STAT_ACTIVE 0x1U
0265
0266 /** @} */
0267
0268 /**
0269  * @defgroup RTEMSDeviceGRLIBMEMSCRUBCONFIG Configuration register (CONFIG)
0270  *
0271  * @brief This group contains register bit definitions.
0272  *
0273  * @{
0274  */
0275
0276 #define MEMSCRUB_CONFIG_DELAY_SHIFT 8
0277 #define MEMSCRUB_CONFIG_DELAY_MASK 0xff00U
0278 #define MEMSCRUB_CONFIG_DELAY_GET( _reg ) \
0279   ( ( ( _reg ) & MEMSCRUB_CONFIG_DELAY_MASK ) >> \
0280     MEMSCRUB_CONFIG_DELAY_SHIFT )
0281 #define MEMSCRUB_CONFIG_DELAY_SET( _reg, _val ) \
0282   ( ( ( _reg ) & ~MEMSCRUB_CONFIG_DELAY_MASK ) | \
0283     ( ( ( _val ) << MEMSCRUB_CONFIG_DELAY_SHIFT ) & \
0284       MEMSCRUB_CONFIG_DELAY_MASK ) )
0285 #define MEMSCRUB_CONFIG_DELAY( _val ) \
0286   ( ( ( _val ) << MEMSCRUB_CONFIG_DELAY_SHIFT ) & \
0287     MEMSCRUB_CONFIG_DELAY_MASK )
0288
0289 #define MEMSCRUB_CONFIG_IRQD 0x80U
0290
0291 #define MEMSCRUB_CONFIG_SERA 0x20U
0292
0293 #define MEMSCRUB_CONFIG_LOOP 0x10U
0294
0295 #define MEMSCRUB_CONFIG_MODE_SHIFT 2
0296 #define MEMSCRUB_CONFIG_MODE_MASK 0xcU
0297 #define MEMSCRUB_CONFIG_MODE_GET( _reg ) \
0298   ( ( ( _reg ) & MEMSCRUB_CONFIG_MODE_MASK ) >> \
0299     MEMSCRUB_CONFIG_MODE_SHIFT )
0300 #define MEMSCRUB_CONFIG_MODE_SET( _reg, _val ) \
0301   ( ( ( _reg ) & ~MEMSCRUB_CONFIG_MODE_MASK ) | \
0302     ( ( ( _val ) << MEMSCRUB_CONFIG_MODE_SHIFT ) & \
0303       MEMSCRUB_CONFIG_MODE_MASK ) )
0304 #define MEMSCRUB_CONFIG_MODE( _val ) \
0305   ( ( ( _val ) << MEMSCRUB_CONFIG_MODE_SHIFT ) & \
0306     MEMSCRUB_CONFIG_MODE_MASK )
0307
0308 #define MEMSCRUB_CONFIG_ES 0x2U
0309
0310 #define MEMSCRUB_CONFIG_SCEN 0x1U
0311
0312 /** @} */
0313
0314 /**
0315  * @defgroup RTEMSDeviceGRLIBMEMSCRUBRANGEL Range low address register (RANGEL)
0316  *
0317  * @brief This group contains register bit definitions.
0318  *
0319  * @{
0320  */
0321
0322 #define MEMSCRUB_RANGEL_RLADDR_SHIFT 0
0323 #define MEMSCRUB_RANGEL_RLADDR_MASK 0xffffffffU
0324 #define MEMSCRUB_RANGEL_RLADDR_GET( _reg ) \
0325   ( ( ( _reg ) & MEMSCRUB_RANGEL_RLADDR_MASK ) >> \
0326     MEMSCRUB_RANGEL_RLADDR_SHIFT )
0327 #define MEMSCRUB_RANGEL_RLADDR_SET( _reg, _val ) \
0328   ( ( ( _reg ) & ~MEMSCRUB_RANGEL_RLADDR_MASK ) | \
0329     ( ( ( _val ) << MEMSCRUB_RANGEL_RLADDR_SHIFT ) & \
0330       MEMSCRUB_RANGEL_RLADDR_MASK ) )
0331 #define MEMSCRUB_RANGEL_RLADDR( _val ) \
0332   ( ( ( _val ) << MEMSCRUB_RANGEL_RLADDR_SHIFT ) & \
0333     MEMSCRUB_RANGEL_RLADDR_MASK )
0334
0335 /** @} */
0336
0337 /**
0338  * @defgroup RTEMSDeviceGRLIBMEMSCRUBRANGEH \
0339  *   Range high address register (RANGEH)
0340  *
0341  * @brief This group contains register bit definitions.
0342  *
0343  * @{
0344  */
0345
0346 #define MEMSCRUB_RANGEH_RHADDR_SHIFT 0
0347 #define MEMSCRUB_RANGEH_RHADDR_MASK 0xffffffffU
0348 #define MEMSCRUB_RANGEH_RHADDR_GET( _reg ) \
0349   ( ( ( _reg ) & MEMSCRUB_RANGEH_RHADDR_MASK ) >> \
0350     MEMSCRUB_RANGEH_RHADDR_SHIFT )
0351 #define MEMSCRUB_RANGEH_RHADDR_SET( _reg, _val ) \
0352   ( ( ( _reg ) & ~MEMSCRUB_RANGEH_RHADDR_MASK ) | \
0353     ( ( ( _val ) << MEMSCRUB_RANGEH_RHADDR_SHIFT ) & \
0354       MEMSCRUB_RANGEH_RHADDR_MASK ) )
0355 #define MEMSCRUB_RANGEH_RHADDR( _val ) \
0356   ( ( ( _val ) << MEMSCRUB_RANGEH_RHADDR_SHIFT ) & \
0357     MEMSCRUB_RANGEH_RHADDR_MASK )
0358
0359 /** @} */
0360
0361 /**
0362  * @defgroup RTEMSDeviceGRLIBMEMSCRUBPOS Position register (POS)
0363  *
0364  * @brief This group contains register bit definitions.
0365  *
0366  * @{
0367  */
0368
0369 #define MEMSCRUB_POS_POSITION_SHIFT 0
0370 #define MEMSCRUB_POS_POSITION_MASK 0xffffffffU
0371 #define MEMSCRUB_POS_POSITION_GET( _reg ) \
0372   ( ( ( _reg ) & MEMSCRUB_POS_POSITION_MASK ) >> \
0373     MEMSCRUB_POS_POSITION_SHIFT )
0374 #define MEMSCRUB_POS_POSITION_SET( _reg, _val ) \
0375   ( ( ( _reg ) & ~MEMSCRUB_POS_POSITION_MASK ) | \
0376     ( ( ( _val ) << MEMSCRUB_POS_POSITION_SHIFT ) & \
0377       MEMSCRUB_POS_POSITION_MASK ) )
0378 #define MEMSCRUB_POS_POSITION( _val ) \
0379   ( ( ( _val ) << MEMSCRUB_POS_POSITION_SHIFT ) & \
0380     MEMSCRUB_POS_POSITION_MASK )
0381
0382 /** @} */
0383
0384 /**
0385  * @defgroup RTEMSDeviceGRLIBMEMSCRUBETHRES Error threshold register (ETHRES)
0386  *
0387  * @brief This group contains register bit definitions.
0388  *
0389  * @{
0390  */
0391
0392 #define MEMSCRUB_ETHRES_RECT_SHIFT 22
0393 #define MEMSCRUB_ETHRES_RECT_MASK 0xffc00000U
0394 #define MEMSCRUB_ETHRES_RECT_GET( _reg ) \
0395   ( ( ( _reg ) & MEMSCRUB_ETHRES_RECT_MASK ) >> \
0396     MEMSCRUB_ETHRES_RECT_SHIFT )
0397 #define MEMSCRUB_ETHRES_RECT_SET( _reg, _val ) \
0398   ( ( ( _reg ) & ~MEMSCRUB_ETHRES_RECT_MASK ) | \
0399     ( ( ( _val ) << MEMSCRUB_ETHRES_RECT_SHIFT ) & \
0400       MEMSCRUB_ETHRES_RECT_MASK ) )
0401 #define MEMSCRUB_ETHRES_RECT( _val ) \
0402   ( ( ( _val ) << MEMSCRUB_ETHRES_RECT_SHIFT ) & \
0403     MEMSCRUB_ETHRES_RECT_MASK )
0404
0405 #define MEMSCRUB_ETHRES_BECT_SHIFT 14
0406 #define MEMSCRUB_ETHRES_BECT_MASK 0x3fc000U
0407 #define MEMSCRUB_ETHRES_BECT_GET( _reg ) \
0408   ( ( ( _reg ) & MEMSCRUB_ETHRES_BECT_MASK ) >> \
0409     MEMSCRUB_ETHRES_BECT_SHIFT )
0410 #define MEMSCRUB_ETHRES_BECT_SET( _reg, _val ) \
0411   ( ( ( _reg ) & ~MEMSCRUB_ETHRES_BECT_MASK ) | \
0412     ( ( ( _val ) << MEMSCRUB_ETHRES_BECT_SHIFT ) & \
0413       MEMSCRUB_ETHRES_BECT_MASK ) )
0414 #define MEMSCRUB_ETHRES_BECT( _val ) \
0415   ( ( ( _val ) << MEMSCRUB_ETHRES_BECT_SHIFT ) & \
0416     MEMSCRUB_ETHRES_BECT_MASK )
0417
0418 #define MEMSCRUB_ETHRES_RECTE 0x2U
0419
0420 #define MEMSCRUB_ETHRES_BECTE 0x1U
0421
0422 /** @} */
0423
0424 /**
0425  * @defgroup RTEMSDeviceGRLIBMEMSCRUBINIT Initialisation data register (INIT)
0426  *
0427  * @brief This group contains register bit definitions.
0428  *
0429  * @{
0430  */
0431
0432 #define MEMSCRUB_INIT_DATA_SHIFT 0
0433 #define MEMSCRUB_INIT_DATA_MASK 0xffffffffU
0434 #define MEMSCRUB_INIT_DATA_GET( _reg ) \
0435   ( ( ( _reg ) & MEMSCRUB_INIT_DATA_MASK ) >> \
0436     MEMSCRUB_INIT_DATA_SHIFT )
0437 #define MEMSCRUB_INIT_DATA_SET( _reg, _val ) \
0438   ( ( ( _reg ) & ~MEMSCRUB_INIT_DATA_MASK ) | \
0439     ( ( ( _val ) << MEMSCRUB_INIT_DATA_SHIFT ) & \
0440       MEMSCRUB_INIT_DATA_MASK ) )
0441 #define MEMSCRUB_INIT_DATA( _val ) \
0442   ( ( ( _val ) << MEMSCRUB_INIT_DATA_SHIFT ) & \
0443     MEMSCRUB_INIT_DATA_MASK )
0444
0445 /** @} */
0446
0447 /**
0448  * @defgroup RTEMSDeviceGRLIBMEMSCRUBRANGEL2 \
0449  *   Second range low address register (RANGEL2)
0450  *
0451  * @brief This group contains register bit definitions.
0452  *
0453  * @{
0454  */
0455
0456 #define MEMSCRUB_RANGEL2_RLADDR_SHIFT 0
0457 #define MEMSCRUB_RANGEL2_RLADDR_MASK 0xffffffffU
0458 #define MEMSCRUB_RANGEL2_RLADDR_GET( _reg ) \
0459   ( ( ( _reg ) & MEMSCRUB_RANGEL2_RLADDR_MASK ) >> \
0460     MEMSCRUB_RANGEL2_RLADDR_SHIFT )
0461 #define MEMSCRUB_RANGEL2_RLADDR_SET( _reg, _val ) \
0462   ( ( ( _reg ) & ~MEMSCRUB_RANGEL2_RLADDR_MASK ) | \
0463     ( ( ( _val ) << MEMSCRUB_RANGEL2_RLADDR_SHIFT ) & \
0464       MEMSCRUB_RANGEL2_RLADDR_MASK ) )
0465 #define MEMSCRUB_RANGEL2_RLADDR( _val ) \
0466   ( ( ( _val ) << MEMSCRUB_RANGEL2_RLADDR_SHIFT ) & \
0467     MEMSCRUB_RANGEL2_RLADDR_MASK )
0468
0469 /** @} */
0470
0471 /**
0472  * @defgroup RTEMSDeviceGRLIBMEMSCRUBRANGEH2 \
0473  *   Second range high address register (RANGEH2)
0474  *
0475  * @brief This group contains register bit definitions.
0476  *
0477  * @{
0478  */
0479
0480 #define MEMSCRUB_RANGEH2_RHADDR_SHIFT 0
0481 #define MEMSCRUB_RANGEH2_RHADDR_MASK 0xffffffffU
0482 #define MEMSCRUB_RANGEH2_RHADDR_GET( _reg ) \
0483   ( ( ( _reg ) & MEMSCRUB_RANGEH2_RHADDR_MASK ) >> \
0484     MEMSCRUB_RANGEH2_RHADDR_SHIFT )
0485 #define MEMSCRUB_RANGEH2_RHADDR_SET( _reg, _val ) \
0486   ( ( ( _reg ) & ~MEMSCRUB_RANGEH2_RHADDR_MASK ) | \
0487     ( ( ( _val ) << MEMSCRUB_RANGEH2_RHADDR_SHIFT ) & \
0488       MEMSCRUB_RANGEH2_RHADDR_MASK ) )
0489 #define MEMSCRUB_RANGEH2_RHADDR( _val ) \
0490   ( ( ( _val ) << MEMSCRUB_RANGEH2_RHADDR_SHIFT ) & \
0491     MEMSCRUB_RANGEH2_RHADDR_MASK )
0492
0493 /** @} */
0494
0495 /**
0496  * @brief This structure defines the MEMSCRUB register block memory map.
0497  */
0498 typedef struct memscrub {
0499   /**
0500    * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBAHBS.
0501    */
0502   uint32_t ahbs;
0503
0504   /**
0505    * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBAHBFAR.
0506    */
0507   uint32_t ahbfar;
0508
0509   /**
0510    * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBAHBERC.
0511    */
0512   uint32_t ahberc;
0513
0514   uint32_t reserved_c_10;
0515
0516   /**
0517    * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBSTAT.
0518    */
0519   uint32_t stat;
0520
0521   /**
0522    * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBCONFIG.
0523    */
0524   uint32_t config;
0525
0526   /**
0527    * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBRANGEL.
0528    */
0529   uint32_t rangel;
0530
0531   /**
0532    * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBRANGEH.
0533    */
0534   uint32_t rangeh;
0535
0536   /**
0537    * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBPOS.
0538    */
0539   uint32_t pos;
0540
0541   /**
0542    * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBETHRES.
0543    */
0544   uint32_t ethres;
0545
0546   /**
0547    * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBINIT.
0548    */
0549   uint32_t init;
0550
0551   /**
0552    * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBRANGEL2.
0553    */
0554   uint32_t rangel2;
0555
0556   /**
0557    * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBRANGEH2.
0558    */
0559   uint32_t rangeh2;
0560 } memscrub;
0561
0562 /** @} */
0563
0564 #ifdef __cplusplus
0565 }
0566 #endif
0567
0568 #endif /* _GRLIB_MEMSCRUB_REGS_H */