include/grlib/l4stat-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRLIBL4STAT
0007  *
0008  * @brief This header file defines the L4STAT register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/l4stat-header */
0054
0055 #ifndef _GRLIB_L4STAT_REGS_H
0056 #define _GRLIB_L4STAT_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/l4stat */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRLIBL4STAT L4STAT
0068  *
0069  * @ingroup RTEMSDeviceGRLIB
0070  *
0071  * @brief This group contains the L4STAT interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRLIBL4STATCVAL Counter 0-15 value register (CVAL)
0078  *
0079  * @brief This group contains register bit definitions.
0080  *
0081  * @{
0082  */
0083
0084 #define L4STAT_CVAL_CVAL_SHIFT 0
0085 #define L4STAT_CVAL_CVAL_MASK 0xffffffffU
0086 #define L4STAT_CVAL_CVAL_GET( _reg ) \
0087   ( ( ( _reg ) & L4STAT_CVAL_CVAL_MASK ) >> \
0088     L4STAT_CVAL_CVAL_SHIFT )
0089 #define L4STAT_CVAL_CVAL_SET( _reg, _val ) \
0090   ( ( ( _reg ) & ~L4STAT_CVAL_CVAL_MASK ) | \
0091     ( ( ( _val ) << L4STAT_CVAL_CVAL_SHIFT ) & \
0092       L4STAT_CVAL_CVAL_MASK ) )
0093 #define L4STAT_CVAL_CVAL( _val ) \
0094   ( ( ( _val ) << L4STAT_CVAL_CVAL_SHIFT ) & \
0095     L4STAT_CVAL_CVAL_MASK )
0096
0097 /** @} */
0098
0099 /**
0100  * @defgroup RTEMSDeviceGRLIBL4STATCCTRL Counter 0-15 control register (CCTRL)
0101  *
0102  * @brief This group contains register bit definitions.
0103  *
0104  * @{
0105  */
0106
0107 #define L4STAT_CCTRL_NCPU_SHIFT 28
0108 #define L4STAT_CCTRL_NCPU_MASK 0xf0000000U
0109 #define L4STAT_CCTRL_NCPU_GET( _reg ) \
0110   ( ( ( _reg ) & L4STAT_CCTRL_NCPU_MASK ) >> \
0111     L4STAT_CCTRL_NCPU_SHIFT )
0112 #define L4STAT_CCTRL_NCPU_SET( _reg, _val ) \
0113   ( ( ( _reg ) & ~L4STAT_CCTRL_NCPU_MASK ) | \
0114     ( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & \
0115       L4STAT_CCTRL_NCPU_MASK ) )
0116 #define L4STAT_CCTRL_NCPU( _val ) \
0117   ( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & \
0118     L4STAT_CCTRL_NCPU_MASK )
0119
0120 #define L4STAT_CCTRL_NCNT_SHIFT 23
0121 #define L4STAT_CCTRL_NCNT_MASK 0xf800000U
0122 #define L4STAT_CCTRL_NCNT_GET( _reg ) \
0123   ( ( ( _reg ) & L4STAT_CCTRL_NCNT_MASK ) >> \
0124     L4STAT_CCTRL_NCNT_SHIFT )
0125 #define L4STAT_CCTRL_NCNT_SET( _reg, _val ) \
0126   ( ( ( _reg ) & ~L4STAT_CCTRL_NCNT_MASK ) | \
0127     ( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & \
0128       L4STAT_CCTRL_NCNT_MASK ) )
0129 #define L4STAT_CCTRL_NCNT( _val ) \
0130   ( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & \
0131     L4STAT_CCTRL_NCNT_MASK )
0132
0133 #define L4STAT_CCTRL_MC 0x400000U
0134
0135 #define L4STAT_CCTRL_IA 0x200000U
0136
0137 #define L4STAT_CCTRL_DS 0x100000U
0138
0139 #define L4STAT_CCTRL_EE 0x80000U
0140
0141 #define L4STAT_CCTRL_AE 0x40000U
0142
0143 #define L4STAT_CCTRL_EL 0x20000U
0144
0145 #define L4STAT_CCTRL_CD 0x10000U
0146
0147 #define L4STAT_CCTRL_SU_SHIFT 14
0148 #define L4STAT_CCTRL_SU_MASK 0xc000U
0149 #define L4STAT_CCTRL_SU_GET( _reg ) \
0150   ( ( ( _reg ) & L4STAT_CCTRL_SU_MASK ) >> \
0151     L4STAT_CCTRL_SU_SHIFT )
0152 #define L4STAT_CCTRL_SU_SET( _reg, _val ) \
0153   ( ( ( _reg ) & ~L4STAT_CCTRL_SU_MASK ) | \
0154     ( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & \
0155       L4STAT_CCTRL_SU_MASK ) )
0156 #define L4STAT_CCTRL_SU( _val ) \
0157   ( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & \
0158     L4STAT_CCTRL_SU_MASK )
0159
0160 #define L4STAT_CCTRL_CL 0x2000U
0161
0162 #define L4STAT_CCTRL_EN 0x1000U
0163
0164 #define L4STAT_CCTRL_EVENT_ID_SHIFT 4
0165 #define L4STAT_CCTRL_EVENT_ID_MASK 0xff0U
0166 #define L4STAT_CCTRL_EVENT_ID_GET( _reg ) \
0167   ( ( ( _reg ) & L4STAT_CCTRL_EVENT_ID_MASK ) >> \
0168     L4STAT_CCTRL_EVENT_ID_SHIFT )
0169 #define L4STAT_CCTRL_EVENT_ID_SET( _reg, _val ) \
0170   ( ( ( _reg ) & ~L4STAT_CCTRL_EVENT_ID_MASK ) | \
0171     ( ( ( _val ) << L4STAT_CCTRL_EVENT_ID_SHIFT ) & \
0172       L4STAT_CCTRL_EVENT_ID_MASK ) )
0173 #define L4STAT_CCTRL_EVENT_ID( _val ) \
0174   ( ( ( _val ) << L4STAT_CCTRL_EVENT_ID_SHIFT ) & \
0175     L4STAT_CCTRL_EVENT_ID_MASK )
0176
0177 #define L4STAT_CCTRL_CPU_AHBM_SHIFT 0
0178 #define L4STAT_CCTRL_CPU_AHBM_MASK 0xfU
0179 #define L4STAT_CCTRL_CPU_AHBM_GET( _reg ) \
0180   ( ( ( _reg ) & L4STAT_CCTRL_CPU_AHBM_MASK ) >> \
0181     L4STAT_CCTRL_CPU_AHBM_SHIFT )
0182 #define L4STAT_CCTRL_CPU_AHBM_SET( _reg, _val ) \
0183   ( ( ( _reg ) & ~L4STAT_CCTRL_CPU_AHBM_MASK ) | \
0184     ( ( ( _val ) << L4STAT_CCTRL_CPU_AHBM_SHIFT ) & \
0185       L4STAT_CCTRL_CPU_AHBM_MASK ) )
0186 #define L4STAT_CCTRL_CPU_AHBM( _val ) \
0187   ( ( ( _val ) << L4STAT_CCTRL_CPU_AHBM_SHIFT ) & \
0188     L4STAT_CCTRL_CPU_AHBM_MASK )
0189
0190 /** @} */
0191
0192 /**
0193  * @defgroup RTEMSDeviceGRLIBL4STATCSVAL \
0194  *   Counter 0-15 max/latch register (CSVAL)
0195  *
0196  * @brief This group contains register bit definitions.
0197  *
0198  * @{
0199  */
0200
0201 #define L4STAT_CSVAL_CSVAL_SHIFT 0
0202 #define L4STAT_CSVAL_CSVAL_MASK 0xffffffffU
0203 #define L4STAT_CSVAL_CSVAL_GET( _reg ) \
0204   ( ( ( _reg ) & L4STAT_CSVAL_CSVAL_MASK ) >> \
0205     L4STAT_CSVAL_CSVAL_SHIFT )
0206 #define L4STAT_CSVAL_CSVAL_SET( _reg, _val ) \
0207   ( ( ( _reg ) & ~L4STAT_CSVAL_CSVAL_MASK ) | \
0208     ( ( ( _val ) << L4STAT_CSVAL_CSVAL_SHIFT ) & \
0209       L4STAT_CSVAL_CSVAL_MASK ) )
0210 #define L4STAT_CSVAL_CSVAL( _val ) \
0211   ( ( ( _val ) << L4STAT_CSVAL_CSVAL_SHIFT ) & \
0212     L4STAT_CSVAL_CSVAL_MASK )
0213
0214 /** @} */
0215
0216 /**
0217  * @defgroup RTEMSDeviceGRLIBL4STATTSTAMP Timestamp register (TSTAMP)
0218  *
0219  * @brief This group contains register bit definitions.
0220  *
0221  * @{
0222  */
0223
0224 #define L4STAT_TSTAMP_TSTAMP_SHIFT 0
0225 #define L4STAT_TSTAMP_TSTAMP_MASK 0xffffffffU
0226 #define L4STAT_TSTAMP_TSTAMP_GET( _reg ) \
0227   ( ( ( _reg ) & L4STAT_TSTAMP_TSTAMP_MASK ) >> \
0228     L4STAT_TSTAMP_TSTAMP_SHIFT )
0229 #define L4STAT_TSTAMP_TSTAMP_SET( _reg, _val ) \
0230   ( ( ( _reg ) & ~L4STAT_TSTAMP_TSTAMP_MASK ) | \
0231     ( ( ( _val ) << L4STAT_TSTAMP_TSTAMP_SHIFT ) & \
0232       L4STAT_TSTAMP_TSTAMP_MASK ) )
0233 #define L4STAT_TSTAMP_TSTAMP( _val ) \
0234   ( ( ( _val ) << L4STAT_TSTAMP_TSTAMP_SHIFT ) & \
0235     L4STAT_TSTAMP_TSTAMP_MASK )
0236
0237 /** @} */
0238
0239 /**
0240  * @brief This structure defines the L4STAT register block memory map.
0241  */
0242 typedef struct l4stat {
0243   /**
0244    * @brief See @ref RTEMSDeviceGRLIBL4STATCVAL.
0245    */
0246   uint32_t cval_0;
0247
0248   uint32_t reserved_4_3c[ 14 ];
0249
0250   /**
0251    * @brief See @ref RTEMSDeviceGRLIBL4STATCVAL.
0252    */
0253   uint32_t cval_1;
0254
0255   uint32_t reserved_40_80[ 16 ];
0256
0257   /**
0258    * @brief See @ref RTEMSDeviceGRLIBL4STATCCTRL.
0259    */
0260   uint32_t cctrl_0;
0261
0262   uint32_t reserved_84_cc[ 18 ];
0263
0264   /**
0265    * @brief See @ref RTEMSDeviceGRLIBL4STATCCTRL.
0266    */
0267   uint32_t cctrl_1;
0268
0269   uint32_t reserved_d0_100[ 12 ];
0270
0271   /**
0272    * @brief See @ref RTEMSDeviceGRLIBL4STATCSVAL.
0273    */
0274   uint32_t csval_0;
0275
0276   uint32_t reserved_104_13c[ 14 ];
0277
0278   /**
0279    * @brief See @ref RTEMSDeviceGRLIBL4STATCSVAL.
0280    */
0281   uint32_t csval_1;
0282
0283   uint32_t reserved_140_180[ 16 ];
0284
0285   /**
0286    * @brief See @ref RTEMSDeviceGRLIBL4STATTSTAMP.
0287    */
0288   uint32_t tstamp;
0289 } l4stat;
0290
0291 /** @} */
0292
0293 #ifdef __cplusplus
0294 }
0295 #endif
0296
0297 #endif /* _GRLIB_L4STAT_REGS_H */