include/grlib/l2cache-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRLIBL2CACHE
0007  *
0008  * @brief This header file defines the L2CACHE register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/l2cache-header */
0054
0055 #ifndef _GRLIB_L2CACHE_REGS_H
0056 #define _GRLIB_L2CACHE_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/l2cache */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRLIBL2CACHE L2CACHE
0068  *
0069  * @ingroup RTEMSDeviceGRLIB
0070  *
0071  * @brief This group contains the L2CACHE interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRLIBL2CACHEL2CC L2C Control register (L2CC)
0078  *
0079  * @brief This group contains register bit definitions.
0080  *
0081  * @{
0082  */
0083
0084 #define L2CACHE_L2CC_EN 0x80000000U
0085
0086 #define L2CACHE_L2CC_EDAC 0x40000000U
0087
0088 #define L2CACHE_L2CC_REPL_SHIFT 28
0089 #define L2CACHE_L2CC_REPL_MASK 0x30000000U
0090 #define L2CACHE_L2CC_REPL_GET( _reg ) \
0091   ( ( ( _reg ) & L2CACHE_L2CC_REPL_MASK ) >> \
0092     L2CACHE_L2CC_REPL_SHIFT )
0093 #define L2CACHE_L2CC_REPL_SET( _reg, _val ) \
0094   ( ( ( _reg ) & ~L2CACHE_L2CC_REPL_MASK ) | \
0095     ( ( ( _val ) << L2CACHE_L2CC_REPL_SHIFT ) & \
0096       L2CACHE_L2CC_REPL_MASK ) )
0097 #define L2CACHE_L2CC_REPL( _val ) \
0098   ( ( ( _val ) << L2CACHE_L2CC_REPL_SHIFT ) & \
0099     L2CACHE_L2CC_REPL_MASK )
0100
0101 #define L2CACHE_L2CC_BBS_SHIFT 16
0102 #define L2CACHE_L2CC_BBS_MASK 0x70000U
0103 #define L2CACHE_L2CC_BBS_GET( _reg ) \
0104   ( ( ( _reg ) & L2CACHE_L2CC_BBS_MASK ) >> \
0105     L2CACHE_L2CC_BBS_SHIFT )
0106 #define L2CACHE_L2CC_BBS_SET( _reg, _val ) \
0107   ( ( ( _reg ) & ~L2CACHE_L2CC_BBS_MASK ) | \
0108     ( ( ( _val ) << L2CACHE_L2CC_BBS_SHIFT ) & \
0109       L2CACHE_L2CC_BBS_MASK ) )
0110 #define L2CACHE_L2CC_BBS( _val ) \
0111   ( ( ( _val ) << L2CACHE_L2CC_BBS_SHIFT ) & \
0112     L2CACHE_L2CC_BBS_MASK )
0113
0114 #define L2CACHE_L2CC_INDEX_WAY_SHIFT 12
0115 #define L2CACHE_L2CC_INDEX_WAY_MASK 0xf000U
0116 #define L2CACHE_L2CC_INDEX_WAY_GET( _reg ) \
0117   ( ( ( _reg ) & L2CACHE_L2CC_INDEX_WAY_MASK ) >> \
0118     L2CACHE_L2CC_INDEX_WAY_SHIFT )
0119 #define L2CACHE_L2CC_INDEX_WAY_SET( _reg, _val ) \
0120   ( ( ( _reg ) & ~L2CACHE_L2CC_INDEX_WAY_MASK ) | \
0121     ( ( ( _val ) << L2CACHE_L2CC_INDEX_WAY_SHIFT ) & \
0122       L2CACHE_L2CC_INDEX_WAY_MASK ) )
0123 #define L2CACHE_L2CC_INDEX_WAY( _val ) \
0124   ( ( ( _val ) << L2CACHE_L2CC_INDEX_WAY_SHIFT ) & \
0125     L2CACHE_L2CC_INDEX_WAY_MASK )
0126
0127 #define L2CACHE_L2CC_LOCK_SHIFT 8
0128 #define L2CACHE_L2CC_LOCK_MASK 0xf00U
0129 #define L2CACHE_L2CC_LOCK_GET( _reg ) \
0130   ( ( ( _reg ) & L2CACHE_L2CC_LOCK_MASK ) >> \
0131     L2CACHE_L2CC_LOCK_SHIFT )
0132 #define L2CACHE_L2CC_LOCK_SET( _reg, _val ) \
0133   ( ( ( _reg ) & ~L2CACHE_L2CC_LOCK_MASK ) | \
0134     ( ( ( _val ) << L2CACHE_L2CC_LOCK_SHIFT ) & \
0135       L2CACHE_L2CC_LOCK_MASK ) )
0136 #define L2CACHE_L2CC_LOCK( _val ) \
0137   ( ( ( _val ) << L2CACHE_L2CC_LOCK_SHIFT ) & \
0138     L2CACHE_L2CC_LOCK_MASK )
0139
0140 #define L2CACHE_L2CC_HPRHB 0x20U
0141
0142 #define L2CACHE_L2CC_HPB 0x10U
0143
0144 #define L2CACHE_L2CC_UC 0x8U
0145
0146 #define L2CACHE_L2CC_HC 0x4U
0147
0148 #define L2CACHE_L2CC_WP 0x2U
0149
0150 #define L2CACHE_L2CC_HP 0x1U
0151
0152 /** @} */
0153
0154 /**
0155  * @defgroup RTEMSDeviceGRLIBL2CACHEL2CS L2C Status register (L2CS)
0156  *
0157  * @brief This group contains register bit definitions.
0158  *
0159  * @{
0160  */
0161
0162 #define L2CACHE_L2CS_LS 0x1000000U
0163
0164 #define L2CACHE_L2CS_AT 0x800000U
0165
0166 #define L2CACHE_L2CS_MP 0x400000U
0167
0168 #define L2CACHE_L2CS_MTRR_SHIFT 16
0169 #define L2CACHE_L2CS_MTRR_MASK 0x3f0000U
0170 #define L2CACHE_L2CS_MTRR_GET( _reg ) \
0171   ( ( ( _reg ) & L2CACHE_L2CS_MTRR_MASK ) >> \
0172     L2CACHE_L2CS_MTRR_SHIFT )
0173 #define L2CACHE_L2CS_MTRR_SET( _reg, _val ) \
0174   ( ( ( _reg ) & ~L2CACHE_L2CS_MTRR_MASK ) | \
0175     ( ( ( _val ) << L2CACHE_L2CS_MTRR_SHIFT ) & \
0176       L2CACHE_L2CS_MTRR_MASK ) )
0177 #define L2CACHE_L2CS_MTRR( _val ) \
0178   ( ( ( _val ) << L2CACHE_L2CS_MTRR_SHIFT ) & \
0179     L2CACHE_L2CS_MTRR_MASK )
0180
0181 #define L2CACHE_L2CS_BBUS_W_SHIFT 13
0182 #define L2CACHE_L2CS_BBUS_W_MASK 0xe000U
0183 #define L2CACHE_L2CS_BBUS_W_GET( _reg ) \
0184   ( ( ( _reg ) & L2CACHE_L2CS_BBUS_W_MASK ) >> \
0185     L2CACHE_L2CS_BBUS_W_SHIFT )
0186 #define L2CACHE_L2CS_BBUS_W_SET( _reg, _val ) \
0187   ( ( ( _reg ) & ~L2CACHE_L2CS_BBUS_W_MASK ) | \
0188     ( ( ( _val ) << L2CACHE_L2CS_BBUS_W_SHIFT ) & \
0189       L2CACHE_L2CS_BBUS_W_MASK ) )
0190 #define L2CACHE_L2CS_BBUS_W( _val ) \
0191   ( ( ( _val ) << L2CACHE_L2CS_BBUS_W_SHIFT ) & \
0192     L2CACHE_L2CS_BBUS_W_MASK )
0193
0194 #define L2CACHE_L2CS_WAY_SIZE_SHIFT 2
0195 #define L2CACHE_L2CS_WAY_SIZE_MASK 0x1ffcU
0196 #define L2CACHE_L2CS_WAY_SIZE_GET( _reg ) \
0197   ( ( ( _reg ) & L2CACHE_L2CS_WAY_SIZE_MASK ) >> \
0198     L2CACHE_L2CS_WAY_SIZE_SHIFT )
0199 #define L2CACHE_L2CS_WAY_SIZE_SET( _reg, _val ) \
0200   ( ( ( _reg ) & ~L2CACHE_L2CS_WAY_SIZE_MASK ) | \
0201     ( ( ( _val ) << L2CACHE_L2CS_WAY_SIZE_SHIFT ) & \
0202       L2CACHE_L2CS_WAY_SIZE_MASK ) )
0203 #define L2CACHE_L2CS_WAY_SIZE( _val ) \
0204   ( ( ( _val ) << L2CACHE_L2CS_WAY_SIZE_SHIFT ) & \
0205     L2CACHE_L2CS_WAY_SIZE_MASK )
0206
0207 #define L2CACHE_L2CS_WAY_SHIFT 0
0208 #define L2CACHE_L2CS_WAY_MASK 0x3U
0209 #define L2CACHE_L2CS_WAY_GET( _reg ) \
0210   ( ( ( _reg ) & L2CACHE_L2CS_WAY_MASK ) >> \
0211     L2CACHE_L2CS_WAY_SHIFT )
0212 #define L2CACHE_L2CS_WAY_SET( _reg, _val ) \
0213   ( ( ( _reg ) & ~L2CACHE_L2CS_WAY_MASK ) | \
0214     ( ( ( _val ) << L2CACHE_L2CS_WAY_SHIFT ) & \
0215       L2CACHE_L2CS_WAY_MASK ) )
0216 #define L2CACHE_L2CS_WAY( _val ) \
0217   ( ( ( _val ) << L2CACHE_L2CS_WAY_SHIFT ) & \
0218     L2CACHE_L2CS_WAY_MASK )
0219
0220 /** @} */
0221
0222 /**
0223  * @defgroup RTEMSDeviceGRLIBL2CACHEL2CFMA \
0224  *   L2C Flush (Memory address) register (L2CFMA)
0225  *
0226  * @brief This group contains register bit definitions.
0227  *
0228  * @{
0229  */
0230
0231 #define L2CACHE_L2CFMA_ADDR_SHIFT 5
0232 #define L2CACHE_L2CFMA_ADDR_MASK 0xffffffe0U
0233 #define L2CACHE_L2CFMA_ADDR_GET( _reg ) \
0234   ( ( ( _reg ) & L2CACHE_L2CFMA_ADDR_MASK ) >> \
0235     L2CACHE_L2CFMA_ADDR_SHIFT )
0236 #define L2CACHE_L2CFMA_ADDR_SET( _reg, _val ) \
0237   ( ( ( _reg ) & ~L2CACHE_L2CFMA_ADDR_MASK ) | \
0238     ( ( ( _val ) << L2CACHE_L2CFMA_ADDR_SHIFT ) & \
0239       L2CACHE_L2CFMA_ADDR_MASK ) )
0240 #define L2CACHE_L2CFMA_ADDR( _val ) \
0241   ( ( ( _val ) << L2CACHE_L2CFMA_ADDR_SHIFT ) & \
0242     L2CACHE_L2CFMA_ADDR_MASK )
0243
0244 #define L2CACHE_L2CFMA_DI 0x8U
0245
0246 #define L2CACHE_L2CFMA_FMODE_SHIFT 0
0247 #define L2CACHE_L2CFMA_FMODE_MASK 0x7U
0248 #define L2CACHE_L2CFMA_FMODE_GET( _reg ) \
0249   ( ( ( _reg ) & L2CACHE_L2CFMA_FMODE_MASK ) >> \
0250     L2CACHE_L2CFMA_FMODE_SHIFT )
0251 #define L2CACHE_L2CFMA_FMODE_SET( _reg, _val ) \
0252   ( ( ( _reg ) & ~L2CACHE_L2CFMA_FMODE_MASK ) | \
0253     ( ( ( _val ) << L2CACHE_L2CFMA_FMODE_SHIFT ) & \
0254       L2CACHE_L2CFMA_FMODE_MASK ) )
0255 #define L2CACHE_L2CFMA_FMODE( _val ) \
0256   ( ( ( _val ) << L2CACHE_L2CFMA_FMODE_SHIFT ) & \
0257     L2CACHE_L2CFMA_FMODE_MASK )
0258
0259 /** @} */
0260
0261 /**
0262  * @defgroup RTEMSDeviceGRLIBL2CACHEL2CFSI \
0263  *   L2C Flush (Set, Index) register (L2CFSI)
0264  *
0265  * @brief This group contains register bit definitions.
0266  *
0267  * @{
0268  */
0269
0270 #define L2CACHE_L2CFSI_INDEX_SHIFT 16
0271 #define L2CACHE_L2CFSI_INDEX_MASK 0xffff0000U
0272 #define L2CACHE_L2CFSI_INDEX_GET( _reg ) \
0273   ( ( ( _reg ) & L2CACHE_L2CFSI_INDEX_MASK ) >> \
0274     L2CACHE_L2CFSI_INDEX_SHIFT )
0275 #define L2CACHE_L2CFSI_INDEX_SET( _reg, _val ) \
0276   ( ( ( _reg ) & ~L2CACHE_L2CFSI_INDEX_MASK ) | \
0277     ( ( ( _val ) << L2CACHE_L2CFSI_INDEX_SHIFT ) & \
0278       L2CACHE_L2CFSI_INDEX_MASK ) )
0279 #define L2CACHE_L2CFSI_INDEX( _val ) \
0280   ( ( ( _val ) << L2CACHE_L2CFSI_INDEX_SHIFT ) & \
0281     L2CACHE_L2CFSI_INDEX_MASK )
0282
0283 #define L2CACHE_L2CFSI_TAG_SHIFT 10
0284 #define L2CACHE_L2CFSI_TAG_MASK 0xfffffc00U
0285 #define L2CACHE_L2CFSI_TAG_GET( _reg ) \
0286   ( ( ( _reg ) & L2CACHE_L2CFSI_TAG_MASK ) >> \
0287     L2CACHE_L2CFSI_TAG_SHIFT )
0288 #define L2CACHE_L2CFSI_TAG_SET( _reg, _val ) \
0289   ( ( ( _reg ) & ~L2CACHE_L2CFSI_TAG_MASK ) | \
0290     ( ( ( _val ) << L2CACHE_L2CFSI_TAG_SHIFT ) & \
0291       L2CACHE_L2CFSI_TAG_MASK ) )
0292 #define L2CACHE_L2CFSI_TAG( _val ) \
0293   ( ( ( _val ) << L2CACHE_L2CFSI_TAG_SHIFT ) & \
0294     L2CACHE_L2CFSI_TAG_MASK )
0295
0296 #define L2CACHE_L2CFSI_FL 0x200U
0297
0298 #define L2CACHE_L2CFSI_VB 0x100U
0299
0300 #define L2CACHE_L2CFSI_DB 0x80U
0301
0302 #define L2CACHE_L2CFSI_WAY_SHIFT 4
0303 #define L2CACHE_L2CFSI_WAY_MASK 0x30U
0304 #define L2CACHE_L2CFSI_WAY_GET( _reg ) \
0305   ( ( ( _reg ) & L2CACHE_L2CFSI_WAY_MASK ) >> \
0306     L2CACHE_L2CFSI_WAY_SHIFT )
0307 #define L2CACHE_L2CFSI_WAY_SET( _reg, _val ) \
0308   ( ( ( _reg ) & ~L2CACHE_L2CFSI_WAY_MASK ) | \
0309     ( ( ( _val ) << L2CACHE_L2CFSI_WAY_SHIFT ) & \
0310       L2CACHE_L2CFSI_WAY_MASK ) )
0311 #define L2CACHE_L2CFSI_WAY( _val ) \
0312   ( ( ( _val ) << L2CACHE_L2CFSI_WAY_SHIFT ) & \
0313     L2CACHE_L2CFSI_WAY_MASK )
0314
0315 #define L2CACHE_L2CFSI_DI 0x8U
0316
0317 #define L2CACHE_L2CFSI_WF 0x4U
0318
0319 #define L2CACHE_L2CFSI_FMODE_SHIFT 0
0320 #define L2CACHE_L2CFSI_FMODE_MASK 0x3U
0321 #define L2CACHE_L2CFSI_FMODE_GET( _reg ) \
0322   ( ( ( _reg ) & L2CACHE_L2CFSI_FMODE_MASK ) >> \
0323     L2CACHE_L2CFSI_FMODE_SHIFT )
0324 #define L2CACHE_L2CFSI_FMODE_SET( _reg, _val ) \
0325   ( ( ( _reg ) & ~L2CACHE_L2CFSI_FMODE_MASK ) | \
0326     ( ( ( _val ) << L2CACHE_L2CFSI_FMODE_SHIFT ) & \
0327       L2CACHE_L2CFSI_FMODE_MASK ) )
0328 #define L2CACHE_L2CFSI_FMODE( _val ) \
0329   ( ( ( _val ) << L2CACHE_L2CFSI_FMODE_SHIFT ) & \
0330     L2CACHE_L2CFSI_FMODE_MASK )
0331
0332 /** @} */
0333
0334 /**
0335  * @defgroup RTEMSDeviceGRLIBL2CACHEL2CERR \
0336  *   L2CError status/control register (L2CERR)
0337  *
0338  * @brief This group contains register bit definitions.
0339  *
0340  * @{
0341  */
0342
0343 #define L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT 28
0344 #define L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK 0xf0000000U
0345 #define L2CACHE_L2CERR_AHB_MASTER_INDEX_GET( _reg ) \
0346   ( ( ( _reg ) & L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK ) >> \
0347     L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT )
0348 #define L2CACHE_L2CERR_AHB_MASTER_INDEX_SET( _reg, _val ) \
0349   ( ( ( _reg ) & ~L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK ) | \
0350     ( ( ( _val ) << L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT ) & \
0351       L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK ) )
0352 #define L2CACHE_L2CERR_AHB_MASTER_INDEX( _val ) \
0353   ( ( ( _val ) << L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT ) & \
0354     L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK )
0355
0356 #define L2CACHE_L2CERR_SCRUB 0x8000000U
0357
0358 #define L2CACHE_L2CERR_TYPE_SHIFT 24
0359 #define L2CACHE_L2CERR_TYPE_MASK 0x7000000U
0360 #define L2CACHE_L2CERR_TYPE_GET( _reg ) \
0361   ( ( ( _reg ) & L2CACHE_L2CERR_TYPE_MASK ) >> \
0362     L2CACHE_L2CERR_TYPE_SHIFT )
0363 #define L2CACHE_L2CERR_TYPE_SET( _reg, _val ) \
0364   ( ( ( _reg ) & ~L2CACHE_L2CERR_TYPE_MASK ) | \
0365     ( ( ( _val ) << L2CACHE_L2CERR_TYPE_SHIFT ) & \
0366       L2CACHE_L2CERR_TYPE_MASK ) )
0367 #define L2CACHE_L2CERR_TYPE( _val ) \
0368   ( ( ( _val ) << L2CACHE_L2CERR_TYPE_SHIFT ) & \
0369     L2CACHE_L2CERR_TYPE_MASK )
0370
0371 #define L2CACHE_L2CERR_TAG_DATA 0x800000U
0372
0373 #define L2CACHE_L2CERR_COR_UCOR 0x400000U
0374
0375 #define L2CACHE_L2CERR_MULTI 0x200000U
0376
0377 #define L2CACHE_L2CERR_VALID 0x100000U
0378
0379 #define L2CACHE_L2CERR_DISERESP 0x80000U
0380
0381 #define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT 16
0382 #define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK 0x70000U
0383 #define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_GET( _reg ) \
0384   ( ( ( _reg ) & L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK ) >> \
0385     L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT )
0386 #define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SET( _reg, _val ) \
0387   ( ( ( _reg ) & ~L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK ) | \
0388     ( ( ( _val ) << L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT ) & \
0389       L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK ) )
0390 #define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER( _val ) \
0391   ( ( ( _val ) << L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT ) & \
0392     L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK )
0393
0394 #define L2CACHE_L2CERR_IRQ_PENDING_SHIFT 12
0395 #define L2CACHE_L2CERR_IRQ_PENDING_MASK 0xf000U
0396 #define L2CACHE_L2CERR_IRQ_PENDING_GET( _reg ) \
0397   ( ( ( _reg ) & L2CACHE_L2CERR_IRQ_PENDING_MASK ) >> \
0398     L2CACHE_L2CERR_IRQ_PENDING_SHIFT )
0399 #define L2CACHE_L2CERR_IRQ_PENDING_SET( _reg, _val ) \
0400   ( ( ( _reg ) & ~L2CACHE_L2CERR_IRQ_PENDING_MASK ) | \
0401     ( ( ( _val ) << L2CACHE_L2CERR_IRQ_PENDING_SHIFT ) & \
0402       L2CACHE_L2CERR_IRQ_PENDING_MASK ) )
0403 #define L2CACHE_L2CERR_IRQ_PENDING( _val ) \
0404   ( ( ( _val ) << L2CACHE_L2CERR_IRQ_PENDING_SHIFT ) & \
0405     L2CACHE_L2CERR_IRQ_PENDING_MASK )
0406
0407 #define L2CACHE_L2CERR_IRQ_MASK_SHIFT 8
0408 #define L2CACHE_L2CERR_IRQ_MASK_MASK 0xf00U
0409 #define L2CACHE_L2CERR_IRQ_MASK_GET( _reg ) \
0410   ( ( ( _reg ) & L2CACHE_L2CERR_IRQ_MASK_MASK ) >> \
0411     L2CACHE_L2CERR_IRQ_MASK_SHIFT )
0412 #define L2CACHE_L2CERR_IRQ_MASK_SET( _reg, _val ) \
0413   ( ( ( _reg ) & ~L2CACHE_L2CERR_IRQ_MASK_MASK ) | \
0414     ( ( ( _val ) << L2CACHE_L2CERR_IRQ_MASK_SHIFT ) & \
0415       L2CACHE_L2CERR_IRQ_MASK_MASK ) )
0416 #define L2CACHE_L2CERR_IRQ_MASK( _val ) \
0417   ( ( ( _val ) << L2CACHE_L2CERR_IRQ_MASK_SHIFT ) & \
0418     L2CACHE_L2CERR_IRQ_MASK_MASK )
0419
0420 #define L2CACHE_L2CERR_SELECT_CB_SHIFT 6
0421 #define L2CACHE_L2CERR_SELECT_CB_MASK 0xc0U
0422 #define L2CACHE_L2CERR_SELECT_CB_GET( _reg ) \
0423   ( ( ( _reg ) & L2CACHE_L2CERR_SELECT_CB_MASK ) >> \
0424     L2CACHE_L2CERR_SELECT_CB_SHIFT )
0425 #define L2CACHE_L2CERR_SELECT_CB_SET( _reg, _val ) \
0426   ( ( ( _reg ) & ~L2CACHE_L2CERR_SELECT_CB_MASK ) | \
0427     ( ( ( _val ) << L2CACHE_L2CERR_SELECT_CB_SHIFT ) & \
0428       L2CACHE_L2CERR_SELECT_CB_MASK ) )
0429 #define L2CACHE_L2CERR_SELECT_CB( _val ) \
0430   ( ( ( _val ) << L2CACHE_L2CERR_SELECT_CB_SHIFT ) & \
0431     L2CACHE_L2CERR_SELECT_CB_MASK )
0432
0433 #define L2CACHE_L2CERR_SELECT_TCB_SHIFT 4
0434 #define L2CACHE_L2CERR_SELECT_TCB_MASK 0x30U
0435 #define L2CACHE_L2CERR_SELECT_TCB_GET( _reg ) \
0436   ( ( ( _reg ) & L2CACHE_L2CERR_SELECT_TCB_MASK ) >> \
0437     L2CACHE_L2CERR_SELECT_TCB_SHIFT )
0438 #define L2CACHE_L2CERR_SELECT_TCB_SET( _reg, _val ) \
0439   ( ( ( _reg ) & ~L2CACHE_L2CERR_SELECT_TCB_MASK ) | \
0440     ( ( ( _val ) << L2CACHE_L2CERR_SELECT_TCB_SHIFT ) & \
0441       L2CACHE_L2CERR_SELECT_TCB_MASK ) )
0442 #define L2CACHE_L2CERR_SELECT_TCB( _val ) \
0443   ( ( ( _val ) << L2CACHE_L2CERR_SELECT_TCB_SHIFT ) & \
0444     L2CACHE_L2CERR_SELECT_TCB_MASK )
0445
0446 #define L2CACHE_L2CERR_XCB 0x8U
0447
0448 #define L2CACHE_L2CERR_RCB 0x4U
0449
0450 #define L2CACHE_L2CERR_COMP 0x2U
0451
0452 #define L2CACHE_L2CERR_RST 0x1U
0453
0454 /** @} */
0455
0456 /**
0457  * @defgroup RTEMSDeviceGRLIBL2CACHEL2CERRA \
0458  *   L2C Error address register (L2CERRA)
0459  *
0460  * @brief This group contains register bit definitions.
0461  *
0462  * @{
0463  */
0464
0465 #define L2CACHE_L2CERRA_EADDR_SHIFT 0
0466 #define L2CACHE_L2CERRA_EADDR_MASK 0xffffffffU
0467 #define L2CACHE_L2CERRA_EADDR_GET( _reg ) \
0468   ( ( ( _reg ) & L2CACHE_L2CERRA_EADDR_MASK ) >> \
0469     L2CACHE_L2CERRA_EADDR_SHIFT )
0470 #define L2CACHE_L2CERRA_EADDR_SET( _reg, _val ) \
0471   ( ( ( _reg ) & ~L2CACHE_L2CERRA_EADDR_MASK ) | \
0472     ( ( ( _val ) << L2CACHE_L2CERRA_EADDR_SHIFT ) & \
0473       L2CACHE_L2CERRA_EADDR_MASK ) )
0474 #define L2CACHE_L2CERRA_EADDR( _val ) \
0475   ( ( ( _val ) << L2CACHE_L2CERRA_EADDR_SHIFT ) & \
0476     L2CACHE_L2CERRA_EADDR_MASK )
0477
0478 /** @} */
0479
0480 /**
0481  * @defgroup RTEMSDeviceGRLIBL2CACHEL2CTCB L2C TAG-Check-Bits register (L2CTCB)
0482  *
0483  * @brief This group contains register bit definitions.
0484  *
0485  * @{
0486  */
0487
0488 #define L2CACHE_L2CTCB_TCB_SHIFT 0
0489 #define L2CACHE_L2CTCB_TCB_MASK 0x7fU
0490 #define L2CACHE_L2CTCB_TCB_GET( _reg ) \
0491   ( ( ( _reg ) & L2CACHE_L2CTCB_TCB_MASK ) >> \
0492     L2CACHE_L2CTCB_TCB_SHIFT )
0493 #define L2CACHE_L2CTCB_TCB_SET( _reg, _val ) \
0494   ( ( ( _reg ) & ~L2CACHE_L2CTCB_TCB_MASK ) | \
0495     ( ( ( _val ) << L2CACHE_L2CTCB_TCB_SHIFT ) & \
0496       L2CACHE_L2CTCB_TCB_MASK ) )
0497 #define L2CACHE_L2CTCB_TCB( _val ) \
0498   ( ( ( _val ) << L2CACHE_L2CTCB_TCB_SHIFT ) & \
0499     L2CACHE_L2CTCB_TCB_MASK )
0500
0501 /** @} */
0502
0503 /**
0504  * @defgroup RTEMSDeviceGRLIBL2CACHEL2CCB L2C Data-Check-Bits register (L2CCB)
0505  *
0506  * @brief This group contains register bit definitions.
0507  *
0508  * @{
0509  */
0510
0511 #define L2CACHE_L2CCB_CB_SHIFT 0
0512 #define L2CACHE_L2CCB_CB_MASK 0xfffffffU
0513 #define L2CACHE_L2CCB_CB_GET( _reg ) \
0514   ( ( ( _reg ) & L2CACHE_L2CCB_CB_MASK ) >> \
0515     L2CACHE_L2CCB_CB_SHIFT )
0516 #define L2CACHE_L2CCB_CB_SET( _reg, _val ) \
0517   ( ( ( _reg ) & ~L2CACHE_L2CCB_CB_MASK ) | \
0518     ( ( ( _val ) << L2CACHE_L2CCB_CB_SHIFT ) & \
0519       L2CACHE_L2CCB_CB_MASK ) )
0520 #define L2CACHE_L2CCB_CB( _val ) \
0521   ( ( ( _val ) << L2CACHE_L2CCB_CB_SHIFT ) & \
0522     L2CACHE_L2CCB_CB_MASK )
0523
0524 /** @} */
0525
0526 /**
0527  * @defgroup RTEMSDeviceGRLIBL2CACHEL2CSCRUB \
0528  *   L2C Scrub control/status register (L2CSCRUB)
0529  *
0530  * @brief This group contains register bit definitions.
0531  *
0532  * @{
0533  */
0534
0535 #define L2CACHE_L2CSCRUB_INDEX_SHIFT 16
0536 #define L2CACHE_L2CSCRUB_INDEX_MASK 0xffff0000U
0537 #define L2CACHE_L2CSCRUB_INDEX_GET( _reg ) \
0538   ( ( ( _reg ) & L2CACHE_L2CSCRUB_INDEX_MASK ) >> \
0539     L2CACHE_L2CSCRUB_INDEX_SHIFT )
0540 #define L2CACHE_L2CSCRUB_INDEX_SET( _reg, _val ) \
0541   ( ( ( _reg ) & ~L2CACHE_L2CSCRUB_INDEX_MASK ) | \
0542     ( ( ( _val ) << L2CACHE_L2CSCRUB_INDEX_SHIFT ) & \
0543       L2CACHE_L2CSCRUB_INDEX_MASK ) )
0544 #define L2CACHE_L2CSCRUB_INDEX( _val ) \
0545   ( ( ( _val ) << L2CACHE_L2CSCRUB_INDEX_SHIFT ) & \
0546     L2CACHE_L2CSCRUB_INDEX_MASK )
0547
0548 #define L2CACHE_L2CSCRUB_WAY_SHIFT 2
0549 #define L2CACHE_L2CSCRUB_WAY_MASK 0xcU
0550 #define L2CACHE_L2CSCRUB_WAY_GET( _reg ) \
0551   ( ( ( _reg ) & L2CACHE_L2CSCRUB_WAY_MASK ) >> \
0552     L2CACHE_L2CSCRUB_WAY_SHIFT )
0553 #define L2CACHE_L2CSCRUB_WAY_SET( _reg, _val ) \
0554   ( ( ( _reg ) & ~L2CACHE_L2CSCRUB_WAY_MASK ) | \
0555     ( ( ( _val ) << L2CACHE_L2CSCRUB_WAY_SHIFT ) & \
0556       L2CACHE_L2CSCRUB_WAY_MASK ) )
0557 #define L2CACHE_L2CSCRUB_WAY( _val ) \
0558   ( ( ( _val ) << L2CACHE_L2CSCRUB_WAY_SHIFT ) & \
0559     L2CACHE_L2CSCRUB_WAY_MASK )
0560
0561 #define L2CACHE_L2CSCRUB_PEN 0x2U
0562
0563 #define L2CACHE_L2CSCRUB_EN 0x1U
0564
0565 /** @} */
0566
0567 /**
0568  * @defgroup RTEMSDeviceGRLIBL2CACHEL2CSDEL L2C Scrub delay register (L2CSDEL)
0569  *
0570  * @brief This group contains register bit definitions.
0571  *
0572  * @{
0573  */
0574
0575 #define L2CACHE_L2CSDEL_DEL_SHIFT 0
0576 #define L2CACHE_L2CSDEL_DEL_MASK 0xffffU
0577 #define L2CACHE_L2CSDEL_DEL_GET( _reg ) \
0578   ( ( ( _reg ) & L2CACHE_L2CSDEL_DEL_MASK ) >> \
0579     L2CACHE_L2CSDEL_DEL_SHIFT )
0580 #define L2CACHE_L2CSDEL_DEL_SET( _reg, _val ) \
0581   ( ( ( _reg ) & ~L2CACHE_L2CSDEL_DEL_MASK ) | \
0582     ( ( ( _val ) << L2CACHE_L2CSDEL_DEL_SHIFT ) & \
0583       L2CACHE_L2CSDEL_DEL_MASK ) )
0584 #define L2CACHE_L2CSDEL_DEL( _val ) \
0585   ( ( ( _val ) << L2CACHE_L2CSDEL_DEL_SHIFT ) & \
0586     L2CACHE_L2CSDEL_DEL_MASK )
0587
0588 /** @} */
0589
0590 /**
0591  * @defgroup RTEMSDeviceGRLIBL2CACHEL2CEINJ \
0592  *   L2C Error injection register (L2CEINJ)
0593  *
0594  * @brief This group contains register bit definitions.
0595  *
0596  * @{
0597  */
0598
0599 #define L2CACHE_L2CEINJ_ADDR_SHIFT 2
0600 #define L2CACHE_L2CEINJ_ADDR_MASK 0xfffffffcU
0601 #define L2CACHE_L2CEINJ_ADDR_GET( _reg ) \
0602   ( ( ( _reg ) & L2CACHE_L2CEINJ_ADDR_MASK ) >> \
0603     L2CACHE_L2CEINJ_ADDR_SHIFT )
0604 #define L2CACHE_L2CEINJ_ADDR_SET( _reg, _val ) \
0605   ( ( ( _reg ) & ~L2CACHE_L2CEINJ_ADDR_MASK ) | \
0606     ( ( ( _val ) << L2CACHE_L2CEINJ_ADDR_SHIFT ) & \
0607       L2CACHE_L2CEINJ_ADDR_MASK ) )
0608 #define L2CACHE_L2CEINJ_ADDR( _val ) \
0609   ( ( ( _val ) << L2CACHE_L2CEINJ_ADDR_SHIFT ) & \
0610     L2CACHE_L2CEINJ_ADDR_MASK )
0611
0612 #define L2CACHE_L2CEINJ_INJ 0x1U
0613
0614 /** @} */
0615
0616 /**
0617  * @defgroup RTEMSDeviceGRLIBL2CACHEL2CACCC \
0618  *   L2C Access control register (L2CACCC)
0619  *
0620  * @brief This group contains register bit definitions.
0621  *
0622  * @{
0623  */
0624
0625 #define L2CACHE_L2CACCC_DSC 0x4000U
0626
0627 #define L2CACHE_L2CACCC_SH 0x2000U
0628
0629 #define L2CACHE_L2CACCC_SPLITQ 0x400U
0630
0631 #define L2CACHE_L2CACCC_NHM 0x200U
0632
0633 #define L2CACHE_L2CACCC_BERR 0x100U
0634
0635 #define L2CACHE_L2CACCC_OAPM 0x80U
0636
0637 #define L2CACHE_L2CACCC_FLINE 0x40U
0638
0639 #define L2CACHE_L2CACCC_DBPF 0x20U
0640
0641 #define L2CACHE_L2CACCC_128WF 0x10U
0642
0643 #define L2CACHE_L2CACCC_DBPWS 0x4U
0644
0645 #define L2CACHE_L2CACCC_SPLIT 0x2U
0646
0647 /** @} */
0648
0649 /**
0650  * @defgroup RTEMSDeviceGRLIBL2CACHEL2CEINJCFG \
0651  *   L2C injection configuration register (L2CEINJCFG)
0652  *
0653  * @brief This group contains register bit definitions.
0654  *
0655  * @{
0656  */
0657
0658 #define L2CACHE_L2CEINJCFG_EDI 0x400U
0659
0660 #define L2CACHE_L2CEINJCFG_TER 0x200U
0661
0662 #define L2CACHE_L2CEINJCFG_IMD 0x100U
0663
0664 /** @} */
0665
0666 /**
0667  * @defgroup RTEMSDeviceGRLIBL2CACHEL2CMTRR \
0668  *   L2C Memory type range register (L2CMTRR)
0669  *
0670  * @brief This group contains register bit definitions.
0671  *
0672  * @{
0673  */
0674
0675 #define L2CACHE_L2CMTRR_ADDR_SHIFT 18
0676 #define L2CACHE_L2CMTRR_ADDR_MASK 0xfffc0000U
0677 #define L2CACHE_L2CMTRR_ADDR_GET( _reg ) \
0678   ( ( ( _reg ) & L2CACHE_L2CMTRR_ADDR_MASK ) >> \
0679     L2CACHE_L2CMTRR_ADDR_SHIFT )
0680 #define L2CACHE_L2CMTRR_ADDR_SET( _reg, _val ) \
0681   ( ( ( _reg ) & ~L2CACHE_L2CMTRR_ADDR_MASK ) | \
0682     ( ( ( _val ) << L2CACHE_L2CMTRR_ADDR_SHIFT ) & \
0683       L2CACHE_L2CMTRR_ADDR_MASK ) )
0684 #define L2CACHE_L2CMTRR_ADDR( _val ) \
0685   ( ( ( _val ) << L2CACHE_L2CMTRR_ADDR_SHIFT ) & \
0686     L2CACHE_L2CMTRR_ADDR_MASK )
0687
0688 #define L2CACHE_L2CMTRR_ACC_SHIFT 16
0689 #define L2CACHE_L2CMTRR_ACC_MASK 0x30000U
0690 #define L2CACHE_L2CMTRR_ACC_GET( _reg ) \
0691   ( ( ( _reg ) & L2CACHE_L2CMTRR_ACC_MASK ) >> \
0692     L2CACHE_L2CMTRR_ACC_SHIFT )
0693 #define L2CACHE_L2CMTRR_ACC_SET( _reg, _val ) \
0694   ( ( ( _reg ) & ~L2CACHE_L2CMTRR_ACC_MASK ) | \
0695     ( ( ( _val ) << L2CACHE_L2CMTRR_ACC_SHIFT ) & \
0696       L2CACHE_L2CMTRR_ACC_MASK ) )
0697 #define L2CACHE_L2CMTRR_ACC( _val ) \
0698   ( ( ( _val ) << L2CACHE_L2CMTRR_ACC_SHIFT ) & \
0699     L2CACHE_L2CMTRR_ACC_MASK )
0700
0701 #define L2CACHE_L2CMTRR_MASK_SHIFT 2
0702 #define L2CACHE_L2CMTRR_MASK_MASK 0xfffcU
0703 #define L2CACHE_L2CMTRR_MASK_GET( _reg ) \
0704   ( ( ( _reg ) & L2CACHE_L2CMTRR_MASK_MASK ) >> \
0705     L2CACHE_L2CMTRR_MASK_SHIFT )
0706 #define L2CACHE_L2CMTRR_MASK_SET( _reg, _val ) \
0707   ( ( ( _reg ) & ~L2CACHE_L2CMTRR_MASK_MASK ) | \
0708     ( ( ( _val ) << L2CACHE_L2CMTRR_MASK_SHIFT ) & \
0709       L2CACHE_L2CMTRR_MASK_MASK ) )
0710 #define L2CACHE_L2CMTRR_MASK( _val ) \
0711   ( ( ( _val ) << L2CACHE_L2CMTRR_MASK_SHIFT ) & \
0712     L2CACHE_L2CMTRR_MASK_MASK )
0713
0714 #define L2CACHE_L2CMTRR_WP 0x2U
0715
0716 #define L2CACHE_L2CMTRR_AC 0x1U
0717
0718 /** @} */
0719
0720 /**
0721  * @brief This structure defines the L2CACHE register block memory map.
0722  */
0723 typedef struct l2cache {
0724   /**
0725    * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CC.
0726    */
0727   uint32_t l2cc;
0728
0729   /**
0730    * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CS.
0731    */
0732   uint32_t l2cs;
0733
0734   /**
0735    * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CFMA.
0736    */
0737   uint32_t l2cfma;
0738
0739   /**
0740    * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CFSI.
0741    */
0742   uint32_t l2cfsi;
0743
0744   uint32_t reserved_10_20[ 4 ];
0745
0746   /**
0747    * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CERR.
0748    */
0749   uint32_t l2cerr;
0750
0751   /**
0752    * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CERRA.
0753    */
0754   uint32_t l2cerra;
0755
0756   /**
0757    * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CTCB.
0758    */
0759   uint32_t l2ctcb;
0760
0761   /**
0762    * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CCB.
0763    */
0764   uint32_t l2ccb;
0765
0766   /**
0767    * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CSCRUB.
0768    */
0769   uint32_t l2cscrub;
0770
0771   /**
0772    * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CSDEL.
0773    */
0774   uint32_t l2csdel;
0775
0776   /**
0777    * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CEINJ.
0778    */
0779   uint32_t l2ceinj;
0780
0781   /**
0782    * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CACCC.
0783    */
0784   uint32_t l2caccc;
0785
0786   uint32_t reserved_40_4c[ 3 ];
0787
0788   /**
0789    * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CEINJCFG.
0790    */
0791   uint32_t l2ceinjcfg;
0792
0793   uint32_t reserved_50_80[ 12 ];
0794
0795   /**
0796    * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CMTRR.
0797    */
0798   uint32_t l2cmtrr;
0799 } l2cache;
0800
0801 /** @} */
0802
0803 #ifdef __cplusplus
0804 }
0805 #endif
0806
0807 #endif /* _GRLIB_L2CACHE_REGS_H */