include/grlib/l2c.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  *  GRLIB L2CACHE Driver
0005  *
0006  *  COPYRIGHT (c) 2017
0007  *  Cobham Gaisler AB
0008  *
0009  * Redistribution and use in source and binary forms, with or without
0010  * modification, are permitted provided that the following conditions
0011  * are met:
0012  * 1. Redistributions of source code must retain the above copyright
0013  *    notice, this list of conditions and the following disclaimer.
0014  * 2. Redistributions in binary form must reproduce the above copyright
0015  *    notice, this list of conditions and the following disclaimer in the
0016  *    documentation and/or other materials provided with the distribution.
0017  *
0018  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0019  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0020  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0021  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0022  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0023  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0024  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0025  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0026  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0027  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0028  * POSSIBILITY OF SUCH DAMAGE.
0029  *
0030  *  OVERVIEW
0031  *  ========
0032  *  This driver controls the L2CACHE device located
0033  *  at an on-chip AMBA.
0034  */
0035
0036 #ifndef __L2CACHE_H__
0037 #define __L2CACHE_H__
0038
0039 #include <stdint.h>
0040 #include <stdio.h>
0041
0042 #ifdef __cplusplus
0043 extern "C" {
0044 #endif
0045
0046 extern void l2cache_register_drv(void);
0047
0048 #define L2CACHE_ERR_OK 0
0049 #define L2CACHE_ERR_NOINIT -1
0050 #define L2CACHE_ERR_EINVAL -2
0051 #define L2CACHE_ERR_TOOMANY -3
0052 #define L2CACHE_ERR_ERROR -4
0053
0054 /* L2C Flush options */
0055 #define L2CACHE_OPTIONS_FLUSH_WAIT (0x1 << 2)
0056 #define L2CACHE_OPTIONS_FLUSH_INVALIDATE (0x3 << 0)
0057 #define L2CACHE_OPTIONS_FLUSH_WRITEBACK (0x2 << 0)
0058 #define L2CACHE_OPTIONS_FLUSH_INV_WBACK (0x1 << 0)
0059 #define L2CACHE_OPTIONS_FLUSH_NONE (0 << 0)
0060
0061 /* L2C Status */
0062 #define L2CACHE_STATUS_ENABLED 1
0063 #define L2CACHE_STATUS_SPLIT_ENABLED (0x1 << 1)
0064 #define L2CACHE_STATUS_EDAC_ENABLED (0x1 << 2)
0065 #define L2CACHE_STATUS_REPL (0x3 << L2CACHE_STATUS_REPL_BIT)
0066 #define L2CACHE_STATUS_REPL_BIT 3
0067 #define L2CACHE_STATUS_WRITETHROUGH (0x1 << 5)
0068 #define L2CACHE_STATUS_LOCK (0xf << L2CACHE_STATUS_LOCK_BIT)
0069 #define L2CACHE_STATUS_LOCK_BIT 6
0070 #define L2CACHE_STATUS_SCRUB_ENABLED (0x1 << 10)
0071 #define L2CACHE_STATUS_INT (0xf << L2CACHE_STATUS_INT_BIT)
0072 #define L2CACHE_STATUS_INT_BIT 11
0073 #define L2CACHE_STATUS_INT_BCKEND (0x1 << 11)
0074 #define L2CACHE_STATUS_INT_WPHIT (0x1 << 12)
0075 #define L2CACHE_STATUS_INT_UEE (0x1 << 13)
0076 #define L2CACHE_STATUS_INT_CEE (0x1 << 14)
0077 #define L2CACHE_STATUS_SCRUB_DELAY (0xffff << L2CACHE_STATUS_SCRUB_DELAY_BIT)
0078 #define L2CACHE_STATUS_SCRUB_DELAY_BIT 15
0079 #define L2CACHE_STATUS_SIGN_BIT 31
0080
0081 /* status helper macros */
0082 #define L2CACHE_ENABLED(status) (status & L2CACHE_STATUS_ENABLED)
0083 #define L2CACHE_DISABLED(status) (!(status & L2CACHE_STATUS_ENABLED))
0084 #define L2CACHE_SPLIT_ENABLED(status) (status & L2CACHE_STATUS_SPLIT_ENABLED)
0085 #define L2CACHE_SPLIT_DISABLED(status) \
0086     (!(status & L2CACHE_STATUS_SPLIT_ENABLED))
0087 #define L2CACHE_EDAC_ENABLED(status) (status & L2CACHE_STATUS_EDAC_ENABLED)
0088 #define L2CACHE_EDAC_DISABLED(status) (!(status & L2CACHE_STATUS_EDAC_ENABLED))
0089 #define L2CACHE_REPL(status) \
0090     ((status & L2CACHE_STATUS_REPL) >> L2CACHE_STATUS_REPL_BIT)
0091 #define L2CACHE_WRITETHROUGH(status) (status & L2CACHE_STATUS_WRITETHROUGH)
0092 #define L2CACHE_WRITEBACK(status) (!(status & L2CACHE_STATUS_WRITETHROUGH))
0093 #define L2CACHE_LOCKED_WAYS(status) \
0094     ((status & L2CACHE_STATUS_LOCK) >> L2CACHE_STATUS_LOCK_BIT)
0095 #define L2CACHE_SCRUB_ENABLED(status) (status & L2CACHE_STATUS_SCRUB_ENABLED)
0096 #define L2CACHE_SCRUB_DISABLED(status) \
0097     (!(status & L2CACHE_STATUS_SCRUB_ENABLED))
0098 #define L2CACHE_SCRUB_DELAY(status) \
0099     ((status & L2CACHE_STATUS_SCRUB_DELAY) >> L2CACHE_STATUS_SCRUB_DELAY_BIT)
0100 #define L2CACHE_INT_ENABLED(status) (status & L2CACHE_STATUS_INT)
0101 #define L2CACHE_INT_DISABLED(status) (!(status & L2CACHE_STATUS_INT))
0102 extern int l2cache_status(void);
0103
0104 /* L2C Setup */
0105 extern int l2cache_enable(int flush);
0106 extern int l2cache_disable(int flush);
0107
0108 extern int l2cache_split_enable(void);
0109 extern int l2cache_split_disable(void);
0110
0111 extern int l2cache_edac_enable(int flush);
0112 extern int l2cache_edac_disable(int flush);
0113
0114 extern int l2cache_scrub_enable(int delay);
0115 extern int l2cache_scrub_disable(void);
0116 extern int l2cache_scrub_line(int way, int index);
0117
0118 extern int l2cache_writethrough(int flush);
0119 extern int l2cache_writeback(int flush);
0120
0121 #define L2CACHE_OPTIONS_REPL_INDEX_WAY_BIT (2)
0122 #define L2CACHE_OPTIONS_REPL_MASTERIDX_MOD (3 << 0)
0123 #define L2CACHE_OPTIONS_REPL_MASTERIDX_IDX (2 << 0)
0124 #define L2CACHE_OPTIONS_REPL_RANDOM (1 << 0)
0125 #define L2CACHE_OPTIONS_REPL_LRU (0 << 0)
0126 extern int l2cache_replacement(int options, int flush);
0127
0128 /* L2C Flush */
0129 extern int l2cache_flush(int flush);
0130 extern int l2cache_flush_address(uint32_t addr, int size, int flush);
0131 extern int l2cache_flush_line(int way, int index, int flush);
0132 extern int l2cache_flush_way(int way, int flush);
0133
0134 /* L2C Lock way */
0135 #define L2CACHE_OPTIONS_DIRTY (0x1 << 2)
0136 #define L2CACHE_OPTIONS_VALID (0x1 << 1)
0137 #define L2CACHE_OPTIONS_FETCH (0x1 << 0)
0138 #define L2CACHE_OPTIONS_DISABLE 2
0139 #define L2CACHE_OPTIONS_ENABLE 1
0140 #define L2CACHE_OPTIONS_NONE 0
0141 extern int l2cache_lock_way(uint32_t tag, int options, int flush, int enable);
0142 extern int l2cache_unlock(void);
0143
0144 /* L2C Fill a way */
0145 extern int l2cache_fill_way(int way, uint32_t tag, int options, int flush);
0146
0147 /* L2C MTRR */
0148 #define L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH (0x1 << 2)
0149 #define L2CACHE_OPTIONS_MTRR_ACCESS_UNCACHED (0x0 << 2)
0150 #define L2CACHE_OPTIONS_MTRR_WRITEPROT_ENABLE (0x1 << 1)
0151 #define L2CACHE_OPTIONS_MTRR_WRITEPROT_DISABLE (0x0 << 1)
0152 extern int l2cache_mtrr_enable(int id, uint32_t addr, uint32_t mask,
0153         int options, int flush);
0154 extern int l2cache_mtrr_disable(int id);
0155
0156 /* L2C Debug print */
0157 extern int l2cache_print(void);
0158
0159 /* L2C Interrupts */
0160 /* Function Interrupt-Code ISR callback prototype.
0161  * arg     - Custom arg provided by user
0162  * addr    - Cacheline addr that generated the error
0163  * status  - Error status register of the L2CACHE core
0164  */
0165 typedef void (*l2cache_isr_t)(void *arg, uint32_t addr, uint32_t status);
0166 #define L2CACHE_INTERRUPT_ALL (0xf << 0)
0167 #define L2CACHE_INTERRUPT_BACKENDERROR (0x1 << 3)
0168 #define L2CACHE_INTERRUPT_WPROTHIT (0x1 << 2)
0169 #define L2CACHE_INTERRUPT_UNCORRERROR (0x1 << 1)
0170 #define L2CACHE_INTERRUPT_CORRERROR (0x1 << 0)
0171 extern int l2cache_isr_register( l2cache_isr_t isr, void * arg, int options);
0172 extern int l2cache_isr_unregister(void);
0173 extern int l2cache_interrupt_mask(int options);
0174 extern int l2cache_interrupt_unmask(int options);
0175
0176 /* L2C error interface */
0177 #define L2CACHE_STATUS_MULTIPLEERRORS 2
0178 #define L2CACHE_STATUS_NEWERROR 1
0179 #define L2CACHE_STATUS_NOERROR 0
0180 extern int l2cache_error_status(uint32_t * addr, uint32_t * status);
0181
0182 /*#define TEST_L2CACHE*/
0183 #ifdef TEST_L2CACHE
0184 /* Used for internal testing */
0185 /*
0186  * L2CACHE Tag private data struture
0187  */
0188 struct l2cache_tag {
0189     uint32_t tag;
0190     int valid;
0191     int dirty;
0192     int lru;
0193 };
0194
0195 /*
0196  * L2CACHE Line private data struture
0197  */
0198 struct l2cache_dataline {
0199     uint32_t data[16];
0200     int words;
0201 };
0202 extern int l2cache_get_index( uint32_t addr);
0203 extern uint32_t l2cache_get_tag( uint32_t addr);
0204
0205 extern int l2cache_diag_tag( int way, int index, struct l2cache_tag * tag);
0206 extern int l2cache_diag_line( int way, int index,
0207         struct l2cache_dataline * dataline);
0208
0209 #define L2CACHE_HIT 1
0210 #define L2CACHE_MISS 0
0211 extern int l2cache_lookup(uint32_t addr, int * way);
0212
0213 extern int l2cache_error_inject_address( uint32_t addr, uint32_t mask);
0214 #endif /* TEST_L2CACHE */
0215
0216 #ifdef __cplusplus
0217 }
0218 #endif
0219
0220 #endif /* __L2CACHE_H__ */