include/grlib/irqamp-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRLIBIRQAMP
0007  *
0008  * @brief This header file defines the IRQAMP register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/irqamp-header */
0054
0055 #ifndef _GRLIB_IRQAMP_REGS_H
0056 #define _GRLIB_IRQAMP_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/irqamp-timestamp */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRLIBIRQAMPTimestamp IRQ(A)MP Timestamp
0068  *
0069  * @ingroup RTEMSDeviceGRLIBIRQAMP
0070  *
0071  * @brief This group contains the IRQ(A)MP Timestamp interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRLIBIRQAMPTimestampITCNT \
0078  *   Interrupt timestamp counter n register (ITCNT)
0079  *
0080  * @brief This group contains register bit definitions.
0081  *
0082  * @{
0083  */
0084
0085 #define IRQAMP_ITCNT_TCNT_SHIFT 0
0086 #define IRQAMP_ITCNT_TCNT_MASK 0xffffffffU
0087 #define IRQAMP_ITCNT_TCNT_GET( _reg ) \
0088   ( ( ( _reg ) & IRQAMP_ITCNT_TCNT_MASK ) >> \
0089     IRQAMP_ITCNT_TCNT_SHIFT )
0090 #define IRQAMP_ITCNT_TCNT_SET( _reg, _val ) \
0091   ( ( ( _reg ) & ~IRQAMP_ITCNT_TCNT_MASK ) | \
0092     ( ( ( _val ) << IRQAMP_ITCNT_TCNT_SHIFT ) & \
0093       IRQAMP_ITCNT_TCNT_MASK ) )
0094 #define IRQAMP_ITCNT_TCNT( _val ) \
0095   ( ( ( _val ) << IRQAMP_ITCNT_TCNT_SHIFT ) & \
0096     IRQAMP_ITCNT_TCNT_MASK )
0097
0098 /** @} */
0099
0100 /**
0101  * @defgroup RTEMSDeviceGRLIBIRQAMPTimestampITSTMPC \
0102  *   Interrupt timestamp n control register (ITSTMPC)
0103  *
0104  * @brief This group contains register bit definitions.
0105  *
0106  * @{
0107  */
0108
0109 #define IRQAMP_ITSTMPC_TSTAMP_SHIFT 27
0110 #define IRQAMP_ITSTMPC_TSTAMP_MASK 0xf8000000U
0111 #define IRQAMP_ITSTMPC_TSTAMP_GET( _reg ) \
0112   ( ( ( _reg ) & IRQAMP_ITSTMPC_TSTAMP_MASK ) >> \
0113     IRQAMP_ITSTMPC_TSTAMP_SHIFT )
0114 #define IRQAMP_ITSTMPC_TSTAMP_SET( _reg, _val ) \
0115   ( ( ( _reg ) & ~IRQAMP_ITSTMPC_TSTAMP_MASK ) | \
0116     ( ( ( _val ) << IRQAMP_ITSTMPC_TSTAMP_SHIFT ) & \
0117       IRQAMP_ITSTMPC_TSTAMP_MASK ) )
0118 #define IRQAMP_ITSTMPC_TSTAMP( _val ) \
0119   ( ( ( _val ) << IRQAMP_ITSTMPC_TSTAMP_SHIFT ) & \
0120     IRQAMP_ITSTMPC_TSTAMP_MASK )
0121
0122 #define IRQAMP_ITSTMPC_S1 0x4000000U
0123
0124 #define IRQAMP_ITSTMPC_S2 0x2000000U
0125
0126 #define IRQAMP_ITSTMPC_KS 0x20U
0127
0128 #define IRQAMP_ITSTMPC_TSISEL_SHIFT 0
0129 #define IRQAMP_ITSTMPC_TSISEL_MASK 0x1fU
0130 #define IRQAMP_ITSTMPC_TSISEL_GET( _reg ) \
0131   ( ( ( _reg ) & IRQAMP_ITSTMPC_TSISEL_MASK ) >> \
0132     IRQAMP_ITSTMPC_TSISEL_SHIFT )
0133 #define IRQAMP_ITSTMPC_TSISEL_SET( _reg, _val ) \
0134   ( ( ( _reg ) & ~IRQAMP_ITSTMPC_TSISEL_MASK ) | \
0135     ( ( ( _val ) << IRQAMP_ITSTMPC_TSISEL_SHIFT ) & \
0136       IRQAMP_ITSTMPC_TSISEL_MASK ) )
0137 #define IRQAMP_ITSTMPC_TSISEL( _val ) \
0138   ( ( ( _val ) << IRQAMP_ITSTMPC_TSISEL_SHIFT ) & \
0139     IRQAMP_ITSTMPC_TSISEL_MASK )
0140
0141 /** @} */
0142
0143 /**
0144  * @defgroup RTEMSDeviceGRLIBIRQAMPTimestampITSTMPAS \
0145  *   Interrupt Assertion Timestamp n register (ITSTMPAS)
0146  *
0147  * @brief This group contains register bit definitions.
0148  *
0149  * @{
0150  */
0151
0152 #define IRQAMP_ITSTMPAS_TASSERTION_SHIFT 0
0153 #define IRQAMP_ITSTMPAS_TASSERTION_MASK 0xffffffffU
0154 #define IRQAMP_ITSTMPAS_TASSERTION_GET( _reg ) \
0155   ( ( ( _reg ) & IRQAMP_ITSTMPAS_TASSERTION_MASK ) >> \
0156     IRQAMP_ITSTMPAS_TASSERTION_SHIFT )
0157 #define IRQAMP_ITSTMPAS_TASSERTION_SET( _reg, _val ) \
0158   ( ( ( _reg ) & ~IRQAMP_ITSTMPAS_TASSERTION_MASK ) | \
0159     ( ( ( _val ) << IRQAMP_ITSTMPAS_TASSERTION_SHIFT ) & \
0160       IRQAMP_ITSTMPAS_TASSERTION_MASK ) )
0161 #define IRQAMP_ITSTMPAS_TASSERTION( _val ) \
0162   ( ( ( _val ) << IRQAMP_ITSTMPAS_TASSERTION_SHIFT ) & \
0163     IRQAMP_ITSTMPAS_TASSERTION_MASK )
0164
0165 /** @} */
0166
0167 /**
0168  * @defgroup RTEMSDeviceGRLIBIRQAMPTimestampITSTMPAC \
0169  *   Interrupt Acknowledge Timestamp n register (ITSTMPAC)
0170  *
0171  * @brief This group contains register bit definitions.
0172  *
0173  * @{
0174  */
0175
0176 #define IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT 0
0177 #define IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK 0xffffffffU
0178 #define IRQAMP_ITSTMPAC_TACKNOWLEDGE_GET( _reg ) \
0179   ( ( ( _reg ) & IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) >> \
0180     IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT )
0181 #define IRQAMP_ITSTMPAC_TACKNOWLEDGE_SET( _reg, _val ) \
0182   ( ( ( _reg ) & ~IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) | \
0183     ( ( ( _val ) << IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT ) & \
0184       IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) )
0185 #define IRQAMP_ITSTMPAC_TACKNOWLEDGE( _val ) \
0186   ( ( ( _val ) << IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT ) & \
0187     IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK )
0188
0189 /** @} */
0190
0191 /**
0192  * @brief This structure defines the IRQ(A)MP Timestamp register block memory
0193  *   map.
0194  */
0195 typedef struct irqamp_timestamp {
0196   /**
0197    * @brief See @ref RTEMSDeviceGRLIBIRQAMPTimestampITCNT.
0198    */
0199   uint32_t itcnt;
0200
0201   /**
0202    * @brief See @ref RTEMSDeviceGRLIBIRQAMPTimestampITSTMPC.
0203    */
0204   uint32_t itstmpc;
0205
0206   /**
0207    * @brief See @ref RTEMSDeviceGRLIBIRQAMPTimestampITSTMPAS.
0208    */
0209   uint32_t itstmpas;
0210
0211   /**
0212    * @brief See @ref RTEMSDeviceGRLIBIRQAMPTimestampITSTMPAC.
0213    */
0214   uint32_t itstmpac;
0215 } irqamp_timestamp;
0216
0217 /** @} */
0218
0219 /* Generated from spec:/dev/grlib/if/irqamp */
0220
0221 /**
0222  * @defgroup RTEMSDeviceGRLIBIRQAMP IRQ(A)MP
0223  *
0224  * @ingroup RTEMSDeviceGRLIB
0225  *
0226  * @brief This group contains the IRQ(A)MP interfaces.
0227  *
0228  * @{
0229  */
0230
0231 /**
0232  * @defgroup RTEMSDeviceGRLIBIRQAMPILEVEL Interrupt level register (ILEVEL)
0233  *
0234  * @brief This group contains register bit definitions.
0235  *
0236  * @{
0237  */
0238
0239 #define IRQAMP_ILEVEL_IL_15_1_SHIFT 1
0240 #define IRQAMP_ILEVEL_IL_15_1_MASK 0xfffeU
0241 #define IRQAMP_ILEVEL_IL_15_1_GET( _reg ) \
0242   ( ( ( _reg ) & IRQAMP_ILEVEL_IL_15_1_MASK ) >> \
0243     IRQAMP_ILEVEL_IL_15_1_SHIFT )
0244 #define IRQAMP_ILEVEL_IL_15_1_SET( _reg, _val ) \
0245   ( ( ( _reg ) & ~IRQAMP_ILEVEL_IL_15_1_MASK ) | \
0246     ( ( ( _val ) << IRQAMP_ILEVEL_IL_15_1_SHIFT ) & \
0247       IRQAMP_ILEVEL_IL_15_1_MASK ) )
0248 #define IRQAMP_ILEVEL_IL_15_1( _val ) \
0249   ( ( ( _val ) << IRQAMP_ILEVEL_IL_15_1_SHIFT ) & \
0250     IRQAMP_ILEVEL_IL_15_1_MASK )
0251
0252 /** @} */
0253
0254 /**
0255  * @defgroup RTEMSDeviceGRLIBIRQAMPIPEND Interrupt pending register (IPEND)
0256  *
0257  * @brief This group contains register bit definitions.
0258  *
0259  * @{
0260  */
0261
0262 #define IRQAMP_IPEND_EIP_31_16_SHIFT 16
0263 #define IRQAMP_IPEND_EIP_31_16_MASK 0xffff0000U
0264 #define IRQAMP_IPEND_EIP_31_16_GET( _reg ) \
0265   ( ( ( _reg ) & IRQAMP_IPEND_EIP_31_16_MASK ) >> \
0266     IRQAMP_IPEND_EIP_31_16_SHIFT )
0267 #define IRQAMP_IPEND_EIP_31_16_SET( _reg, _val ) \
0268   ( ( ( _reg ) & ~IRQAMP_IPEND_EIP_31_16_MASK ) | \
0269     ( ( ( _val ) << IRQAMP_IPEND_EIP_31_16_SHIFT ) & \
0270       IRQAMP_IPEND_EIP_31_16_MASK ) )
0271 #define IRQAMP_IPEND_EIP_31_16( _val ) \
0272   ( ( ( _val ) << IRQAMP_IPEND_EIP_31_16_SHIFT ) & \
0273     IRQAMP_IPEND_EIP_31_16_MASK )
0274
0275 #define IRQAMP_IPEND_IP_15_1_SHIFT 1
0276 #define IRQAMP_IPEND_IP_15_1_MASK 0xfffeU
0277 #define IRQAMP_IPEND_IP_15_1_GET( _reg ) \
0278   ( ( ( _reg ) & IRQAMP_IPEND_IP_15_1_MASK ) >> \
0279     IRQAMP_IPEND_IP_15_1_SHIFT )
0280 #define IRQAMP_IPEND_IP_15_1_SET( _reg, _val ) \
0281   ( ( ( _reg ) & ~IRQAMP_IPEND_IP_15_1_MASK ) | \
0282     ( ( ( _val ) << IRQAMP_IPEND_IP_15_1_SHIFT ) & \
0283       IRQAMP_IPEND_IP_15_1_MASK ) )
0284 #define IRQAMP_IPEND_IP_15_1( _val ) \
0285   ( ( ( _val ) << IRQAMP_IPEND_IP_15_1_SHIFT ) & \
0286     IRQAMP_IPEND_IP_15_1_MASK )
0287
0288 /** @} */
0289
0290 /**
0291  * @defgroup RTEMSDeviceGRLIBIRQAMPIFORCE0 \
0292  *   Interrupt force register for processor 0 (IFORCE0)
0293  *
0294  * @brief This group contains register bit definitions.
0295  *
0296  * @{
0297  */
0298
0299 #define IRQAMP_IFORCE0_IF_15_1_SHIFT 1
0300 #define IRQAMP_IFORCE0_IF_15_1_MASK 0xfffeU
0301 #define IRQAMP_IFORCE0_IF_15_1_GET( _reg ) \
0302   ( ( ( _reg ) & IRQAMP_IFORCE0_IF_15_1_MASK ) >> \
0303     IRQAMP_IFORCE0_IF_15_1_SHIFT )
0304 #define IRQAMP_IFORCE0_IF_15_1_SET( _reg, _val ) \
0305   ( ( ( _reg ) & ~IRQAMP_IFORCE0_IF_15_1_MASK ) | \
0306     ( ( ( _val ) << IRQAMP_IFORCE0_IF_15_1_SHIFT ) & \
0307       IRQAMP_IFORCE0_IF_15_1_MASK ) )
0308 #define IRQAMP_IFORCE0_IF_15_1( _val ) \
0309   ( ( ( _val ) << IRQAMP_IFORCE0_IF_15_1_SHIFT ) & \
0310     IRQAMP_IFORCE0_IF_15_1_MASK )
0311
0312 /** @} */
0313
0314 /**
0315  * @defgroup RTEMSDeviceGRLIBIRQAMPICLEAR Interrupt clear register (ICLEAR)
0316  *
0317  * @brief This group contains register bit definitions.
0318  *
0319  * @{
0320  */
0321
0322 #define IRQAMP_ICLEAR_EIC_31_16_SHIFT 16
0323 #define IRQAMP_ICLEAR_EIC_31_16_MASK 0xffff0000U
0324 #define IRQAMP_ICLEAR_EIC_31_16_GET( _reg ) \
0325   ( ( ( _reg ) & IRQAMP_ICLEAR_EIC_31_16_MASK ) >> \
0326     IRQAMP_ICLEAR_EIC_31_16_SHIFT )
0327 #define IRQAMP_ICLEAR_EIC_31_16_SET( _reg, _val ) \
0328   ( ( ( _reg ) & ~IRQAMP_ICLEAR_EIC_31_16_MASK ) | \
0329     ( ( ( _val ) << IRQAMP_ICLEAR_EIC_31_16_SHIFT ) & \
0330       IRQAMP_ICLEAR_EIC_31_16_MASK ) )
0331 #define IRQAMP_ICLEAR_EIC_31_16( _val ) \
0332   ( ( ( _val ) << IRQAMP_ICLEAR_EIC_31_16_SHIFT ) & \
0333     IRQAMP_ICLEAR_EIC_31_16_MASK )
0334
0335 #define IRQAMP_ICLEAR_IC_15_1_SHIFT 1
0336 #define IRQAMP_ICLEAR_IC_15_1_MASK 0xfffeU
0337 #define IRQAMP_ICLEAR_IC_15_1_GET( _reg ) \
0338   ( ( ( _reg ) & IRQAMP_ICLEAR_IC_15_1_MASK ) >> \
0339     IRQAMP_ICLEAR_IC_15_1_SHIFT )
0340 #define IRQAMP_ICLEAR_IC_15_1_SET( _reg, _val ) \
0341   ( ( ( _reg ) & ~IRQAMP_ICLEAR_IC_15_1_MASK ) | \
0342     ( ( ( _val ) << IRQAMP_ICLEAR_IC_15_1_SHIFT ) & \
0343       IRQAMP_ICLEAR_IC_15_1_MASK ) )
0344 #define IRQAMP_ICLEAR_IC_15_1( _val ) \
0345   ( ( ( _val ) << IRQAMP_ICLEAR_IC_15_1_SHIFT ) & \
0346     IRQAMP_ICLEAR_IC_15_1_MASK )
0347
0348 /** @} */
0349
0350 /**
0351  * @defgroup RTEMSDeviceGRLIBIRQAMPMPSTAT \
0352  *   Multiprocessor status register (MPSTAT)
0353  *
0354  * @brief This group contains register bit definitions.
0355  *
0356  * @{
0357  */
0358
0359 #define IRQAMP_MPSTAT_NCPU_SHIFT 28
0360 #define IRQAMP_MPSTAT_NCPU_MASK 0xf0000000U
0361 #define IRQAMP_MPSTAT_NCPU_GET( _reg ) \
0362   ( ( ( _reg ) & IRQAMP_MPSTAT_NCPU_MASK ) >> \
0363     IRQAMP_MPSTAT_NCPU_SHIFT )
0364 #define IRQAMP_MPSTAT_NCPU_SET( _reg, _val ) \
0365   ( ( ( _reg ) & ~IRQAMP_MPSTAT_NCPU_MASK ) | \
0366     ( ( ( _val ) << IRQAMP_MPSTAT_NCPU_SHIFT ) & \
0367       IRQAMP_MPSTAT_NCPU_MASK ) )
0368 #define IRQAMP_MPSTAT_NCPU( _val ) \
0369   ( ( ( _val ) << IRQAMP_MPSTAT_NCPU_SHIFT ) & \
0370     IRQAMP_MPSTAT_NCPU_MASK )
0371
0372 #define IRQAMP_MPSTAT_BA 0x8000000U
0373
0374 #define IRQAMP_MPSTAT_ER 0x4000000U
0375
0376 #define IRQAMP_MPSTAT_EIRQ_SHIFT 16
0377 #define IRQAMP_MPSTAT_EIRQ_MASK 0xf0000U
0378 #define IRQAMP_MPSTAT_EIRQ_GET( _reg ) \
0379   ( ( ( _reg ) & IRQAMP_MPSTAT_EIRQ_MASK ) >> \
0380     IRQAMP_MPSTAT_EIRQ_SHIFT )
0381 #define IRQAMP_MPSTAT_EIRQ_SET( _reg, _val ) \
0382   ( ( ( _reg ) & ~IRQAMP_MPSTAT_EIRQ_MASK ) | \
0383     ( ( ( _val ) << IRQAMP_MPSTAT_EIRQ_SHIFT ) & \
0384       IRQAMP_MPSTAT_EIRQ_MASK ) )
0385 #define IRQAMP_MPSTAT_EIRQ( _val ) \
0386   ( ( ( _val ) << IRQAMP_MPSTAT_EIRQ_SHIFT ) & \
0387     IRQAMP_MPSTAT_EIRQ_MASK )
0388
0389 #define IRQAMP_MPSTAT_STATUS_SHIFT 0
0390 #define IRQAMP_MPSTAT_STATUS_MASK 0xfU
0391 #define IRQAMP_MPSTAT_STATUS_GET( _reg ) \
0392   ( ( ( _reg ) & IRQAMP_MPSTAT_STATUS_MASK ) >> \
0393     IRQAMP_MPSTAT_STATUS_SHIFT )
0394 #define IRQAMP_MPSTAT_STATUS_SET( _reg, _val ) \
0395   ( ( ( _reg ) & ~IRQAMP_MPSTAT_STATUS_MASK ) | \
0396     ( ( ( _val ) << IRQAMP_MPSTAT_STATUS_SHIFT ) & \
0397       IRQAMP_MPSTAT_STATUS_MASK ) )
0398 #define IRQAMP_MPSTAT_STATUS( _val ) \
0399   ( ( ( _val ) << IRQAMP_MPSTAT_STATUS_SHIFT ) & \
0400     IRQAMP_MPSTAT_STATUS_MASK )
0401
0402 /** @} */
0403
0404 /**
0405  * @defgroup RTEMSDeviceGRLIBIRQAMPBRDCST Broadcast register (BRDCST)
0406  *
0407  * @brief This group contains register bit definitions.
0408  *
0409  * @{
0410  */
0411
0412 #define IRQAMP_BRDCST_BM15_1_SHIFT 1
0413 #define IRQAMP_BRDCST_BM15_1_MASK 0xfffeU
0414 #define IRQAMP_BRDCST_BM15_1_GET( _reg ) \
0415   ( ( ( _reg ) & IRQAMP_BRDCST_BM15_1_MASK ) >> \
0416     IRQAMP_BRDCST_BM15_1_SHIFT )
0417 #define IRQAMP_BRDCST_BM15_1_SET( _reg, _val ) \
0418   ( ( ( _reg ) & ~IRQAMP_BRDCST_BM15_1_MASK ) | \
0419     ( ( ( _val ) << IRQAMP_BRDCST_BM15_1_SHIFT ) & \
0420       IRQAMP_BRDCST_BM15_1_MASK ) )
0421 #define IRQAMP_BRDCST_BM15_1( _val ) \
0422   ( ( ( _val ) << IRQAMP_BRDCST_BM15_1_SHIFT ) & \
0423     IRQAMP_BRDCST_BM15_1_MASK )
0424
0425 /** @} */
0426
0427 /**
0428  * @defgroup RTEMSDeviceGRLIBIRQAMPERRSTAT Error Mode Status Register (ERRSTAT)
0429  *
0430  * @brief This group contains register bit definitions.
0431  *
0432  * @{
0433  */
0434
0435 #define IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT 0
0436 #define IRQAMP_ERRSTAT_ERRMODE_3_0_MASK 0xfU
0437 #define IRQAMP_ERRSTAT_ERRMODE_3_0_GET( _reg ) \
0438   ( ( ( _reg ) & IRQAMP_ERRSTAT_ERRMODE_3_0_MASK ) >> \
0439     IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT )
0440 #define IRQAMP_ERRSTAT_ERRMODE_3_0_SET( _reg, _val ) \
0441   ( ( ( _reg ) & ~IRQAMP_ERRSTAT_ERRMODE_3_0_MASK ) | \
0442     ( ( ( _val ) << IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT ) & \
0443       IRQAMP_ERRSTAT_ERRMODE_3_0_MASK ) )
0444 #define IRQAMP_ERRSTAT_ERRMODE_3_0( _val ) \
0445   ( ( ( _val ) << IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT ) & \
0446     IRQAMP_ERRSTAT_ERRMODE_3_0_MASK )
0447
0448 /** @} */
0449
0450 /**
0451  * @defgroup RTEMSDeviceGRLIBIRQAMPWDOGCTRL \
0452  *   Watchdog control register (WDOGCTRL)
0453  *
0454  * @brief This group contains register bit definitions.
0455  *
0456  * @{
0457  */
0458
0459 #define IRQAMP_WDOGCTRL_NWDOG_SHIFT 27
0460 #define IRQAMP_WDOGCTRL_NWDOG_MASK 0xf8000000U
0461 #define IRQAMP_WDOGCTRL_NWDOG_GET( _reg ) \
0462   ( ( ( _reg ) & IRQAMP_WDOGCTRL_NWDOG_MASK ) >> \
0463     IRQAMP_WDOGCTRL_NWDOG_SHIFT )
0464 #define IRQAMP_WDOGCTRL_NWDOG_SET( _reg, _val ) \
0465   ( ( ( _reg ) & ~IRQAMP_WDOGCTRL_NWDOG_MASK ) | \
0466     ( ( ( _val ) << IRQAMP_WDOGCTRL_NWDOG_SHIFT ) & \
0467       IRQAMP_WDOGCTRL_NWDOG_MASK ) )
0468 #define IRQAMP_WDOGCTRL_NWDOG( _val ) \
0469   ( ( ( _val ) << IRQAMP_WDOGCTRL_NWDOG_SHIFT ) & \
0470     IRQAMP_WDOGCTRL_NWDOG_MASK )
0471
0472 #define IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT 16
0473 #define IRQAMP_WDOGCTRL_WDOGIRQ_MASK 0xf0000U
0474 #define IRQAMP_WDOGCTRL_WDOGIRQ_GET( _reg ) \
0475   ( ( ( _reg ) & IRQAMP_WDOGCTRL_WDOGIRQ_MASK ) >> \
0476     IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT )
0477 #define IRQAMP_WDOGCTRL_WDOGIRQ_SET( _reg, _val ) \
0478   ( ( ( _reg ) & ~IRQAMP_WDOGCTRL_WDOGIRQ_MASK ) | \
0479     ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT ) & \
0480       IRQAMP_WDOGCTRL_WDOGIRQ_MASK ) )
0481 #define IRQAMP_WDOGCTRL_WDOGIRQ( _val ) \
0482   ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT ) & \
0483     IRQAMP_WDOGCTRL_WDOGIRQ_MASK )
0484
0485 #define IRQAMP_WDOGCTRL_WDOGMSK_SHIFT 0
0486 #define IRQAMP_WDOGCTRL_WDOGMSK_MASK 0xfU
0487 #define IRQAMP_WDOGCTRL_WDOGMSK_GET( _reg ) \
0488   ( ( ( _reg ) & IRQAMP_WDOGCTRL_WDOGMSK_MASK ) >> \
0489     IRQAMP_WDOGCTRL_WDOGMSK_SHIFT )
0490 #define IRQAMP_WDOGCTRL_WDOGMSK_SET( _reg, _val ) \
0491   ( ( ( _reg ) & ~IRQAMP_WDOGCTRL_WDOGMSK_MASK ) | \
0492     ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGMSK_SHIFT ) & \
0493       IRQAMP_WDOGCTRL_WDOGMSK_MASK ) )
0494 #define IRQAMP_WDOGCTRL_WDOGMSK( _val ) \
0495   ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGMSK_SHIFT ) & \
0496     IRQAMP_WDOGCTRL_WDOGMSK_MASK )
0497
0498 /** @} */
0499
0500 /**
0501  * @defgroup RTEMSDeviceGRLIBIRQAMPASMPCTRL \
0502  *   Asymmetric multiprocessing control register (ASMPCTRL)
0503  *
0504  * @brief This group contains register bit definitions.
0505  *
0506  * @{
0507  */
0508
0509 #define IRQAMP_ASMPCTRL_NCTRL_SHIFT 28
0510 #define IRQAMP_ASMPCTRL_NCTRL_MASK 0xf0000000U
0511 #define IRQAMP_ASMPCTRL_NCTRL_GET( _reg ) \
0512   ( ( ( _reg ) & IRQAMP_ASMPCTRL_NCTRL_MASK ) >> \
0513     IRQAMP_ASMPCTRL_NCTRL_SHIFT )
0514 #define IRQAMP_ASMPCTRL_NCTRL_SET( _reg, _val ) \
0515   ( ( ( _reg ) & ~IRQAMP_ASMPCTRL_NCTRL_MASK ) | \
0516     ( ( ( _val ) << IRQAMP_ASMPCTRL_NCTRL_SHIFT ) & \
0517       IRQAMP_ASMPCTRL_NCTRL_MASK ) )
0518 #define IRQAMP_ASMPCTRL_NCTRL( _val ) \
0519   ( ( ( _val ) << IRQAMP_ASMPCTRL_NCTRL_SHIFT ) & \
0520     IRQAMP_ASMPCTRL_NCTRL_MASK )
0521
0522 #define IRQAMP_ASMPCTRL_ICF 0x2U
0523
0524 #define IRQAMP_ASMPCTRL_L 0x1U
0525
0526 /** @} */
0527
0528 /**
0529  * @defgroup RTEMSDeviceGRLIBIRQAMPICSELR \
0530  *   Interrupt controller select register (ICSELR)
0531  *
0532  * @brief This group contains register bit definitions.
0533  *
0534  * @{
0535  */
0536
0537 #define IRQAMP_ICSELR_ICSEL0_SHIFT 28
0538 #define IRQAMP_ICSELR_ICSEL0_MASK 0xf0000000U
0539 #define IRQAMP_ICSELR_ICSEL0_GET( _reg ) \
0540   ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL0_MASK ) >> \
0541     IRQAMP_ICSELR_ICSEL0_SHIFT )
0542 #define IRQAMP_ICSELR_ICSEL0_SET( _reg, _val ) \
0543   ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL0_MASK ) | \
0544     ( ( ( _val ) << IRQAMP_ICSELR_ICSEL0_SHIFT ) & \
0545       IRQAMP_ICSELR_ICSEL0_MASK ) )
0546 #define IRQAMP_ICSELR_ICSEL0( _val ) \
0547   ( ( ( _val ) << IRQAMP_ICSELR_ICSEL0_SHIFT ) & \
0548     IRQAMP_ICSELR_ICSEL0_MASK )
0549
0550 #define IRQAMP_ICSELR_ICSEL1_SHIFT 24
0551 #define IRQAMP_ICSELR_ICSEL1_MASK 0xf000000U
0552 #define IRQAMP_ICSELR_ICSEL1_GET( _reg ) \
0553   ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL1_MASK ) >> \
0554     IRQAMP_ICSELR_ICSEL1_SHIFT )
0555 #define IRQAMP_ICSELR_ICSEL1_SET( _reg, _val ) \
0556   ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL1_MASK ) | \
0557     ( ( ( _val ) << IRQAMP_ICSELR_ICSEL1_SHIFT ) & \
0558       IRQAMP_ICSELR_ICSEL1_MASK ) )
0559 #define IRQAMP_ICSELR_ICSEL1( _val ) \
0560   ( ( ( _val ) << IRQAMP_ICSELR_ICSEL1_SHIFT ) & \
0561     IRQAMP_ICSELR_ICSEL1_MASK )
0562
0563 #define IRQAMP_ICSELR_ICSEL2_SHIFT 20
0564 #define IRQAMP_ICSELR_ICSEL2_MASK 0xf00000U
0565 #define IRQAMP_ICSELR_ICSEL2_GET( _reg ) \
0566   ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL2_MASK ) >> \
0567     IRQAMP_ICSELR_ICSEL2_SHIFT )
0568 #define IRQAMP_ICSELR_ICSEL2_SET( _reg, _val ) \
0569   ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL2_MASK ) | \
0570     ( ( ( _val ) << IRQAMP_ICSELR_ICSEL2_SHIFT ) & \
0571       IRQAMP_ICSELR_ICSEL2_MASK ) )
0572 #define IRQAMP_ICSELR_ICSEL2( _val ) \
0573   ( ( ( _val ) << IRQAMP_ICSELR_ICSEL2_SHIFT ) & \
0574     IRQAMP_ICSELR_ICSEL2_MASK )
0575
0576 #define IRQAMP_ICSELR_ICSEL3_SHIFT 16
0577 #define IRQAMP_ICSELR_ICSEL3_MASK 0xf0000U
0578 #define IRQAMP_ICSELR_ICSEL3_GET( _reg ) \
0579   ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL3_MASK ) >> \
0580     IRQAMP_ICSELR_ICSEL3_SHIFT )
0581 #define IRQAMP_ICSELR_ICSEL3_SET( _reg, _val ) \
0582   ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL3_MASK ) | \
0583     ( ( ( _val ) << IRQAMP_ICSELR_ICSEL3_SHIFT ) & \
0584       IRQAMP_ICSELR_ICSEL3_MASK ) )
0585 #define IRQAMP_ICSELR_ICSEL3( _val ) \
0586   ( ( ( _val ) << IRQAMP_ICSELR_ICSEL3_SHIFT ) & \
0587     IRQAMP_ICSELR_ICSEL3_MASK )
0588
0589 /** @} */
0590
0591 /**
0592  * @defgroup RTEMSDeviceGRLIBIRQAMPPIMASK \
0593  *   Processor n interrupt mask register (PIMASK)
0594  *
0595  * @brief This group contains register bit definitions.
0596  *
0597  * @{
0598  */
0599
0600 #define IRQAMP_PIMASK_EIM_31_16_SHIFT 16
0601 #define IRQAMP_PIMASK_EIM_31_16_MASK 0xffff0000U
0602 #define IRQAMP_PIMASK_EIM_31_16_GET( _reg ) \
0603   ( ( ( _reg ) & IRQAMP_PIMASK_EIM_31_16_MASK ) >> \
0604     IRQAMP_PIMASK_EIM_31_16_SHIFT )
0605 #define IRQAMP_PIMASK_EIM_31_16_SET( _reg, _val ) \
0606   ( ( ( _reg ) & ~IRQAMP_PIMASK_EIM_31_16_MASK ) | \
0607     ( ( ( _val ) << IRQAMP_PIMASK_EIM_31_16_SHIFT ) & \
0608       IRQAMP_PIMASK_EIM_31_16_MASK ) )
0609 #define IRQAMP_PIMASK_EIM_31_16( _val ) \
0610   ( ( ( _val ) << IRQAMP_PIMASK_EIM_31_16_SHIFT ) & \
0611     IRQAMP_PIMASK_EIM_31_16_MASK )
0612
0613 #define IRQAMP_PIMASK_IM15_1_SHIFT 1
0614 #define IRQAMP_PIMASK_IM15_1_MASK 0xfffeU
0615 #define IRQAMP_PIMASK_IM15_1_GET( _reg ) \
0616   ( ( ( _reg ) & IRQAMP_PIMASK_IM15_1_MASK ) >> \
0617     IRQAMP_PIMASK_IM15_1_SHIFT )
0618 #define IRQAMP_PIMASK_IM15_1_SET( _reg, _val ) \
0619   ( ( ( _reg ) & ~IRQAMP_PIMASK_IM15_1_MASK ) | \
0620     ( ( ( _val ) << IRQAMP_PIMASK_IM15_1_SHIFT ) & \
0621       IRQAMP_PIMASK_IM15_1_MASK ) )
0622 #define IRQAMP_PIMASK_IM15_1( _val ) \
0623   ( ( ( _val ) << IRQAMP_PIMASK_IM15_1_SHIFT ) & \
0624     IRQAMP_PIMASK_IM15_1_MASK )
0625
0626 /** @} */
0627
0628 /**
0629  * @defgroup RTEMSDeviceGRLIBIRQAMPPIFORCE \
0630  *   Processor n interrupt force register (PIFORCE)
0631  *
0632  * @brief This group contains register bit definitions.
0633  *
0634  * @{
0635  */
0636
0637 #define IRQAMP_PIFORCE_FC_15_1_SHIFT 17
0638 #define IRQAMP_PIFORCE_FC_15_1_MASK 0xfffe0000U
0639 #define IRQAMP_PIFORCE_FC_15_1_GET( _reg ) \
0640   ( ( ( _reg ) & IRQAMP_PIFORCE_FC_15_1_MASK ) >> \
0641     IRQAMP_PIFORCE_FC_15_1_SHIFT )
0642 #define IRQAMP_PIFORCE_FC_15_1_SET( _reg, _val ) \
0643   ( ( ( _reg ) & ~IRQAMP_PIFORCE_FC_15_1_MASK ) | \
0644     ( ( ( _val ) << IRQAMP_PIFORCE_FC_15_1_SHIFT ) & \
0645       IRQAMP_PIFORCE_FC_15_1_MASK ) )
0646 #define IRQAMP_PIFORCE_FC_15_1( _val ) \
0647   ( ( ( _val ) << IRQAMP_PIFORCE_FC_15_1_SHIFT ) & \
0648     IRQAMP_PIFORCE_FC_15_1_MASK )
0649
0650 #define IRQAMP_PIFORCE_IF15_1_SHIFT 1
0651 #define IRQAMP_PIFORCE_IF15_1_MASK 0xfffeU
0652 #define IRQAMP_PIFORCE_IF15_1_GET( _reg ) \
0653   ( ( ( _reg ) & IRQAMP_PIFORCE_IF15_1_MASK ) >> \
0654     IRQAMP_PIFORCE_IF15_1_SHIFT )
0655 #define IRQAMP_PIFORCE_IF15_1_SET( _reg, _val ) \
0656   ( ( ( _reg ) & ~IRQAMP_PIFORCE_IF15_1_MASK ) | \
0657     ( ( ( _val ) << IRQAMP_PIFORCE_IF15_1_SHIFT ) & \
0658       IRQAMP_PIFORCE_IF15_1_MASK ) )
0659 #define IRQAMP_PIFORCE_IF15_1( _val ) \
0660   ( ( ( _val ) << IRQAMP_PIFORCE_IF15_1_SHIFT ) & \
0661     IRQAMP_PIFORCE_IF15_1_MASK )
0662
0663 /** @} */
0664
0665 /**
0666  * @defgroup RTEMSDeviceGRLIBIRQAMPPEXTACK \
0667  *   Processor n extended interrupt acknowledge register (PEXTACK)
0668  *
0669  * @brief This group contains register bit definitions.
0670  *
0671  * @{
0672  */
0673
0674 #define IRQAMP_PEXTACK_EID_4_0_SHIFT 0
0675 #define IRQAMP_PEXTACK_EID_4_0_MASK 0x1fU
0676 #define IRQAMP_PEXTACK_EID_4_0_GET( _reg ) \
0677   ( ( ( _reg ) & IRQAMP_PEXTACK_EID_4_0_MASK ) >> \
0678     IRQAMP_PEXTACK_EID_4_0_SHIFT )
0679 #define IRQAMP_PEXTACK_EID_4_0_SET( _reg, _val ) \
0680   ( ( ( _reg ) & ~IRQAMP_PEXTACK_EID_4_0_MASK ) | \
0681     ( ( ( _val ) << IRQAMP_PEXTACK_EID_4_0_SHIFT ) & \
0682       IRQAMP_PEXTACK_EID_4_0_MASK ) )
0683 #define IRQAMP_PEXTACK_EID_4_0( _val ) \
0684   ( ( ( _val ) << IRQAMP_PEXTACK_EID_4_0_SHIFT ) & \
0685     IRQAMP_PEXTACK_EID_4_0_MASK )
0686
0687 /** @} */
0688
0689 /**
0690  * @defgroup RTEMSDeviceGRLIBIRQAMPBADDR \
0691  *   Processor n Boot Address register (BADDR)
0692  *
0693  * @brief This group contains register bit definitions.
0694  *
0695  * @{
0696  */
0697
0698 #define IRQAMP_BADDR_BOOTADDR_31_3_SHIFT 3
0699 #define IRQAMP_BADDR_BOOTADDR_31_3_MASK 0xfffffff8U
0700 #define IRQAMP_BADDR_BOOTADDR_31_3_GET( _reg ) \
0701   ( ( ( _reg ) & IRQAMP_BADDR_BOOTADDR_31_3_MASK ) >> \
0702     IRQAMP_BADDR_BOOTADDR_31_3_SHIFT )
0703 #define IRQAMP_BADDR_BOOTADDR_31_3_SET( _reg, _val ) \
0704   ( ( ( _reg ) & ~IRQAMP_BADDR_BOOTADDR_31_3_MASK ) | \
0705     ( ( ( _val ) << IRQAMP_BADDR_BOOTADDR_31_3_SHIFT ) & \
0706       IRQAMP_BADDR_BOOTADDR_31_3_MASK ) )
0707 #define IRQAMP_BADDR_BOOTADDR_31_3( _val ) \
0708   ( ( ( _val ) << IRQAMP_BADDR_BOOTADDR_31_3_SHIFT ) & \
0709     IRQAMP_BADDR_BOOTADDR_31_3_MASK )
0710
0711 #define IRQAMP_BADDR_AS 0x1U
0712
0713 /** @} */
0714
0715 /**
0716  * @defgroup RTEMSDeviceGRLIBIRQAMPIRQMAP Interrupt map register n (IRQMAP)
0717  *
0718  * @brief This group contains register bit definitions.
0719  *
0720  * @{
0721  */
0722
0723 #define IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT 24
0724 #define IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK 0xff000000U
0725 #define IRQAMP_IRQMAP_IRQMAP_4_N_0_GET( _reg ) \
0726   ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK ) >> \
0727     IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT )
0728 #define IRQAMP_IRQMAP_IRQMAP_4_N_0_SET( _reg, _val ) \
0729   ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK ) | \
0730     ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT ) & \
0731       IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK ) )
0732 #define IRQAMP_IRQMAP_IRQMAP_4_N_0( _val ) \
0733   ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT ) & \
0734     IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK )
0735
0736 #define IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT 16
0737 #define IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK 0xff0000U
0738 #define IRQAMP_IRQMAP_IRQMAP_4_N_1_GET( _reg ) \
0739   ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK ) >> \
0740     IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT )
0741 #define IRQAMP_IRQMAP_IRQMAP_4_N_1_SET( _reg, _val ) \
0742   ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK ) | \
0743     ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT ) & \
0744       IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK ) )
0745 #define IRQAMP_IRQMAP_IRQMAP_4_N_1( _val ) \
0746   ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT ) & \
0747     IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK )
0748
0749 #define IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT 8
0750 #define IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK 0xff00U
0751 #define IRQAMP_IRQMAP_IRQMAP_4_N_2_GET( _reg ) \
0752   ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK ) >> \
0753     IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT )
0754 #define IRQAMP_IRQMAP_IRQMAP_4_N_2_SET( _reg, _val ) \
0755   ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK ) | \
0756     ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT ) & \
0757       IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK ) )
0758 #define IRQAMP_IRQMAP_IRQMAP_4_N_2( _val ) \
0759   ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT ) & \
0760     IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK )
0761
0762 #define IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT 0
0763 #define IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK 0xffU
0764 #define IRQAMP_IRQMAP_IRQMAP_4_N_3_GET( _reg ) \
0765   ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK ) >> \
0766     IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT )
0767 #define IRQAMP_IRQMAP_IRQMAP_4_N_3_SET( _reg, _val ) \
0768   ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK ) | \
0769     ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT ) & \
0770       IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK ) )
0771 #define IRQAMP_IRQMAP_IRQMAP_4_N_3( _val ) \
0772   ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT ) & \
0773     IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK )
0774
0775 /** @} */
0776
0777 /**
0778  * @brief This structure defines the IRQ(A)MP register block memory map.
0779  */
0780 typedef struct irqamp {
0781   /**
0782    * @brief See @ref RTEMSDeviceGRLIBIRQAMPILEVEL.
0783    */
0784   uint32_t ilevel;
0785
0786   /**
0787    * @brief See @ref RTEMSDeviceGRLIBIRQAMPIPEND.
0788    */
0789   uint32_t ipend;
0790
0791   /**
0792    * @brief See @ref RTEMSDeviceGRLIBIRQAMPIFORCE0.
0793    */
0794   uint32_t iforce0;
0795
0796   /**
0797    * @brief See @ref RTEMSDeviceGRLIBIRQAMPICLEAR.
0798    */
0799   uint32_t iclear;
0800
0801   /**
0802    * @brief See @ref RTEMSDeviceGRLIBIRQAMPMPSTAT.
0803    */
0804   uint32_t mpstat;
0805
0806   /**
0807    * @brief See @ref RTEMSDeviceGRLIBIRQAMPBRDCST.
0808    */
0809   uint32_t brdcst;
0810
0811   /**
0812    * @brief See @ref RTEMSDeviceGRLIBIRQAMPERRSTAT.
0813    */
0814   uint32_t errstat;
0815
0816   /**
0817    * @brief See @ref RTEMSDeviceGRLIBIRQAMPWDOGCTRL.
0818    */
0819   uint32_t wdogctrl;
0820
0821   /**
0822    * @brief See @ref RTEMSDeviceGRLIBIRQAMPASMPCTRL.
0823    */
0824   uint32_t asmpctrl;
0825
0826   /**
0827    * @brief See @ref RTEMSDeviceGRLIBIRQAMPICSELR.
0828    */
0829   uint32_t icselr[ 2 ];
0830
0831   uint32_t reserved_2c_40[ 5 ];
0832
0833   /**
0834    * @brief See @ref RTEMSDeviceGRLIBIRQAMPPIMASK.
0835    */
0836   uint32_t pimask[ 16 ];
0837
0838   /**
0839    * @brief See @ref RTEMSDeviceGRLIBIRQAMPPIFORCE.
0840    */
0841   uint32_t piforce[ 16 ];
0842
0843   /**
0844    * @brief See @ref RTEMSDeviceGRLIBIRQAMPPEXTACK.
0845    */
0846   uint32_t pextack[ 16 ];
0847
0848   /**
0849    * @brief See @ref RTEMSDeviceGRLIBIRQAMPTimestamp.
0850    */
0851   irqamp_timestamp itstmp[ 16 ];
0852
0853   /**
0854    * @brief See @ref RTEMSDeviceGRLIBIRQAMPBADDR.
0855    */
0856   uint32_t baddr[ 16 ];
0857
0858   uint32_t reserved_240_300[ 48 ];
0859
0860   /**
0861    * @brief See @ref RTEMSDeviceGRLIBIRQAMPIRQMAP.
0862    */
0863   uint32_t irqmap[ 16 ];
0864
0865   uint32_t reserved_340_400[ 48 ];
0866 } irqamp;
0867
0868 /** @} */
0869
0870 #ifdef __cplusplus
0871 }
0872 #endif
0873
0874 #endif /* _GRLIB_IRQAMP_REGS_H */