include/grlib/grspwrouter-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRSPWROUTER
0007  *
0008  * @brief This header file defines the GRSPWROUTER register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/grspwrouter-header */
0054
0055 #ifndef _GRLIB_GRSPWROUTER_REGS_H
0056 #define _GRLIB_GRSPWROUTER_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/grspwrouter-portstats */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRSPWRouterPortStats SpaceWire Router Port Statistics
0068  *
0069  * @ingroup RTEMSDeviceGRSPWROUTER
0070  *
0071  * @brief This group contains the SpaceWire Router Port Statistics interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRSPWRouterPortStatsOCHARCNT \
0078  *   Outgoing character counter, ports > 0 (OCHARCNT)
0079  *
0080  * @brief This group contains register bit definitions.
0081  *
0082  * @{
0083  */
0084
0085 #define GRSPWROUTER_OCHARCNT_OR 0x80000000U
0086
0087 #define GRSPWROUTER_OCHARCNT_CC_SHIFT 0
0088 #define GRSPWROUTER_OCHARCNT_CC_MASK 0x7fffffffU
0089 #define GRSPWROUTER_OCHARCNT_CC_GET( _reg ) \
0090   ( ( ( _reg ) & GRSPWROUTER_OCHARCNT_CC_MASK ) >> \
0091     GRSPWROUTER_OCHARCNT_CC_SHIFT )
0092 #define GRSPWROUTER_OCHARCNT_CC_SET( _reg, _val ) \
0093   ( ( ( _reg ) & ~GRSPWROUTER_OCHARCNT_CC_MASK ) | \
0094     ( ( ( _val ) << GRSPWROUTER_OCHARCNT_CC_SHIFT ) & \
0095       GRSPWROUTER_OCHARCNT_CC_MASK ) )
0096 #define GRSPWROUTER_OCHARCNT_CC( _val ) \
0097   ( ( ( _val ) << GRSPWROUTER_OCHARCNT_CC_SHIFT ) & \
0098     GRSPWROUTER_OCHARCNT_CC_MASK )
0099
0100 /** @} */
0101
0102 /**
0103  * @defgroup RTEMSDeviceGRSPWRouterPortStatsICHARCNT \
0104  *   Incoming character counter, ports > 0 (ICHARCNT)
0105  *
0106  * @brief This group contains register bit definitions.
0107  *
0108  * @{
0109  */
0110
0111 #define GRSPWROUTER_ICHARCNT_OR 0x80000000U
0112
0113 #define GRSPWROUTER_ICHARCNT_CC_SHIFT 0
0114 #define GRSPWROUTER_ICHARCNT_CC_MASK 0x7fffffffU
0115 #define GRSPWROUTER_ICHARCNT_CC_GET( _reg ) \
0116   ( ( ( _reg ) & GRSPWROUTER_ICHARCNT_CC_MASK ) >> \
0117     GRSPWROUTER_ICHARCNT_CC_SHIFT )
0118 #define GRSPWROUTER_ICHARCNT_CC_SET( _reg, _val ) \
0119   ( ( ( _reg ) & ~GRSPWROUTER_ICHARCNT_CC_MASK ) | \
0120     ( ( ( _val ) << GRSPWROUTER_ICHARCNT_CC_SHIFT ) & \
0121       GRSPWROUTER_ICHARCNT_CC_MASK ) )
0122 #define GRSPWROUTER_ICHARCNT_CC( _val ) \
0123   ( ( ( _val ) << GRSPWROUTER_ICHARCNT_CC_SHIFT ) & \
0124     GRSPWROUTER_ICHARCNT_CC_MASK )
0125
0126 /** @} */
0127
0128 /**
0129  * @defgroup RTEMSDeviceGRSPWRouterPortStatsOPKTCNT \
0130  *   Outgoing packet counter, ports > 0 (OPKTCNT)
0131  *
0132  * @brief This group contains register bit definitions.
0133  *
0134  * @{
0135  */
0136
0137 #define GRSPWROUTER_OPKTCNT_OR 0x80000000U
0138
0139 #define GRSPWROUTER_OPKTCNT_PC_SHIFT 0
0140 #define GRSPWROUTER_OPKTCNT_PC_MASK 0x7fffffffU
0141 #define GRSPWROUTER_OPKTCNT_PC_GET( _reg ) \
0142   ( ( ( _reg ) & GRSPWROUTER_OPKTCNT_PC_MASK ) >> \
0143     GRSPWROUTER_OPKTCNT_PC_SHIFT )
0144 #define GRSPWROUTER_OPKTCNT_PC_SET( _reg, _val ) \
0145   ( ( ( _reg ) & ~GRSPWROUTER_OPKTCNT_PC_MASK ) | \
0146     ( ( ( _val ) << GRSPWROUTER_OPKTCNT_PC_SHIFT ) & \
0147       GRSPWROUTER_OPKTCNT_PC_MASK ) )
0148 #define GRSPWROUTER_OPKTCNT_PC( _val ) \
0149   ( ( ( _val ) << GRSPWROUTER_OPKTCNT_PC_SHIFT ) & \
0150     GRSPWROUTER_OPKTCNT_PC_MASK )
0151
0152 /** @} */
0153
0154 /**
0155  * @defgroup RTEMSDeviceGRSPWRouterPortStatsIPKTCNT \
0156  *   Incoming packet counter, ports > 0 (IPKTCNT)
0157  *
0158  * @brief This group contains register bit definitions.
0159  *
0160  * @{
0161  */
0162
0163 #define GRSPWROUTER_IPKTCNT_OR 0x80000000U
0164
0165 #define GRSPWROUTER_IPKTCNT_PC_SHIFT 0
0166 #define GRSPWROUTER_IPKTCNT_PC_MASK 0x7fffffffU
0167 #define GRSPWROUTER_IPKTCNT_PC_GET( _reg ) \
0168   ( ( ( _reg ) & GRSPWROUTER_IPKTCNT_PC_MASK ) >> \
0169     GRSPWROUTER_IPKTCNT_PC_SHIFT )
0170 #define GRSPWROUTER_IPKTCNT_PC_SET( _reg, _val ) \
0171   ( ( ( _reg ) & ~GRSPWROUTER_IPKTCNT_PC_MASK ) | \
0172     ( ( ( _val ) << GRSPWROUTER_IPKTCNT_PC_SHIFT ) & \
0173       GRSPWROUTER_IPKTCNT_PC_MASK ) )
0174 #define GRSPWROUTER_IPKTCNT_PC( _val ) \
0175   ( ( ( _val ) << GRSPWROUTER_IPKTCNT_PC_SHIFT ) & \
0176     GRSPWROUTER_IPKTCNT_PC_MASK )
0177
0178 /** @} */
0179
0180 /**
0181  * @brief This structure defines the SpaceWire Router Port Statistics register
0182  *   block memory map.
0183  */
0184 typedef struct grspwrouter_portstats {
0185   /**
0186    * @brief See @ref RTEMSDeviceGRSPWRouterPortStatsOCHARCNT.
0187    */
0188   uint32_t ocharcnt;
0189
0190   /**
0191    * @brief See @ref RTEMSDeviceGRSPWRouterPortStatsICHARCNT.
0192    */
0193   uint32_t icharcnt;
0194
0195   /**
0196    * @brief See @ref RTEMSDeviceGRSPWRouterPortStatsOPKTCNT.
0197    */
0198   uint32_t opktcnt;
0199
0200   /**
0201    * @brief See @ref RTEMSDeviceGRSPWRouterPortStatsIPKTCNT.
0202    */
0203   uint32_t ipktcnt;
0204 } grspwrouter_portstats;
0205
0206 /** @} */
0207
0208 /* Generated from spec:/dev/grlib/if/grspwrouter */
0209
0210 /**
0211  * @defgroup RTEMSDeviceGRSPWROUTER SpaceWire Router
0212  *
0213  * @ingroup RTEMSDeviceGRLIB
0214  *
0215  * @brief This group contains the SpaceWire Router interfaces.
0216  *
0217  * @{
0218  */
0219
0220 /**
0221  * @defgroup RTEMSDeviceGRSPWROUTERRTPMAP \
0222  *   Routing table port mapping, addresses 1-31 and 32-255 (RTPMAP)
0223  *
0224  * @brief This group contains register bit definitions.
0225  *
0226  * @{
0227  */
0228
0229 #define GRSPWROUTER_RTPMAP_PE_SHIFT 1
0230 #define GRSPWROUTER_RTPMAP_PE_MASK 0xfffffffeU
0231 #define GRSPWROUTER_RTPMAP_PE_GET( _reg ) \
0232   ( ( ( _reg ) & GRSPWROUTER_RTPMAP_PE_MASK ) >> \
0233     GRSPWROUTER_RTPMAP_PE_SHIFT )
0234 #define GRSPWROUTER_RTPMAP_PE_SET( _reg, _val ) \
0235   ( ( ( _reg ) & ~GRSPWROUTER_RTPMAP_PE_MASK ) | \
0236     ( ( ( _val ) << GRSPWROUTER_RTPMAP_PE_SHIFT ) & \
0237       GRSPWROUTER_RTPMAP_PE_MASK ) )
0238 #define GRSPWROUTER_RTPMAP_PE( _val ) \
0239   ( ( ( _val ) << GRSPWROUTER_RTPMAP_PE_SHIFT ) & \
0240     GRSPWROUTER_RTPMAP_PE_MASK )
0241
0242 #define GRSPWROUTER_RTPMAP_PD 0x1U
0243
0244 /** @} */
0245
0246 /**
0247  * @defgroup RTEMSDeviceGRSPWROUTERRTACTRL \
0248  *   Routing table address control, addresses 1-31 and 32-255 (RTACTRL)
0249  *
0250  * @brief This group contains register bit definitions.
0251  *
0252  * @{
0253  */
0254
0255 #define GRSPWROUTER_RTACTRL_SR 0x8U
0256
0257 #define GRSPWROUTER_RTACTRL_EN 0x4U
0258
0259 #define GRSPWROUTER_RTACTRL_PR 0x2U
0260
0261 #define GRSPWROUTER_RTACTRL_HD 0x1U
0262
0263 /** @} */
0264
0265 /**
0266  * @defgroup RTEMSDeviceGRSPWROUTERPCTRLCFG \
0267  *   Port control, port 0 (configuration port) (PCTRLCFG)
0268  *
0269  * @brief This group contains register bit definitions.
0270  *
0271  * @{
0272  */
0273
0274 #define GRSPWROUTER_PCTRLCFG_PL 0x20000U
0275
0276 #define GRSPWROUTER_PCTRLCFG_TS 0x10000U
0277
0278 #define GRSPWROUTER_PCTRLCFG_TR 0x200U
0279
0280 /** @} */
0281
0282 /**
0283  * @defgroup RTEMSDeviceGRSPWROUTERPCTRL Port control, ports > 0 (PCTRL)
0284  *
0285  * @brief This group contains register bit definitions.
0286  *
0287  * @{
0288  */
0289
0290 #define GRSPWROUTER_PCTRL_RD_SHIFT 24
0291 #define GRSPWROUTER_PCTRL_RD_MASK 0xff000000U
0292 #define GRSPWROUTER_PCTRL_RD_GET( _reg ) \
0293   ( ( ( _reg ) & GRSPWROUTER_PCTRL_RD_MASK ) >> \
0294     GRSPWROUTER_PCTRL_RD_SHIFT )
0295 #define GRSPWROUTER_PCTRL_RD_SET( _reg, _val ) \
0296   ( ( ( _reg ) & ~GRSPWROUTER_PCTRL_RD_MASK ) | \
0297     ( ( ( _val ) << GRSPWROUTER_PCTRL_RD_SHIFT ) & \
0298       GRSPWROUTER_PCTRL_RD_MASK ) )
0299 #define GRSPWROUTER_PCTRL_RD( _val ) \
0300   ( ( ( _val ) << GRSPWROUTER_PCTRL_RD_SHIFT ) & \
0301     GRSPWROUTER_PCTRL_RD_MASK )
0302
0303 #define GRSPWROUTER_PCTRL_RES_SHIFT 22
0304 #define GRSPWROUTER_PCTRL_RES_MASK 0xc00000U
0305 #define GRSPWROUTER_PCTRL_RES_GET( _reg ) \
0306   ( ( ( _reg ) & GRSPWROUTER_PCTRL_RES_MASK ) >> \
0307     GRSPWROUTER_PCTRL_RES_SHIFT )
0308 #define GRSPWROUTER_PCTRL_RES_SET( _reg, _val ) \
0309   ( ( ( _reg ) & ~GRSPWROUTER_PCTRL_RES_MASK ) | \
0310     ( ( ( _val ) << GRSPWROUTER_PCTRL_RES_SHIFT ) & \
0311       GRSPWROUTER_PCTRL_RES_MASK ) )
0312 #define GRSPWROUTER_PCTRL_RES( _val ) \
0313   ( ( ( _val ) << GRSPWROUTER_PCTRL_RES_SHIFT ) & \
0314     GRSPWROUTER_PCTRL_RES_MASK )
0315
0316 #define GRSPWROUTER_PCTRL_ST 0x200000U
0317
0318 #define GRSPWROUTER_PCTRL_SR 0x100000U
0319
0320 #define GRSPWROUTER_PCTRL_AD 0x80000U
0321
0322 #define GRSPWROUTER_PCTRL_LR 0x40000U
0323
0324 #define GRSPWROUTER_PCTRL_PL 0x20000U
0325
0326 #define GRSPWROUTER_PCTRL_TS 0x10000U
0327
0328 #define GRSPWROUTER_PCTRL_IC 0x8000U
0329
0330 #define GRSPWROUTER_PCTRL_ET 0x4000U
0331
0332 #define GRSPWROUTER_PCTRL_NF 0x2000U
0333
0334 #define GRSPWROUTER_PCTRL_PS 0x1000U
0335
0336 #define GRSPWROUTER_PCTRL_BE 0x800U
0337
0338 #define GRSPWROUTER_PCTRL_DI 0x400U
0339
0340 #define GRSPWROUTER_PCTRL_TR 0x200U
0341
0342 #define GRSPWROUTER_PCTRL_PR 0x100U
0343
0344 #define GRSPWROUTER_PCTRL_TF 0x80U
0345
0346 #define GRSPWROUTER_PCTRL_RS 0x40U
0347
0348 #define GRSPWROUTER_PCTRL_TE 0x20U
0349
0350 #define GRSPWROUTER_PCTRL_R 0x10U
0351
0352 #define GRSPWROUTER_PCTRL_CE 0x8U
0353
0354 #define GRSPWROUTER_PCTRL_AS 0x4U
0355
0356 #define GRSPWROUTER_PCTRL_LS 0x2U
0357
0358 #define GRSPWROUTER_PCTRL_LD 0x1U
0359
0360 /** @} */
0361
0362 /**
0363  * @defgroup RTEMSDeviceGRSPWROUTERPSTSCFG \
0364  *   Port status, port 0 (configuration port) (PSTSCFG)
0365  *
0366  * @brief This group contains register bit definitions.
0367  *
0368  * @{
0369  */
0370
0371 #define GRSPWROUTER_PSTSCFG_EO 0x80000000U
0372
0373 #define GRSPWROUTER_PSTSCFG_EE 0x40000000U
0374
0375 #define GRSPWROUTER_PSTSCFG_PL 0x20000000U
0376
0377 #define GRSPWROUTER_PSTSCFG_TT 0x10000000U
0378
0379 #define GRSPWROUTER_PSTSCFG_PT 0x8000000U
0380
0381 #define GRSPWROUTER_PSTSCFG_HC 0x4000000U
0382
0383 #define GRSPWROUTER_PSTSCFG_PI 0x2000000U
0384
0385 #define GRSPWROUTER_PSTSCFG_CE 0x1000000U
0386
0387 #define GRSPWROUTER_PSTSCFG_EC_SHIFT 20
0388 #define GRSPWROUTER_PSTSCFG_EC_MASK 0xf00000U
0389 #define GRSPWROUTER_PSTSCFG_EC_GET( _reg ) \
0390   ( ( ( _reg ) & GRSPWROUTER_PSTSCFG_EC_MASK ) >> \
0391     GRSPWROUTER_PSTSCFG_EC_SHIFT )
0392 #define GRSPWROUTER_PSTSCFG_EC_SET( _reg, _val ) \
0393   ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_EC_MASK ) | \
0394     ( ( ( _val ) << GRSPWROUTER_PSTSCFG_EC_SHIFT ) & \
0395       GRSPWROUTER_PSTSCFG_EC_MASK ) )
0396 #define GRSPWROUTER_PSTSCFG_EC( _val ) \
0397   ( ( ( _val ) << GRSPWROUTER_PSTSCFG_EC_SHIFT ) & \
0398     GRSPWROUTER_PSTSCFG_EC_MASK )
0399
0400 #define GRSPWROUTER_PSTSCFG_R 0x80000U
0401
0402 #define GRSPWROUTER_PSTSCFG_TS 0x40000U
0403
0404 #define GRSPWROUTER_PSTSCFG_ME 0x20000U
0405
0406 #define GRSPWROUTER_PSTSCFG_IP_SHIFT 7
0407 #define GRSPWROUTER_PSTSCFG_IP_MASK 0xf80U
0408 #define GRSPWROUTER_PSTSCFG_IP_GET( _reg ) \
0409   ( ( ( _reg ) & GRSPWROUTER_PSTSCFG_IP_MASK ) >> \
0410     GRSPWROUTER_PSTSCFG_IP_SHIFT )
0411 #define GRSPWROUTER_PSTSCFG_IP_SET( _reg, _val ) \
0412   ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_IP_MASK ) | \
0413     ( ( ( _val ) << GRSPWROUTER_PSTSCFG_IP_SHIFT ) & \
0414       GRSPWROUTER_PSTSCFG_IP_MASK ) )
0415 #define GRSPWROUTER_PSTSCFG_IP( _val ) \
0416   ( ( ( _val ) << GRSPWROUTER_PSTSCFG_IP_SHIFT ) & \
0417     GRSPWROUTER_PSTSCFG_IP_MASK )
0418
0419 #define GRSPWROUTER_PSTSCFG_RES_SHIFT 5
0420 #define GRSPWROUTER_PSTSCFG_RES_MASK 0x60U
0421 #define GRSPWROUTER_PSTSCFG_RES_GET( _reg ) \
0422   ( ( ( _reg ) & GRSPWROUTER_PSTSCFG_RES_MASK ) >> \
0423     GRSPWROUTER_PSTSCFG_RES_SHIFT )
0424 #define GRSPWROUTER_PSTSCFG_RES_SET( _reg, _val ) \
0425   ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_RES_MASK ) | \
0426     ( ( ( _val ) << GRSPWROUTER_PSTSCFG_RES_SHIFT ) & \
0427       GRSPWROUTER_PSTSCFG_RES_MASK ) )
0428 #define GRSPWROUTER_PSTSCFG_RES( _val ) \
0429   ( ( ( _val ) << GRSPWROUTER_PSTSCFG_RES_SHIFT ) & \
0430     GRSPWROUTER_PSTSCFG_RES_MASK )
0431
0432 #define GRSPWROUTER_PSTSCFG_CP 0x10U
0433
0434 #define GRSPWROUTER_PSTSCFG_PC_SHIFT 0
0435 #define GRSPWROUTER_PSTSCFG_PC_MASK 0xfU
0436 #define GRSPWROUTER_PSTSCFG_PC_GET( _reg ) \
0437   ( ( ( _reg ) & GRSPWROUTER_PSTSCFG_PC_MASK ) >> \
0438     GRSPWROUTER_PSTSCFG_PC_SHIFT )
0439 #define GRSPWROUTER_PSTSCFG_PC_SET( _reg, _val ) \
0440   ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_PC_MASK ) | \
0441     ( ( ( _val ) << GRSPWROUTER_PSTSCFG_PC_SHIFT ) & \
0442       GRSPWROUTER_PSTSCFG_PC_MASK ) )
0443 #define GRSPWROUTER_PSTSCFG_PC( _val ) \
0444   ( ( ( _val ) << GRSPWROUTER_PSTSCFG_PC_SHIFT ) & \
0445     GRSPWROUTER_PSTSCFG_PC_MASK )
0446
0447 /** @} */
0448
0449 /**
0450  * @defgroup RTEMSDeviceGRSPWROUTERPSTS Port status, ports > 0 (PSTS)
0451  *
0452  * @brief This group contains register bit definitions.
0453  *
0454  * @{
0455  */
0456
0457 #define GRSPWROUTER_PSTS_PT_SHIFT 30
0458 #define GRSPWROUTER_PSTS_PT_MASK 0xc0000000U
0459 #define GRSPWROUTER_PSTS_PT_GET( _reg ) \
0460   ( ( ( _reg ) & GRSPWROUTER_PSTS_PT_MASK ) >> \
0461     GRSPWROUTER_PSTS_PT_SHIFT )
0462 #define GRSPWROUTER_PSTS_PT_SET( _reg, _val ) \
0463   ( ( ( _reg ) & ~GRSPWROUTER_PSTS_PT_MASK ) | \
0464     ( ( ( _val ) << GRSPWROUTER_PSTS_PT_SHIFT ) & \
0465       GRSPWROUTER_PSTS_PT_MASK ) )
0466 #define GRSPWROUTER_PSTS_PT( _val ) \
0467   ( ( ( _val ) << GRSPWROUTER_PSTS_PT_SHIFT ) & \
0468     GRSPWROUTER_PSTS_PT_MASK )
0469
0470 #define GRSPWROUTER_PSTS_PL 0x20000000U
0471
0472 #define GRSPWROUTER_PSTS_TT 0x10000000U
0473
0474 #define GRSPWROUTER_PSTS_RS 0x8000000U
0475
0476 #define GRSPWROUTER_PSTS_SR 0x4000000U
0477
0478 #define GRSPWROUTER_PSTS_LR 0x400000U
0479
0480 #define GRSPWROUTER_PSTS_SP 0x200000U
0481
0482 #define GRSPWROUTER_PSTS_AC 0x100000U
0483
0484 #define GRSPWROUTER_PSTS_AP 0x80000U
0485
0486 #define GRSPWROUTER_PSTS_TS 0x40000U
0487
0488 #define GRSPWROUTER_PSTS_ME 0x20000U
0489
0490 #define GRSPWROUTER_PSTS_TF 0x10000U
0491
0492 #define GRSPWROUTER_PSTS_RE 0x8000U
0493
0494 #define GRSPWROUTER_PSTS_LS_SHIFT 12
0495 #define GRSPWROUTER_PSTS_LS_MASK 0x7000U
0496 #define GRSPWROUTER_PSTS_LS_GET( _reg ) \
0497   ( ( ( _reg ) & GRSPWROUTER_PSTS_LS_MASK ) >> \
0498     GRSPWROUTER_PSTS_LS_SHIFT )
0499 #define GRSPWROUTER_PSTS_LS_SET( _reg, _val ) \
0500   ( ( ( _reg ) & ~GRSPWROUTER_PSTS_LS_MASK ) | \
0501     ( ( ( _val ) << GRSPWROUTER_PSTS_LS_SHIFT ) & \
0502       GRSPWROUTER_PSTS_LS_MASK ) )
0503 #define GRSPWROUTER_PSTS_LS( _val ) \
0504   ( ( ( _val ) << GRSPWROUTER_PSTS_LS_SHIFT ) & \
0505     GRSPWROUTER_PSTS_LS_MASK )
0506
0507 #define GRSPWROUTER_PSTS_IP_SHIFT 7
0508 #define GRSPWROUTER_PSTS_IP_MASK 0xf80U
0509 #define GRSPWROUTER_PSTS_IP_GET( _reg ) \
0510   ( ( ( _reg ) & GRSPWROUTER_PSTS_IP_MASK ) >> \
0511     GRSPWROUTER_PSTS_IP_SHIFT )
0512 #define GRSPWROUTER_PSTS_IP_SET( _reg, _val ) \
0513   ( ( ( _reg ) & ~GRSPWROUTER_PSTS_IP_MASK ) | \
0514     ( ( ( _val ) << GRSPWROUTER_PSTS_IP_SHIFT ) & \
0515       GRSPWROUTER_PSTS_IP_MASK ) )
0516 #define GRSPWROUTER_PSTS_IP( _val ) \
0517   ( ( ( _val ) << GRSPWROUTER_PSTS_IP_SHIFT ) & \
0518     GRSPWROUTER_PSTS_IP_MASK )
0519
0520 #define GRSPWROUTER_PSTS_PR 0x40U
0521
0522 #define GRSPWROUTER_PSTS_PB 0x20U
0523
0524 #define GRSPWROUTER_PSTS_IA 0x10U
0525
0526 #define GRSPWROUTER_PSTS_CE 0x8U
0527
0528 #define GRSPWROUTER_PSTS_ER 0x4U
0529
0530 #define GRSPWROUTER_PSTS_DE 0x2U
0531
0532 #define GRSPWROUTER_PSTS_PE 0x1U
0533
0534 /** @} */
0535
0536 /**
0537  * @defgroup RTEMSDeviceGRSPWROUTERPTIMER Port timer reload (PTIMER)
0538  *
0539  * @brief This group contains register bit definitions.
0540  *
0541  * @{
0542  */
0543
0544 #define GRSPWROUTER_PTIMER_RL_SHIFT 0
0545 #define GRSPWROUTER_PTIMER_RL_MASK 0x3ffU
0546 #define GRSPWROUTER_PTIMER_RL_GET( _reg ) \
0547   ( ( ( _reg ) & GRSPWROUTER_PTIMER_RL_MASK ) >> \
0548     GRSPWROUTER_PTIMER_RL_SHIFT )
0549 #define GRSPWROUTER_PTIMER_RL_SET( _reg, _val ) \
0550   ( ( ( _reg ) & ~GRSPWROUTER_PTIMER_RL_MASK ) | \
0551     ( ( ( _val ) << GRSPWROUTER_PTIMER_RL_SHIFT ) & \
0552       GRSPWROUTER_PTIMER_RL_MASK ) )
0553 #define GRSPWROUTER_PTIMER_RL( _val ) \
0554   ( ( ( _val ) << GRSPWROUTER_PTIMER_RL_SHIFT ) & \
0555     GRSPWROUTER_PTIMER_RL_MASK )
0556
0557 /** @} */
0558
0559 /**
0560  * @defgroup RTEMSDeviceGRSPWROUTERPCTRL2CFG \
0561  *   Port control 2, port 0 (configuration port) (PCTRL2CFG)
0562  *
0563  * @brief This group contains register bit definitions.
0564  *
0565  * @{
0566  */
0567
0568 #define GRSPWROUTER_PCTRL2CFG_SM_SHIFT 24
0569 #define GRSPWROUTER_PCTRL2CFG_SM_MASK 0xff000000U
0570 #define GRSPWROUTER_PCTRL2CFG_SM_GET( _reg ) \
0571   ( ( ( _reg ) & GRSPWROUTER_PCTRL2CFG_SM_MASK ) >> \
0572     GRSPWROUTER_PCTRL2CFG_SM_SHIFT )
0573 #define GRSPWROUTER_PCTRL2CFG_SM_SET( _reg, _val ) \
0574   ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2CFG_SM_MASK ) | \
0575     ( ( ( _val ) << GRSPWROUTER_PCTRL2CFG_SM_SHIFT ) & \
0576       GRSPWROUTER_PCTRL2CFG_SM_MASK ) )
0577 #define GRSPWROUTER_PCTRL2CFG_SM( _val ) \
0578   ( ( ( _val ) << GRSPWROUTER_PCTRL2CFG_SM_SHIFT ) & \
0579     GRSPWROUTER_PCTRL2CFG_SM_MASK )
0580
0581 #define GRSPWROUTER_PCTRL2CFG_SV_SHIFT 16
0582 #define GRSPWROUTER_PCTRL2CFG_SV_MASK 0xff0000U
0583 #define GRSPWROUTER_PCTRL2CFG_SV_GET( _reg ) \
0584   ( ( ( _reg ) & GRSPWROUTER_PCTRL2CFG_SV_MASK ) >> \
0585     GRSPWROUTER_PCTRL2CFG_SV_SHIFT )
0586 #define GRSPWROUTER_PCTRL2CFG_SV_SET( _reg, _val ) \
0587   ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2CFG_SV_MASK ) | \
0588     ( ( ( _val ) << GRSPWROUTER_PCTRL2CFG_SV_SHIFT ) & \
0589       GRSPWROUTER_PCTRL2CFG_SV_MASK ) )
0590 #define GRSPWROUTER_PCTRL2CFG_SV( _val ) \
0591   ( ( ( _val ) << GRSPWROUTER_PCTRL2CFG_SV_SHIFT ) & \
0592     GRSPWROUTER_PCTRL2CFG_SV_MASK )
0593
0594 #define GRSPWROUTER_PCTRL2CFG_OR 0x8000U
0595
0596 /** @} */
0597
0598 /**
0599  * @defgroup RTEMSDeviceGRSPWROUTERPCTRL2 Port control 2, ports > 0 (PCTRL2)
0600  *
0601  * @brief This group contains register bit definitions.
0602  *
0603  * @{
0604  */
0605
0606 #define GRSPWROUTER_PCTRL2_SM_SHIFT 24
0607 #define GRSPWROUTER_PCTRL2_SM_MASK 0xff000000U
0608 #define GRSPWROUTER_PCTRL2_SM_GET( _reg ) \
0609   ( ( ( _reg ) & GRSPWROUTER_PCTRL2_SM_MASK ) >> \
0610     GRSPWROUTER_PCTRL2_SM_SHIFT )
0611 #define GRSPWROUTER_PCTRL2_SM_SET( _reg, _val ) \
0612   ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2_SM_MASK ) | \
0613     ( ( ( _val ) << GRSPWROUTER_PCTRL2_SM_SHIFT ) & \
0614       GRSPWROUTER_PCTRL2_SM_MASK ) )
0615 #define GRSPWROUTER_PCTRL2_SM( _val ) \
0616   ( ( ( _val ) << GRSPWROUTER_PCTRL2_SM_SHIFT ) & \
0617     GRSPWROUTER_PCTRL2_SM_MASK )
0618
0619 #define GRSPWROUTER_PCTRL2_SV_SHIFT 16
0620 #define GRSPWROUTER_PCTRL2_SV_MASK 0xff0000U
0621 #define GRSPWROUTER_PCTRL2_SV_GET( _reg ) \
0622   ( ( ( _reg ) & GRSPWROUTER_PCTRL2_SV_MASK ) >> \
0623     GRSPWROUTER_PCTRL2_SV_SHIFT )
0624 #define GRSPWROUTER_PCTRL2_SV_SET( _reg, _val ) \
0625   ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2_SV_MASK ) | \
0626     ( ( ( _val ) << GRSPWROUTER_PCTRL2_SV_SHIFT ) & \
0627       GRSPWROUTER_PCTRL2_SV_MASK ) )
0628 #define GRSPWROUTER_PCTRL2_SV( _val ) \
0629   ( ( ( _val ) << GRSPWROUTER_PCTRL2_SV_SHIFT ) & \
0630     GRSPWROUTER_PCTRL2_SV_MASK )
0631
0632 #define GRSPWROUTER_PCTRL2_OR 0x8000U
0633
0634 #define GRSPWROUTER_PCTRL2_UR 0x4000U
0635
0636 #define GRSPWROUTER_PCTRL2_R 0x2000U
0637
0638 #define GRSPWROUTER_PCTRL2_AT 0x1000U
0639
0640 #define GRSPWROUTER_PCTRL2_AR 0x800U
0641
0642 #define GRSPWROUTER_PCTRL2_IT 0x400U
0643
0644 #define GRSPWROUTER_PCTRL2_IR 0x200U
0645
0646 #define GRSPWROUTER_PCTRL2_SD_SHIFT 1
0647 #define GRSPWROUTER_PCTRL2_SD_MASK 0x3eU
0648 #define GRSPWROUTER_PCTRL2_SD_GET( _reg ) \
0649   ( ( ( _reg ) & GRSPWROUTER_PCTRL2_SD_MASK ) >> \
0650     GRSPWROUTER_PCTRL2_SD_SHIFT )
0651 #define GRSPWROUTER_PCTRL2_SD_SET( _reg, _val ) \
0652   ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2_SD_MASK ) | \
0653     ( ( ( _val ) << GRSPWROUTER_PCTRL2_SD_SHIFT ) & \
0654       GRSPWROUTER_PCTRL2_SD_MASK ) )
0655 #define GRSPWROUTER_PCTRL2_SD( _val ) \
0656   ( ( ( _val ) << GRSPWROUTER_PCTRL2_SD_SHIFT ) & \
0657     GRSPWROUTER_PCTRL2_SD_MASK )
0658
0659 #define GRSPWROUTER_PCTRL2_SC 0x1U
0660
0661 /** @} */
0662
0663 /**
0664  * @defgroup RTEMSDeviceGRSPWROUTERRTRCFG \
0665  *   Router configuration / status (RTRCFG)
0666  *
0667  * @brief This group contains register bit definitions.
0668  *
0669  * @{
0670  */
0671
0672 #define GRSPWROUTER_RTRCFG_SP_SHIFT 27
0673 #define GRSPWROUTER_RTRCFG_SP_MASK 0xf8000000U
0674 #define GRSPWROUTER_RTRCFG_SP_GET( _reg ) \
0675   ( ( ( _reg ) & GRSPWROUTER_RTRCFG_SP_MASK ) >> \
0676     GRSPWROUTER_RTRCFG_SP_SHIFT )
0677 #define GRSPWROUTER_RTRCFG_SP_SET( _reg, _val ) \
0678   ( ( ( _reg ) & ~GRSPWROUTER_RTRCFG_SP_MASK ) | \
0679     ( ( ( _val ) << GRSPWROUTER_RTRCFG_SP_SHIFT ) & \
0680       GRSPWROUTER_RTRCFG_SP_MASK ) )
0681 #define GRSPWROUTER_RTRCFG_SP( _val ) \
0682   ( ( ( _val ) << GRSPWROUTER_RTRCFG_SP_SHIFT ) & \
0683     GRSPWROUTER_RTRCFG_SP_MASK )
0684
0685 #define GRSPWROUTER_RTRCFG_AP_SHIFT 22
0686 #define GRSPWROUTER_RTRCFG_AP_MASK 0x7c00000U
0687 #define GRSPWROUTER_RTRCFG_AP_GET( _reg ) \
0688   ( ( ( _reg ) & GRSPWROUTER_RTRCFG_AP_MASK ) >> \
0689     GRSPWROUTER_RTRCFG_AP_SHIFT )
0690 #define GRSPWROUTER_RTRCFG_AP_SET( _reg, _val ) \
0691   ( ( ( _reg ) & ~GRSPWROUTER_RTRCFG_AP_MASK ) | \
0692     ( ( ( _val ) << GRSPWROUTER_RTRCFG_AP_SHIFT ) & \
0693       GRSPWROUTER_RTRCFG_AP_MASK ) )
0694 #define GRSPWROUTER_RTRCFG_AP( _val ) \
0695   ( ( ( _val ) << GRSPWROUTER_RTRCFG_AP_SHIFT ) & \
0696     GRSPWROUTER_RTRCFG_AP_MASK )
0697
0698 #define GRSPWROUTER_RTRCFG_FP_SHIFT 17
0699 #define GRSPWROUTER_RTRCFG_FP_MASK 0x3e0000U
0700 #define GRSPWROUTER_RTRCFG_FP_GET( _reg ) \
0701   ( ( ( _reg ) & GRSPWROUTER_RTRCFG_FP_MASK ) >> \
0702     GRSPWROUTER_RTRCFG_FP_SHIFT )
0703 #define GRSPWROUTER_RTRCFG_FP_SET( _reg, _val ) \
0704   ( ( ( _reg ) & ~GRSPWROUTER_RTRCFG_FP_MASK ) | \
0705     ( ( ( _val ) << GRSPWROUTER_RTRCFG_FP_SHIFT ) & \
0706       GRSPWROUTER_RTRCFG_FP_MASK ) )
0707 #define GRSPWROUTER_RTRCFG_FP( _val ) \
0708   ( ( ( _val ) << GRSPWROUTER_RTRCFG_FP_SHIFT ) & \
0709     GRSPWROUTER_RTRCFG_FP_MASK )
0710
0711 #define GRSPWROUTER_RTRCFG_R 0x10000U
0712
0713 #define GRSPWROUTER_RTRCFG_SR 0x8000U
0714
0715 #define GRSPWROUTER_RTRCFG_PE 0x4000U
0716
0717 #define GRSPWROUTER_RTRCFG_IC 0x2000U
0718
0719 #define GRSPWROUTER_RTRCFG_IS 0x1000U
0720
0721 #define GRSPWROUTER_RTRCFG_IP 0x800U
0722
0723 #define GRSPWROUTER_RTRCFG_AI 0x400U
0724
0725 #define GRSPWROUTER_RTRCFG_AT 0x200U
0726
0727 #define GRSPWROUTER_RTRCFG_IE 0x100U
0728
0729 #define GRSPWROUTER_RTRCFG_RE 0x80U
0730
0731 #define GRSPWROUTER_RTRCFG_EE 0x40U
0732
0733 #define GRSPWROUTER_RTRCFG_R 0x20U
0734
0735 #define GRSPWROUTER_RTRCFG_SA 0x10U
0736
0737 #define GRSPWROUTER_RTRCFG_TF 0x8U
0738
0739 #define GRSPWROUTER_RTRCFG_RM 0x4U
0740
0741 #define GRSPWROUTER_RTRCFG_TA 0x2U
0742
0743 #define GRSPWROUTER_RTRCFG_PP 0x1U
0744
0745 /** @} */
0746
0747 /**
0748  * @defgroup RTEMSDeviceGRSPWROUTERTC Time-code (TC)
0749  *
0750  * @brief This group contains register bit definitions.
0751  *
0752  * @{
0753  */
0754
0755 #define GRSPWROUTER_TC_RE 0x200U
0756
0757 #define GRSPWROUTER_TC_EN 0x100U
0758
0759 #define GRSPWROUTER_TC_CF_SHIFT 6
0760 #define GRSPWROUTER_TC_CF_MASK 0xc0U
0761 #define GRSPWROUTER_TC_CF_GET( _reg ) \
0762   ( ( ( _reg ) & GRSPWROUTER_TC_CF_MASK ) >> \
0763     GRSPWROUTER_TC_CF_SHIFT )
0764 #define GRSPWROUTER_TC_CF_SET( _reg, _val ) \
0765   ( ( ( _reg ) & ~GRSPWROUTER_TC_CF_MASK ) | \
0766     ( ( ( _val ) << GRSPWROUTER_TC_CF_SHIFT ) & \
0767       GRSPWROUTER_TC_CF_MASK ) )
0768 #define GRSPWROUTER_TC_CF( _val ) \
0769   ( ( ( _val ) << GRSPWROUTER_TC_CF_SHIFT ) & \
0770     GRSPWROUTER_TC_CF_MASK )
0771
0772 #define GRSPWROUTER_TC_TC_SHIFT 0
0773 #define GRSPWROUTER_TC_TC_MASK 0x3fU
0774 #define GRSPWROUTER_TC_TC_GET( _reg ) \
0775   ( ( ( _reg ) & GRSPWROUTER_TC_TC_MASK ) >> \
0776     GRSPWROUTER_TC_TC_SHIFT )
0777 #define GRSPWROUTER_TC_TC_SET( _reg, _val ) \
0778   ( ( ( _reg ) & ~GRSPWROUTER_TC_TC_MASK ) | \
0779     ( ( ( _val ) << GRSPWROUTER_TC_TC_SHIFT ) & \
0780       GRSPWROUTER_TC_TC_MASK ) )
0781 #define GRSPWROUTER_TC_TC( _val ) \
0782   ( ( ( _val ) << GRSPWROUTER_TC_TC_SHIFT ) & \
0783     GRSPWROUTER_TC_TC_MASK )
0784
0785 /** @} */
0786
0787 /**
0788  * @defgroup RTEMSDeviceGRSPWROUTERVER Version / instance ID (VER)
0789  *
0790  * @brief This group contains register bit definitions.
0791  *
0792  * @{
0793  */
0794
0795 #define GRSPWROUTER_VER_MA_SHIFT 24
0796 #define GRSPWROUTER_VER_MA_MASK 0xff000000U
0797 #define GRSPWROUTER_VER_MA_GET( _reg ) \
0798   ( ( ( _reg ) & GRSPWROUTER_VER_MA_MASK ) >> \
0799     GRSPWROUTER_VER_MA_SHIFT )
0800 #define GRSPWROUTER_VER_MA_SET( _reg, _val ) \
0801   ( ( ( _reg ) & ~GRSPWROUTER_VER_MA_MASK ) | \
0802     ( ( ( _val ) << GRSPWROUTER_VER_MA_SHIFT ) & \
0803       GRSPWROUTER_VER_MA_MASK ) )
0804 #define GRSPWROUTER_VER_MA( _val ) \
0805   ( ( ( _val ) << GRSPWROUTER_VER_MA_SHIFT ) & \
0806     GRSPWROUTER_VER_MA_MASK )
0807
0808 #define GRSPWROUTER_VER_MI_SHIFT 16
0809 #define GRSPWROUTER_VER_MI_MASK 0xff0000U
0810 #define GRSPWROUTER_VER_MI_GET( _reg ) \
0811   ( ( ( _reg ) & GRSPWROUTER_VER_MI_MASK ) >> \
0812     GRSPWROUTER_VER_MI_SHIFT )
0813 #define GRSPWROUTER_VER_MI_SET( _reg, _val ) \
0814   ( ( ( _reg ) & ~GRSPWROUTER_VER_MI_MASK ) | \
0815     ( ( ( _val ) << GRSPWROUTER_VER_MI_SHIFT ) & \
0816       GRSPWROUTER_VER_MI_MASK ) )
0817 #define GRSPWROUTER_VER_MI( _val ) \
0818   ( ( ( _val ) << GRSPWROUTER_VER_MI_SHIFT ) & \
0819     GRSPWROUTER_VER_MI_MASK )
0820
0821 #define GRSPWROUTER_VER_PA_SHIFT 8
0822 #define GRSPWROUTER_VER_PA_MASK 0xff00U
0823 #define GRSPWROUTER_VER_PA_GET( _reg ) \
0824   ( ( ( _reg ) & GRSPWROUTER_VER_PA_MASK ) >> \
0825     GRSPWROUTER_VER_PA_SHIFT )
0826 #define GRSPWROUTER_VER_PA_SET( _reg, _val ) \
0827   ( ( ( _reg ) & ~GRSPWROUTER_VER_PA_MASK ) | \
0828     ( ( ( _val ) << GRSPWROUTER_VER_PA_SHIFT ) & \
0829       GRSPWROUTER_VER_PA_MASK ) )
0830 #define GRSPWROUTER_VER_PA( _val ) \
0831   ( ( ( _val ) << GRSPWROUTER_VER_PA_SHIFT ) & \
0832     GRSPWROUTER_VER_PA_MASK )
0833
0834 #define GRSPWROUTER_VER_ID_SHIFT 0
0835 #define GRSPWROUTER_VER_ID_MASK 0xffU
0836 #define GRSPWROUTER_VER_ID_GET( _reg ) \
0837   ( ( ( _reg ) & GRSPWROUTER_VER_ID_MASK ) >> \
0838     GRSPWROUTER_VER_ID_SHIFT )
0839 #define GRSPWROUTER_VER_ID_SET( _reg, _val ) \
0840   ( ( ( _reg ) & ~GRSPWROUTER_VER_ID_MASK ) | \
0841     ( ( ( _val ) << GRSPWROUTER_VER_ID_SHIFT ) & \
0842       GRSPWROUTER_VER_ID_MASK ) )
0843 #define GRSPWROUTER_VER_ID( _val ) \
0844   ( ( ( _val ) << GRSPWROUTER_VER_ID_SHIFT ) & \
0845     GRSPWROUTER_VER_ID_MASK )
0846
0847 /** @} */
0848
0849 /**
0850  * @defgroup RTEMSDeviceGRSPWROUTERIDIV Initialization divisor (IDIV)
0851  *
0852  * @brief This group contains register bit definitions.
0853  *
0854  * @{
0855  */
0856
0857 #define GRSPWROUTER_IDIV_ID_SHIFT 0
0858 #define GRSPWROUTER_IDIV_ID_MASK 0xffU
0859 #define GRSPWROUTER_IDIV_ID_GET( _reg ) \
0860   ( ( ( _reg ) & GRSPWROUTER_IDIV_ID_MASK ) >> \
0861     GRSPWROUTER_IDIV_ID_SHIFT )
0862 #define GRSPWROUTER_IDIV_ID_SET( _reg, _val ) \
0863   ( ( ( _reg ) & ~GRSPWROUTER_IDIV_ID_MASK ) | \
0864     ( ( ( _val ) << GRSPWROUTER_IDIV_ID_SHIFT ) & \
0865       GRSPWROUTER_IDIV_ID_MASK ) )
0866 #define GRSPWROUTER_IDIV_ID( _val ) \
0867   ( ( ( _val ) << GRSPWROUTER_IDIV_ID_SHIFT ) & \
0868     GRSPWROUTER_IDIV_ID_MASK )
0869
0870 /** @} */
0871
0872 /**
0873  * @defgroup RTEMSDeviceGRSPWROUTERCFGWE \
0874  *   Configuration port write enable (CFGWE)
0875  *
0876  * @brief This group contains register bit definitions.
0877  *
0878  * @{
0879  */
0880
0881 #define GRSPWROUTER_CFGWE_WE 0x1U
0882
0883 /** @} */
0884
0885 /**
0886  * @defgroup RTEMSDeviceGRSPWROUTERPRESCALER Timer prescaler reload (PRESCALER)
0887  *
0888  * @brief This group contains register bit definitions.
0889  *
0890  * @{
0891  */
0892
0893 #define GRSPWROUTER_PRESCALER_RL_SHIFT 0
0894 #define GRSPWROUTER_PRESCALER_RL_MASK 0xffffffffU
0895 #define GRSPWROUTER_PRESCALER_RL_GET( _reg ) \
0896   ( ( ( _reg ) & GRSPWROUTER_PRESCALER_RL_MASK ) >> \
0897     GRSPWROUTER_PRESCALER_RL_SHIFT )
0898 #define GRSPWROUTER_PRESCALER_RL_SET( _reg, _val ) \
0899   ( ( ( _reg ) & ~GRSPWROUTER_PRESCALER_RL_MASK ) | \
0900     ( ( ( _val ) << GRSPWROUTER_PRESCALER_RL_SHIFT ) & \
0901       GRSPWROUTER_PRESCALER_RL_MASK ) )
0902 #define GRSPWROUTER_PRESCALER_RL( _val ) \
0903   ( ( ( _val ) << GRSPWROUTER_PRESCALER_RL_SHIFT ) & \
0904     GRSPWROUTER_PRESCALER_RL_MASK )
0905
0906 /** @} */
0907
0908 /**
0909  * @defgroup RTEMSDeviceGRSPWROUTERIMASK Interrupt mask (IMASK)
0910  *
0911  * @brief This group contains register bit definitions.
0912  *
0913  * @{
0914  */
0915
0916 #define GRSPWROUTER_IMASK_PE 0x400U
0917
0918 #define GRSPWROUTER_IMASK_SR 0x200U
0919
0920 #define GRSPWROUTER_IMASK_RS 0x100U
0921
0922 #define GRSPWROUTER_IMASK_TT 0x80U
0923
0924 #define GRSPWROUTER_IMASK_PL 0x40U
0925
0926 #define GRSPWROUTER_IMASK_TS 0x20U
0927
0928 #define GRSPWROUTER_IMASK_AC 0x10U
0929
0930 #define GRSPWROUTER_IMASK_RE 0x8U
0931
0932 #define GRSPWROUTER_IMASK_IA 0x4U
0933
0934 #define GRSPWROUTER_IMASK_LE 0x2U
0935
0936 #define GRSPWROUTER_IMASK_ME 0x1U
0937
0938 /** @} */
0939
0940 /**
0941  * @defgroup RTEMSDeviceGRSPWROUTERIPMASK Interrupt port mask (IPMASK)
0942  *
0943  * @brief This group contains register bit definitions.
0944  *
0945  * @{
0946  */
0947
0948 #define GRSPWROUTER_IPMASK_IE_SHIFT 0
0949 #define GRSPWROUTER_IPMASK_IE_MASK 0xffffffffU
0950 #define GRSPWROUTER_IPMASK_IE_GET( _reg ) \
0951   ( ( ( _reg ) & GRSPWROUTER_IPMASK_IE_MASK ) >> \
0952     GRSPWROUTER_IPMASK_IE_SHIFT )
0953 #define GRSPWROUTER_IPMASK_IE_SET( _reg, _val ) \
0954   ( ( ( _reg ) & ~GRSPWROUTER_IPMASK_IE_MASK ) | \
0955     ( ( ( _val ) << GRSPWROUTER_IPMASK_IE_SHIFT ) & \
0956       GRSPWROUTER_IPMASK_IE_MASK ) )
0957 #define GRSPWROUTER_IPMASK_IE( _val ) \
0958   ( ( ( _val ) << GRSPWROUTER_IPMASK_IE_SHIFT ) & \
0959     GRSPWROUTER_IPMASK_IE_MASK )
0960
0961 /** @} */
0962
0963 /**
0964  * @defgroup RTEMSDeviceGRSPWROUTERPIP Port interrupt pending (PIP)
0965  *
0966  * @brief This group contains register bit definitions.
0967  *
0968  * @{
0969  */
0970
0971 #define GRSPWROUTER_PIP_IP_SHIFT 0
0972 #define GRSPWROUTER_PIP_IP_MASK 0xffffffffU
0973 #define GRSPWROUTER_PIP_IP_GET( _reg ) \
0974   ( ( ( _reg ) & GRSPWROUTER_PIP_IP_MASK ) >> \
0975     GRSPWROUTER_PIP_IP_SHIFT )
0976 #define GRSPWROUTER_PIP_IP_SET( _reg, _val ) \
0977   ( ( ( _reg ) & ~GRSPWROUTER_PIP_IP_MASK ) | \
0978     ( ( ( _val ) << GRSPWROUTER_PIP_IP_SHIFT ) & \
0979       GRSPWROUTER_PIP_IP_MASK ) )
0980 #define GRSPWROUTER_PIP_IP( _val ) \
0981   ( ( ( _val ) << GRSPWROUTER_PIP_IP_SHIFT ) & \
0982     GRSPWROUTER_PIP_IP_MASK )
0983
0984 /** @} */
0985
0986 /**
0987  * @defgroup RTEMSDeviceGRSPWROUTERICODEGEN \
0988  *   Interrupt code generation (ICODEGEN)
0989  *
0990  * @brief This group contains register bit definitions.
0991  *
0992  * @{
0993  */
0994
0995 #define GRSPWROUTER_ICODEGEN_HI 0x200000U
0996
0997 #define GRSPWROUTER_ICODEGEN_UA 0x100000U
0998
0999 #define GRSPWROUTER_ICODEGEN_AH 0x80000U
1000
1001 #define GRSPWROUTER_ICODEGEN_IT 0x40000U
1002
1003 #define GRSPWROUTER_ICODEGEN_TE 0x1U
1004
1005 #define GRSPWROUTER_ICODEGEN_EN 0x20000U
1006
1007 #define GRSPWROUTER_ICODEGEN_IN_SHIFT 6
1008 #define GRSPWROUTER_ICODEGEN_IN_MASK 0xffc0U
1009 #define GRSPWROUTER_ICODEGEN_IN_GET( _reg ) \
1010   ( ( ( _reg ) & GRSPWROUTER_ICODEGEN_IN_MASK ) >> \
1011     GRSPWROUTER_ICODEGEN_IN_SHIFT )
1012 #define GRSPWROUTER_ICODEGEN_IN_SET( _reg, _val ) \
1013   ( ( ( _reg ) & ~GRSPWROUTER_ICODEGEN_IN_MASK ) | \
1014     ( ( ( _val ) << GRSPWROUTER_ICODEGEN_IN_SHIFT ) & \
1015       GRSPWROUTER_ICODEGEN_IN_MASK ) )
1016 #define GRSPWROUTER_ICODEGEN_IN( _val ) \
1017   ( ( ( _val ) << GRSPWROUTER_ICODEGEN_IN_SHIFT ) & \
1018     GRSPWROUTER_ICODEGEN_IN_MASK )
1019
1020 /** @} */
1021
1022 /**
1023  * @defgroup RTEMSDeviceGRSPWROUTERISR0 \
1024  *   Interrupt code distribution ISR register, interrupt 0-31 (ISR0)
1025  *
1026  * @brief This group contains register bit definitions.
1027  *
1028  * @{
1029  */
1030
1031 #define GRSPWROUTER_ISR0_IB_SHIFT 0
1032 #define GRSPWROUTER_ISR0_IB_MASK 0xffffffffU
1033 #define GRSPWROUTER_ISR0_IB_GET( _reg ) \
1034   ( ( ( _reg ) & GRSPWROUTER_ISR0_IB_MASK ) >> \
1035     GRSPWROUTER_ISR0_IB_SHIFT )
1036 #define GRSPWROUTER_ISR0_IB_SET( _reg, _val ) \
1037   ( ( ( _reg ) & ~GRSPWROUTER_ISR0_IB_MASK ) | \
1038     ( ( ( _val ) << GRSPWROUTER_ISR0_IB_SHIFT ) & \
1039       GRSPWROUTER_ISR0_IB_MASK ) )
1040 #define GRSPWROUTER_ISR0_IB( _val ) \
1041   ( ( ( _val ) << GRSPWROUTER_ISR0_IB_SHIFT ) & \
1042     GRSPWROUTER_ISR0_IB_MASK )
1043
1044 /** @} */
1045
1046 /**
1047  * @defgroup RTEMSDeviceGRSPWROUTERISR1 \
1048  *   Interrupt code distribution ISR register, interrupt 32-63 (ISR1)
1049  *
1050  * @brief This group contains register bit definitions.
1051  *
1052  * @{
1053  */
1054
1055 #define GRSPWROUTER_ISR1_IB_SHIFT 0
1056 #define GRSPWROUTER_ISR1_IB_MASK 0xffffffffU
1057 #define GRSPWROUTER_ISR1_IB_GET( _reg ) \
1058   ( ( ( _reg ) & GRSPWROUTER_ISR1_IB_MASK ) >> \
1059     GRSPWROUTER_ISR1_IB_SHIFT )
1060 #define GRSPWROUTER_ISR1_IB_SET( _reg, _val ) \
1061   ( ( ( _reg ) & ~GRSPWROUTER_ISR1_IB_MASK ) | \
1062     ( ( ( _val ) << GRSPWROUTER_ISR1_IB_SHIFT ) & \
1063       GRSPWROUTER_ISR1_IB_MASK ) )
1064 #define GRSPWROUTER_ISR1_IB( _val ) \
1065   ( ( ( _val ) << GRSPWROUTER_ISR1_IB_SHIFT ) & \
1066     GRSPWROUTER_ISR1_IB_MASK )
1067
1068 /** @} */
1069
1070 /**
1071  * @defgroup RTEMSDeviceGRSPWROUTERISRTIMER \
1072  *   Interrupt code distribution ISR timer reload (ISRTIMER)
1073  *
1074  * @brief This group contains register bit definitions.
1075  *
1076  * @{
1077  */
1078
1079 #define GRSPWROUTER_ISRTIMER_RL_SHIFT 0
1080 #define GRSPWROUTER_ISRTIMER_RL_MASK 0xffffffffU
1081 #define GRSPWROUTER_ISRTIMER_RL_GET( _reg ) \
1082   ( ( ( _reg ) & GRSPWROUTER_ISRTIMER_RL_MASK ) >> \
1083     GRSPWROUTER_ISRTIMER_RL_SHIFT )
1084 #define GRSPWROUTER_ISRTIMER_RL_SET( _reg, _val ) \
1085   ( ( ( _reg ) & ~GRSPWROUTER_ISRTIMER_RL_MASK ) | \
1086     ( ( ( _val ) << GRSPWROUTER_ISRTIMER_RL_SHIFT ) & \
1087       GRSPWROUTER_ISRTIMER_RL_MASK ) )
1088 #define GRSPWROUTER_ISRTIMER_RL( _val ) \
1089   ( ( ( _val ) << GRSPWROUTER_ISRTIMER_RL_SHIFT ) & \
1090     GRSPWROUTER_ISRTIMER_RL_MASK )
1091
1092 /** @} */
1093
1094 /**
1095  * @defgroup RTEMSDeviceGRSPWROUTERAITIMER \
1096  *   Interrupt code distribution ACK-to-INT timer reload (AITIMER)
1097  *
1098  * @brief This group contains register bit definitions.
1099  *
1100  * @{
1101  */
1102
1103 #define GRSPWROUTER_AITIMER_RL_SHIFT 0
1104 #define GRSPWROUTER_AITIMER_RL_MASK 0xffffffffU
1105 #define GRSPWROUTER_AITIMER_RL_GET( _reg ) \
1106   ( ( ( _reg ) & GRSPWROUTER_AITIMER_RL_MASK ) >> \
1107     GRSPWROUTER_AITIMER_RL_SHIFT )
1108 #define GRSPWROUTER_AITIMER_RL_SET( _reg, _val ) \
1109   ( ( ( _reg ) & ~GRSPWROUTER_AITIMER_RL_MASK ) | \
1110     ( ( ( _val ) << GRSPWROUTER_AITIMER_RL_SHIFT ) & \
1111       GRSPWROUTER_AITIMER_RL_MASK ) )
1112 #define GRSPWROUTER_AITIMER_RL( _val ) \
1113   ( ( ( _val ) << GRSPWROUTER_AITIMER_RL_SHIFT ) & \
1114     GRSPWROUTER_AITIMER_RL_MASK )
1115
1116 /** @} */
1117
1118 /**
1119  * @defgroup RTEMSDeviceGRSPWROUTERISRCTIMER \
1120  *   Interrupt code distribution ISR change timer reload (ISRCTIMER)
1121  *
1122  * @brief This group contains register bit definitions.
1123  *
1124  * @{
1125  */
1126
1127 #define GRSPWROUTER_ISRCTIMER_RL_SHIFT 0
1128 #define GRSPWROUTER_ISRCTIMER_RL_MASK 0x1fU
1129 #define GRSPWROUTER_ISRCTIMER_RL_GET( _reg ) \
1130   ( ( ( _reg ) & GRSPWROUTER_ISRCTIMER_RL_MASK ) >> \
1131     GRSPWROUTER_ISRCTIMER_RL_SHIFT )
1132 #define GRSPWROUTER_ISRCTIMER_RL_SET( _reg, _val ) \
1133   ( ( ( _reg ) & ~GRSPWROUTER_ISRCTIMER_RL_MASK ) | \
1134     ( ( ( _val ) << GRSPWROUTER_ISRCTIMER_RL_SHIFT ) & \
1135       GRSPWROUTER_ISRCTIMER_RL_MASK ) )
1136 #define GRSPWROUTER_ISRCTIMER_RL( _val ) \
1137   ( ( ( _val ) << GRSPWROUTER_ISRCTIMER_RL_SHIFT ) & \
1138     GRSPWROUTER_ISRCTIMER_RL_MASK )
1139
1140 /** @} */
1141
1142 /**
1143  * @defgroup RTEMSDeviceGRSPWROUTERLRUNSTAT Link running status (LRUNSTAT)
1144  *
1145  * @brief This group contains register bit definitions.
1146  *
1147  * @{
1148  */
1149
1150 #define GRSPWROUTER_LRUNSTAT_LR_SHIFT 1
1151 #define GRSPWROUTER_LRUNSTAT_LR_MASK 0xfffffffeU
1152 #define GRSPWROUTER_LRUNSTAT_LR_GET( _reg ) \
1153   ( ( ( _reg ) & GRSPWROUTER_LRUNSTAT_LR_MASK ) >> \
1154     GRSPWROUTER_LRUNSTAT_LR_SHIFT )
1155 #define GRSPWROUTER_LRUNSTAT_LR_SET( _reg, _val ) \
1156   ( ( ( _reg ) & ~GRSPWROUTER_LRUNSTAT_LR_MASK ) | \
1157     ( ( ( _val ) << GRSPWROUTER_LRUNSTAT_LR_SHIFT ) & \
1158       GRSPWROUTER_LRUNSTAT_LR_MASK ) )
1159 #define GRSPWROUTER_LRUNSTAT_LR( _val ) \
1160   ( ( ( _val ) << GRSPWROUTER_LRUNSTAT_LR_SHIFT ) & \
1161     GRSPWROUTER_LRUNSTAT_LR_MASK )
1162
1163 #define GRSPWROUTER_LRUNSTAT_R 0x1U
1164
1165 /** @} */
1166
1167 /**
1168  * @defgroup RTEMSDeviceGRSPWROUTERCAP Capability (CAP)
1169  *
1170  * @brief This group contains register bit definitions.
1171  *
1172  * @{
1173  */
1174
1175 #define GRSPWROUTER_CAP_AF_SHIFT 24
1176 #define GRSPWROUTER_CAP_AF_MASK 0x3000000U
1177 #define GRSPWROUTER_CAP_AF_GET( _reg ) \
1178   ( ( ( _reg ) & GRSPWROUTER_CAP_AF_MASK ) >> \
1179     GRSPWROUTER_CAP_AF_SHIFT )
1180 #define GRSPWROUTER_CAP_AF_SET( _reg, _val ) \
1181   ( ( ( _reg ) & ~GRSPWROUTER_CAP_AF_MASK ) | \
1182     ( ( ( _val ) << GRSPWROUTER_CAP_AF_SHIFT ) & \
1183       GRSPWROUTER_CAP_AF_MASK ) )
1184 #define GRSPWROUTER_CAP_AF( _val ) \
1185   ( ( ( _val ) << GRSPWROUTER_CAP_AF_SHIFT ) & \
1186     GRSPWROUTER_CAP_AF_MASK )
1187
1188 #define GRSPWROUTER_CAP_R 0x800000U
1189
1190 #define GRSPWROUTER_CAP_PF_SHIFT 20
1191 #define GRSPWROUTER_CAP_PF_MASK 0x700000U
1192 #define GRSPWROUTER_CAP_PF_GET( _reg ) \
1193   ( ( ( _reg ) & GRSPWROUTER_CAP_PF_MASK ) >> \
1194     GRSPWROUTER_CAP_PF_SHIFT )
1195 #define GRSPWROUTER_CAP_PF_SET( _reg, _val ) \
1196   ( ( ( _reg ) & ~GRSPWROUTER_CAP_PF_MASK ) | \
1197     ( ( ( _val ) << GRSPWROUTER_CAP_PF_SHIFT ) & \
1198       GRSPWROUTER_CAP_PF_MASK ) )
1199 #define GRSPWROUTER_CAP_PF( _val ) \
1200   ( ( ( _val ) << GRSPWROUTER_CAP_PF_SHIFT ) & \
1201     GRSPWROUTER_CAP_PF_MASK )
1202
1203 #define GRSPWROUTER_CAP_R 0x80000U
1204
1205 #define GRSPWROUTER_CAP_RM_SHIFT 16
1206 #define GRSPWROUTER_CAP_RM_MASK 0x70000U
1207 #define GRSPWROUTER_CAP_RM_GET( _reg ) \
1208   ( ( ( _reg ) & GRSPWROUTER_CAP_RM_MASK ) >> \
1209     GRSPWROUTER_CAP_RM_SHIFT )
1210 #define GRSPWROUTER_CAP_RM_SET( _reg, _val ) \
1211   ( ( ( _reg ) & ~GRSPWROUTER_CAP_RM_MASK ) | \
1212     ( ( ( _val ) << GRSPWROUTER_CAP_RM_SHIFT ) & \
1213       GRSPWROUTER_CAP_RM_MASK ) )
1214 #define GRSPWROUTER_CAP_RM( _val ) \
1215   ( ( ( _val ) << GRSPWROUTER_CAP_RM_SHIFT ) & \
1216     GRSPWROUTER_CAP_RM_MASK )
1217
1218 #define GRSPWROUTER_CAP_R 0x8000U
1219
1220 #define GRSPWROUTER_CAP_AA 0x4000U
1221
1222 #define GRSPWROUTER_CAP_AX 0x2000U
1223
1224 #define GRSPWROUTER_CAP_DP 0x1000U
1225
1226 #define GRSPWROUTER_CAP_ID 0x800U
1227
1228 #define GRSPWROUTER_CAP_SD 0x400U
1229
1230 #define GRSPWROUTER_CAP_PC_SHIFT 5
1231 #define GRSPWROUTER_CAP_PC_MASK 0x3e0U
1232 #define GRSPWROUTER_CAP_PC_GET( _reg ) \
1233   ( ( ( _reg ) & GRSPWROUTER_CAP_PC_MASK ) >> \
1234     GRSPWROUTER_CAP_PC_SHIFT )
1235 #define GRSPWROUTER_CAP_PC_SET( _reg, _val ) \
1236   ( ( ( _reg ) & ~GRSPWROUTER_CAP_PC_MASK ) | \
1237     ( ( ( _val ) << GRSPWROUTER_CAP_PC_SHIFT ) & \
1238       GRSPWROUTER_CAP_PC_MASK ) )
1239 #define GRSPWROUTER_CAP_PC( _val ) \
1240   ( ( ( _val ) << GRSPWROUTER_CAP_PC_SHIFT ) & \
1241     GRSPWROUTER_CAP_PC_MASK )
1242
1243 #define GRSPWROUTER_CAP_CC_SHIFT 0
1244 #define GRSPWROUTER_CAP_CC_MASK 0x1fU
1245 #define GRSPWROUTER_CAP_CC_GET( _reg ) \
1246   ( ( ( _reg ) & GRSPWROUTER_CAP_CC_MASK ) >> \
1247     GRSPWROUTER_CAP_CC_SHIFT )
1248 #define GRSPWROUTER_CAP_CC_SET( _reg, _val ) \
1249   ( ( ( _reg ) & ~GRSPWROUTER_CAP_CC_MASK ) | \
1250     ( ( ( _val ) << GRSPWROUTER_CAP_CC_SHIFT ) & \
1251       GRSPWROUTER_CAP_CC_MASK ) )
1252 #define GRSPWROUTER_CAP_CC( _val ) \
1253   ( ( ( _val ) << GRSPWROUTER_CAP_CC_SHIFT ) & \
1254     GRSPWROUTER_CAP_CC_MASK )
1255
1256 /** @} */
1257
1258 /**
1259  * @defgroup RTEMSDeviceGRSPWROUTERPNPVEND \
1260  *   SpaceWire Plug-and-Play - Device Vendor and Product ID (PNPVEND)
1261  *
1262  * @brief This group contains register bit definitions.
1263  *
1264  * @{
1265  */
1266
1267 #define GRSPWROUTER_PNPVEND_VI_SHIFT 16
1268 #define GRSPWROUTER_PNPVEND_VI_MASK 0xffff0000U
1269 #define GRSPWROUTER_PNPVEND_VI_GET( _reg ) \
1270   ( ( ( _reg ) & GRSPWROUTER_PNPVEND_VI_MASK ) >> \
1271     GRSPWROUTER_PNPVEND_VI_SHIFT )
1272 #define GRSPWROUTER_PNPVEND_VI_SET( _reg, _val ) \
1273   ( ( ( _reg ) & ~GRSPWROUTER_PNPVEND_VI_MASK ) | \
1274     ( ( ( _val ) << GRSPWROUTER_PNPVEND_VI_SHIFT ) & \
1275       GRSPWROUTER_PNPVEND_VI_MASK ) )
1276 #define GRSPWROUTER_PNPVEND_VI( _val ) \
1277   ( ( ( _val ) << GRSPWROUTER_PNPVEND_VI_SHIFT ) & \
1278     GRSPWROUTER_PNPVEND_VI_MASK )
1279
1280 #define GRSPWROUTER_PNPVEND_PI_SHIFT 0
1281 #define GRSPWROUTER_PNPVEND_PI_MASK 0x3ffffffU
1282 #define GRSPWROUTER_PNPVEND_PI_GET( _reg ) \
1283   ( ( ( _reg ) & GRSPWROUTER_PNPVEND_PI_MASK ) >> \
1284     GRSPWROUTER_PNPVEND_PI_SHIFT )
1285 #define GRSPWROUTER_PNPVEND_PI_SET( _reg, _val ) \
1286   ( ( ( _reg ) & ~GRSPWROUTER_PNPVEND_PI_MASK ) | \
1287     ( ( ( _val ) << GRSPWROUTER_PNPVEND_PI_SHIFT ) & \
1288       GRSPWROUTER_PNPVEND_PI_MASK ) )
1289 #define GRSPWROUTER_PNPVEND_PI( _val ) \
1290   ( ( ( _val ) << GRSPWROUTER_PNPVEND_PI_SHIFT ) & \
1291     GRSPWROUTER_PNPVEND_PI_MASK )
1292
1293 /** @} */
1294
1295 /**
1296  * @defgroup RTEMSDeviceGRSPWROUTERPNPUVEND \
1297  *   SpaceWire Plug-and-Play - Unit Vendor and Product ID (PNPUVEND)
1298  *
1299  * @brief This group contains register bit definitions.
1300  *
1301  * @{
1302  */
1303
1304 #define GRSPWROUTER_PNPUVEND_VI_SHIFT 16
1305 #define GRSPWROUTER_PNPUVEND_VI_MASK 0xffff0000U
1306 #define GRSPWROUTER_PNPUVEND_VI_GET( _reg ) \
1307   ( ( ( _reg ) & GRSPWROUTER_PNPUVEND_VI_MASK ) >> \
1308     GRSPWROUTER_PNPUVEND_VI_SHIFT )
1309 #define GRSPWROUTER_PNPUVEND_VI_SET( _reg, _val ) \
1310   ( ( ( _reg ) & ~GRSPWROUTER_PNPUVEND_VI_MASK ) | \
1311     ( ( ( _val ) << GRSPWROUTER_PNPUVEND_VI_SHIFT ) & \
1312       GRSPWROUTER_PNPUVEND_VI_MASK ) )
1313 #define GRSPWROUTER_PNPUVEND_VI( _val ) \
1314   ( ( ( _val ) << GRSPWROUTER_PNPUVEND_VI_SHIFT ) & \
1315     GRSPWROUTER_PNPUVEND_VI_MASK )
1316
1317 #define GRSPWROUTER_PNPUVEND_PI_SHIFT 0
1318 #define GRSPWROUTER_PNPUVEND_PI_MASK 0x3ffffffU
1319 #define GRSPWROUTER_PNPUVEND_PI_GET( _reg ) \
1320   ( ( ( _reg ) & GRSPWROUTER_PNPUVEND_PI_MASK ) >> \
1321     GRSPWROUTER_PNPUVEND_PI_SHIFT )
1322 #define GRSPWROUTER_PNPUVEND_PI_SET( _reg, _val ) \
1323   ( ( ( _reg ) & ~GRSPWROUTER_PNPUVEND_PI_MASK ) | \
1324     ( ( ( _val ) << GRSPWROUTER_PNPUVEND_PI_SHIFT ) & \
1325       GRSPWROUTER_PNPUVEND_PI_MASK ) )
1326 #define GRSPWROUTER_PNPUVEND_PI( _val ) \
1327   ( ( ( _val ) << GRSPWROUTER_PNPUVEND_PI_SHIFT ) & \
1328     GRSPWROUTER_PNPUVEND_PI_MASK )
1329
1330 /** @} */
1331
1332 /**
1333  * @defgroup RTEMSDeviceGRSPWROUTERPNPUSN \
1334  *   SpaceWire Plug-and-Play - Unit Serial Number (PNPUSN)
1335  *
1336  * @brief This group contains register bit definitions.
1337  *
1338  * @{
1339  */
1340
1341 #define GRSPWROUTER_PNPUSN_SN_SHIFT 0
1342 #define GRSPWROUTER_PNPUSN_SN_MASK 0xffffffffU
1343 #define GRSPWROUTER_PNPUSN_SN_GET( _reg ) \
1344   ( ( ( _reg ) & GRSPWROUTER_PNPUSN_SN_MASK ) >> \
1345     GRSPWROUTER_PNPUSN_SN_SHIFT )
1346 #define GRSPWROUTER_PNPUSN_SN_SET( _reg, _val ) \
1347   ( ( ( _reg ) & ~GRSPWROUTER_PNPUSN_SN_MASK ) | \
1348     ( ( ( _val ) << GRSPWROUTER_PNPUSN_SN_SHIFT ) & \
1349       GRSPWROUTER_PNPUSN_SN_MASK ) )
1350 #define GRSPWROUTER_PNPUSN_SN( _val ) \
1351   ( ( ( _val ) << GRSPWROUTER_PNPUSN_SN_SHIFT ) & \
1352     GRSPWROUTER_PNPUSN_SN_MASK )
1353
1354 /** @} */
1355
1356 /**
1357  * @defgroup RTEMSDeviceGRSPWROUTERPNPNETDISC \
1358  *   SpaceWire Plug-and-Play - Port network discovery enable (PNPNETDISC)
1359  *
1360  * @brief This group contains register bit definitions.
1361  *
1362  * @{
1363  */
1364
1365 #define GRSPWROUTER_PNPNETDISC_ND_SHIFT 0
1366 #define GRSPWROUTER_PNPNETDISC_ND_MASK 0xffffffffU
1367 #define GRSPWROUTER_PNPNETDISC_ND_GET( _reg ) \
1368   ( ( ( _reg ) & GRSPWROUTER_PNPNETDISC_ND_MASK ) >> \
1369     GRSPWROUTER_PNPNETDISC_ND_SHIFT )
1370 #define GRSPWROUTER_PNPNETDISC_ND_SET( _reg, _val ) \
1371   ( ( ( _reg ) & ~GRSPWROUTER_PNPNETDISC_ND_MASK ) | \
1372     ( ( ( _val ) << GRSPWROUTER_PNPNETDISC_ND_SHIFT ) & \
1373       GRSPWROUTER_PNPNETDISC_ND_MASK ) )
1374 #define GRSPWROUTER_PNPNETDISC_ND( _val ) \
1375   ( ( ( _val ) << GRSPWROUTER_PNPNETDISC_ND_SHIFT ) & \
1376     GRSPWROUTER_PNPNETDISC_ND_MASK )
1377
1378 /** @} */
1379
1380 /**
1381  * @defgroup RTEMSDeviceGRSPWROUTERMAXPLEN \
1382  *   Maximum packet length, ports > 0 (MAXPLEN)
1383  *
1384  * @brief This group contains register bit definitions.
1385  *
1386  * @{
1387  */
1388
1389 #define GRSPWROUTER_MAXPLEN_ML_SHIFT 0
1390 #define GRSPWROUTER_MAXPLEN_ML_MASK 0x1ffffffU
1391 #define GRSPWROUTER_MAXPLEN_ML_GET( _reg ) \
1392   ( ( ( _reg ) & GRSPWROUTER_MAXPLEN_ML_MASK ) >> \
1393     GRSPWROUTER_MAXPLEN_ML_SHIFT )
1394 #define GRSPWROUTER_MAXPLEN_ML_SET( _reg, _val ) \
1395   ( ( ( _reg ) & ~GRSPWROUTER_MAXPLEN_ML_MASK ) | \
1396     ( ( ( _val ) << GRSPWROUTER_MAXPLEN_ML_SHIFT ) & \
1397       GRSPWROUTER_MAXPLEN_ML_MASK ) )
1398 #define GRSPWROUTER_MAXPLEN_ML( _val ) \
1399   ( ( ( _val ) << GRSPWROUTER_MAXPLEN_ML_SHIFT ) & \
1400     GRSPWROUTER_MAXPLEN_ML_MASK )
1401
1402 /** @} */
1403
1404 /**
1405  * @defgroup RTEMSDeviceGRSPWROUTERCREDCNT \
1406  *   Credit counter, SpaceWire ports (CREDCNT)
1407  *
1408  * @brief This group contains register bit definitions.
1409  *
1410  * @{
1411  */
1412
1413 #define GRSPWROUTER_CREDCNT_OC_SHIFT 6
1414 #define GRSPWROUTER_CREDCNT_OC_MASK 0xfc0U
1415 #define GRSPWROUTER_CREDCNT_OC_GET( _reg ) \
1416   ( ( ( _reg ) & GRSPWROUTER_CREDCNT_OC_MASK ) >> \
1417     GRSPWROUTER_CREDCNT_OC_SHIFT )
1418 #define GRSPWROUTER_CREDCNT_OC_SET( _reg, _val ) \
1419   ( ( ( _reg ) & ~GRSPWROUTER_CREDCNT_OC_MASK ) | \
1420     ( ( ( _val ) << GRSPWROUTER_CREDCNT_OC_SHIFT ) & \
1421       GRSPWROUTER_CREDCNT_OC_MASK ) )
1422 #define GRSPWROUTER_CREDCNT_OC( _val ) \
1423   ( ( ( _val ) << GRSPWROUTER_CREDCNT_OC_SHIFT ) & \
1424     GRSPWROUTER_CREDCNT_OC_MASK )
1425
1426 #define GRSPWROUTER_CREDCNT_IC_SHIFT 0
1427 #define GRSPWROUTER_CREDCNT_IC_MASK 0x3fU
1428 #define GRSPWROUTER_CREDCNT_IC_GET( _reg ) \
1429   ( ( ( _reg ) & GRSPWROUTER_CREDCNT_IC_MASK ) >> \
1430     GRSPWROUTER_CREDCNT_IC_SHIFT )
1431 #define GRSPWROUTER_CREDCNT_IC_SET( _reg, _val ) \
1432   ( ( ( _reg ) & ~GRSPWROUTER_CREDCNT_IC_MASK ) | \
1433     ( ( ( _val ) << GRSPWROUTER_CREDCNT_IC_SHIFT ) & \
1434       GRSPWROUTER_CREDCNT_IC_MASK ) )
1435 #define GRSPWROUTER_CREDCNT_IC( _val ) \
1436   ( ( ( _val ) << GRSPWROUTER_CREDCNT_IC_SHIFT ) & \
1437     GRSPWROUTER_CREDCNT_IC_MASK )
1438
1439 /** @} */
1440
1441 /**
1442  * @defgroup RTEMSDeviceGRSPWROUTERGPO \
1443  *   General purpose out, bits 0-31, 32-63, 64-95, and 96-127 (GPO)
1444  *
1445  * @brief This group contains register bit definitions.
1446  *
1447  * @{
1448  */
1449
1450 #define GRSPWROUTER_GPO_GPO_SHIFT 0
1451 #define GRSPWROUTER_GPO_GPO_MASK 0xffffffffU
1452 #define GRSPWROUTER_GPO_GPO_GET( _reg ) \
1453   ( ( ( _reg ) & GRSPWROUTER_GPO_GPO_MASK ) >> \
1454     GRSPWROUTER_GPO_GPO_SHIFT )
1455 #define GRSPWROUTER_GPO_GPO_SET( _reg, _val ) \
1456   ( ( ( _reg ) & ~GRSPWROUTER_GPO_GPO_MASK ) | \
1457     ( ( ( _val ) << GRSPWROUTER_GPO_GPO_SHIFT ) & \
1458       GRSPWROUTER_GPO_GPO_MASK ) )
1459 #define GRSPWROUTER_GPO_GPO( _val ) \
1460   ( ( ( _val ) << GRSPWROUTER_GPO_GPO_SHIFT ) & \
1461     GRSPWROUTER_GPO_GPO_MASK )
1462
1463 /** @} */
1464
1465 /**
1466  * @defgroup RTEMSDeviceGRSPWROUTERGPI \
1467  *   General purpose in, bits 0-31, 32-63, 64-95, and 96-127 (GPI)
1468  *
1469  * @brief This group contains register bit definitions.
1470  *
1471  * @{
1472  */
1473
1474 #define GRSPWROUTER_GPI_GPI_SHIFT 0
1475 #define GRSPWROUTER_GPI_GPI_MASK 0xffffffffU
1476 #define GRSPWROUTER_GPI_GPI_GET( _reg ) \
1477   ( ( ( _reg ) & GRSPWROUTER_GPI_GPI_MASK ) >> \
1478     GRSPWROUTER_GPI_GPI_SHIFT )
1479 #define GRSPWROUTER_GPI_GPI_SET( _reg, _val ) \
1480   ( ( ( _reg ) & ~GRSPWROUTER_GPI_GPI_MASK ) | \
1481     ( ( ( _val ) << GRSPWROUTER_GPI_GPI_SHIFT ) & \
1482       GRSPWROUTER_GPI_GPI_MASK ) )
1483 #define GRSPWROUTER_GPI_GPI( _val ) \
1484   ( ( ( _val ) << GRSPWROUTER_GPI_GPI_SHIFT ) & \
1485     GRSPWROUTER_GPI_GPI_MASK )
1486
1487 /** @} */
1488
1489 /**
1490  * @defgroup RTEMSDeviceGRSPWROUTERRTCOMB \
1491  *   Routing table, combined port mapping and address control, addresses 1-255 (RTCOMB)
1492  *
1493  * @brief This group contains register bit definitions.
1494  *
1495  * @{
1496  */
1497
1498 #define GRSPWROUTER_RTCOMB_SR 0x80000000U
1499
1500 #define GRSPWROUTER_RTCOMB_EN 0x40000000U
1501
1502 #define GRSPWROUTER_RTCOMB_PR 0x20000000U
1503
1504 #define GRSPWROUTER_RTCOMB_HD 0x10000000U
1505
1506 #define GRSPWROUTER_RTCOMB_PE_SHIFT 1
1507 #define GRSPWROUTER_RTCOMB_PE_MASK 0xffffffeU
1508 #define GRSPWROUTER_RTCOMB_PE_GET( _reg ) \
1509   ( ( ( _reg ) & GRSPWROUTER_RTCOMB_PE_MASK ) >> \
1510     GRSPWROUTER_RTCOMB_PE_SHIFT )
1511 #define GRSPWROUTER_RTCOMB_PE_SET( _reg, _val ) \
1512   ( ( ( _reg ) & ~GRSPWROUTER_RTCOMB_PE_MASK ) | \
1513     ( ( ( _val ) << GRSPWROUTER_RTCOMB_PE_SHIFT ) & \
1514       GRSPWROUTER_RTCOMB_PE_MASK ) )
1515 #define GRSPWROUTER_RTCOMB_PE( _val ) \
1516   ( ( ( _val ) << GRSPWROUTER_RTCOMB_PE_SHIFT ) & \
1517     GRSPWROUTER_RTCOMB_PE_MASK )
1518
1519 #define GRSPWROUTER_RTCOMB_PD 0x1U
1520
1521 /** @} */
1522
1523 /**
1524  * @defgroup RTEMSDeviceGRSPWROUTERAPBAREA APB address area (APBAREA)
1525  *
1526  * @brief This group contains register bit definitions.
1527  *
1528  * @{
1529  */
1530
1531 #define GRSPWROUTER_APBAREA_APB_SHIFT 0
1532 #define GRSPWROUTER_APBAREA_APB_MASK 0xffffffffU
1533 #define GRSPWROUTER_APBAREA_APB_GET( _reg ) \
1534   ( ( ( _reg ) & GRSPWROUTER_APBAREA_APB_MASK ) >> \
1535     GRSPWROUTER_APBAREA_APB_SHIFT )
1536 #define GRSPWROUTER_APBAREA_APB_SET( _reg, _val ) \
1537   ( ( ( _reg ) & ~GRSPWROUTER_APBAREA_APB_MASK ) | \
1538     ( ( ( _val ) << GRSPWROUTER_APBAREA_APB_SHIFT ) & \
1539       GRSPWROUTER_APBAREA_APB_MASK ) )
1540 #define GRSPWROUTER_APBAREA_APB( _val ) \
1541   ( ( ( _val ) << GRSPWROUTER_APBAREA_APB_SHIFT ) & \
1542     GRSPWROUTER_APBAREA_APB_MASK )
1543
1544 /** @} */
1545
1546 /**
1547  * @brief This structure defines the SpaceWire Router register block memory
1548  *   map.
1549  */
1550 typedef struct grspwrouter {
1551   uint32_t reserved_0_4;
1552
1553   /**
1554    * @brief See @ref RTEMSDeviceGRSPWROUTERRTPMAP.
1555    */
1556   uint32_t rtpmap[ 255 ];
1557
1558   uint32_t reserved_400_404;
1559
1560   /**
1561    * @brief See @ref RTEMSDeviceGRSPWROUTERRTACTRL.
1562    */
1563   uint32_t rtactrl[ 255 ];
1564
1565   /**
1566    * @brief See @ref RTEMSDeviceGRSPWROUTERPCTRLCFG.
1567    */
1568   uint32_t pctrlcfg;
1569
1570   /**
1571    * @brief See @ref RTEMSDeviceGRSPWROUTERPCTRL.
1572    */
1573   uint32_t pctrl[ 31 ];
1574
1575   /**
1576    * @brief See @ref RTEMSDeviceGRSPWROUTERPSTSCFG.
1577    */
1578   uint32_t pstscfg;
1579
1580   /**
1581    * @brief See @ref RTEMSDeviceGRSPWROUTERPSTS.
1582    */
1583   uint32_t psts[ 31 ];
1584
1585   /**
1586    * @brief See @ref RTEMSDeviceGRSPWROUTERPTIMER.
1587    */
1588   uint32_t ptimer[ 32 ];
1589
1590   /**
1591    * @brief See @ref RTEMSDeviceGRSPWROUTERPCTRL2CFG.
1592    */
1593   uint32_t pctrl2cfg;
1594
1595   /**
1596    * @brief See @ref RTEMSDeviceGRSPWROUTERPCTRL2.
1597    */
1598   uint32_t pctrl2[ 31 ];
1599
1600   /**
1601    * @brief See @ref RTEMSDeviceGRSPWROUTERRTRCFG.
1602    */
1603   uint32_t rtrcfg;
1604
1605   /**
1606    * @brief See @ref RTEMSDeviceGRSPWROUTERTC.
1607    */
1608   uint32_t tc;
1609
1610   /**
1611    * @brief See @ref RTEMSDeviceGRSPWROUTERVER.
1612    */
1613   uint32_t ver;
1614
1615   /**
1616    * @brief See @ref RTEMSDeviceGRSPWROUTERIDIV.
1617    */
1618   uint32_t idiv;
1619
1620   /**
1621    * @brief See @ref RTEMSDeviceGRSPWROUTERCFGWE.
1622    */
1623   uint32_t cfgwe;
1624
1625   /**
1626    * @brief See @ref RTEMSDeviceGRSPWROUTERPRESCALER.
1627    */
1628   uint32_t prescaler;
1629
1630   /**
1631    * @brief See @ref RTEMSDeviceGRSPWROUTERIMASK.
1632    */
1633   uint32_t imask;
1634
1635   /**
1636    * @brief See @ref RTEMSDeviceGRSPWROUTERIPMASK.
1637    */
1638   uint32_t ipmask;
1639
1640   /**
1641    * @brief See @ref RTEMSDeviceGRSPWROUTERPIP.
1642    */
1643   uint32_t pip;
1644
1645   /**
1646    * @brief See @ref RTEMSDeviceGRSPWROUTERICODEGEN.
1647    */
1648   uint32_t icodegen;
1649
1650   /**
1651    * @brief See @ref RTEMSDeviceGRSPWROUTERISR0.
1652    */
1653   uint32_t isr0;
1654
1655   /**
1656    * @brief See @ref RTEMSDeviceGRSPWROUTERISR1.
1657    */
1658   uint32_t isr1;
1659
1660   /**
1661    * @brief See @ref RTEMSDeviceGRSPWROUTERISRTIMER.
1662    */
1663   uint32_t isrtimer;
1664
1665   /**
1666    * @brief See @ref RTEMSDeviceGRSPWROUTERAITIMER.
1667    */
1668   uint32_t aitimer;
1669
1670   /**
1671    * @brief See @ref RTEMSDeviceGRSPWROUTERISRCTIMER.
1672    */
1673   uint32_t isrctimer;
1674
1675   uint32_t reserved_a3c_a40;
1676
1677   /**
1678    * @brief See @ref RTEMSDeviceGRSPWROUTERLRUNSTAT.
1679    */
1680   uint32_t lrunstat;
1681
1682   /**
1683    * @brief See @ref RTEMSDeviceGRSPWROUTERCAP.
1684    */
1685   uint32_t cap;
1686
1687   uint32_t reserved_a48_a50[ 2 ];
1688
1689   /**
1690    * @brief See @ref RTEMSDeviceGRSPWROUTERPNPVEND.
1691    */
1692   uint32_t pnpvend;
1693
1694   /**
1695    * @brief See @ref RTEMSDeviceGRSPWROUTERPNPUVEND.
1696    */
1697   uint32_t pnpuvend;
1698
1699   /**
1700    * @brief See @ref RTEMSDeviceGRSPWROUTERPNPUSN.
1701    */
1702   uint32_t pnpusn;
1703
1704   /**
1705    * @brief See @ref RTEMSDeviceGRSPWROUTERPNPNETDISC.
1706    */
1707   uint32_t pnpnetdisc;
1708
1709   uint32_t reserved_a60_c10[ 108 ];
1710
1711   /**
1712    * @brief See @ref RTEMSDeviceGRSPWRouterPortStats.
1713    */
1714   grspwrouter_portstats portstats[ 31 ];
1715
1716   /**
1717    * @brief See @ref RTEMSDeviceGRSPWROUTERMAXPLEN.
1718    */
1719   uint32_t maxplen[ 32 ];
1720
1721   uint32_t reserved_e80_e84;
1722
1723   /**
1724    * @brief See @ref RTEMSDeviceGRSPWROUTERCREDCNT.
1725    */
1726   uint32_t credcnt[ 31 ];
1727
1728   /**
1729    * @brief See @ref RTEMSDeviceGRSPWROUTERGPO.
1730    */
1731   uint32_t gpo[ 4 ];
1732
1733   /**
1734    * @brief See @ref RTEMSDeviceGRSPWROUTERGPI.
1735    */
1736   uint32_t gpi[ 4 ];
1737
1738   uint32_t reserved_f20_1004[ 57 ];
1739
1740   /**
1741    * @brief See @ref RTEMSDeviceGRSPWROUTERRTCOMB.
1742    */
1743   uint32_t rtcomb[ 255 ];
1744
1745   uint32_t reserved_1400_2000[ 768 ];
1746
1747   /**
1748    * @brief See @ref RTEMSDeviceGRSPWROUTERAPBAREA.
1749    */
1750   uint32_t apbarea[ 1024 ];
1751 } grspwrouter;
1752
1753 /** @} */
1754
1755 #ifdef __cplusplus
1756 }
1757 #endif
1758
1759 #endif /* _GRLIB_GRSPWROUTER_REGS_H */