include/grlib/grspw_router.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * GRSPW ROUTER APB-Register Driver.
0005  *
0006  * COPYRIGHT (c) 2010-2017.
0007  * Cobham Gaisler AB.
0008  *
0009  * Redistribution and use in source and binary forms, with or without
0010  * modification, are permitted provided that the following conditions
0011  * are met:
0012  * 1. Redistributions of source code must retain the above copyright
0013  *    notice, this list of conditions and the following disclaimer.
0014  * 2. Redistributions in binary form must reproduce the above copyright
0015  *    notice, this list of conditions and the following disclaimer in the
0016  *    documentation and/or other materials provided with the distribution.
0017  *
0018  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0019  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0020  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0021  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0022  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0023  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0024  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0025  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0026  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0027  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0028  * POSSIBILITY OF SUCH DAMAGE.
0029  */
0030
0031 #ifndef __GRSPW_ROUTER_H__
0032 #define __GRSPW_ROUTER_H__
0033
0034 #ifdef __cplusplus
0035 extern "C" {
0036 #endif
0037
0038 /* Maximum number of ROUTER devices supported by driver */
0039 #define ROUTER_MAX 2
0040
0041 #define ROUTER_ERR_OK 0
0042 #define ROUTER_ERR_EINVAL -1
0043 #define ROUTER_ERR_ERROR -2
0044 #define ROUTER_ERR_TOOMANY -3
0045 #define ROUTER_ERR_IMPLEMENTED -4
0046
0047 /* Hardware Information */
0048 struct router_hw_info {
0049     uint8_t nports_spw;
0050     uint8_t nports_amba;
0051     uint8_t nports_fifo;
0052     int8_t srouting;
0053     int8_t pnp_enable;
0054     int8_t timers_avail;
0055     int8_t pnp_avail;
0056     uint8_t ver_major;
0057     uint8_t ver_minor;
0058     uint8_t ver_patch;
0059     uint8_t iid;
0060
0061     /* Router capabilities */
0062     uint8_t amba_port_fifo_size;
0063     uint8_t spw_port_fifo_size;
0064     uint8_t rmap_maxdlen;
0065     int8_t aux_async;
0066     int8_t aux_dist_int_support;
0067     int8_t dual_port_support;
0068     int8_t dist_int_support;
0069     int8_t spwd_support;
0070     uint8_t pktcnt_support;
0071     uint8_t charcnt_support;
0072 };
0073
0074 #define ROUTER_FLG_CFG      0x01
0075 #define ROUTER_FLG_IID      0x02
0076 #define ROUTER_FLG_IDIV     0x04
0077 #define ROUTER_FLG_TPRES    0x08
0078 #define ROUTER_FLG_TRLD     0x10
0079 #define ROUTER_FLG_ALL      0x1f    /* All Above Flags */
0080
0081 struct router_config {
0082     uint32_t flags; /* Determine what configuration should be updated */
0083
0084     /* Router Configuration Register */
0085     uint32_t config;
0086
0087     /* Set Instance ID */
0088     uint8_t iid;
0089
0090     /* SpaceWire Link Initialization Clock Divisor */
0091     uint8_t idiv;
0092
0093     /* Timer Prescaler */
0094     uint32_t timer_prescaler;
0095 };
0096
0097 /* Routing table address control */
0098 struct router_route_acontrol {
0099     uint32_t control[31];
0100     uint32_t control_logical[224];
0101 };
0102
0103 /* Routing table port mapping */
0104 struct router_route_portmap {
0105     uint32_t pmap[31]; /* Port Setup for ports 1-31 */
0106     uint32_t pmap_logical[224]; /* Port setup for locgical addresses 32-255 */
0107 };
0108
0109 /* Routing table */
0110 #define ROUTER_ROUTE_FLG_MAP 0x01
0111 #define ROUTER_ROUTE_FLG_CTRL 0x02
0112 #define ROUTER_ROUTE_FLG_ALL 0x3    /* All Above Flags */
0113 struct router_routing_table {
0114     uint32_t flags; /* Determine what configuration should be updated */
0115
0116     struct router_route_acontrol acontrol;
0117     struct router_route_portmap portmap;
0118 };
0119
0120 /* Set/Get Port Control/Status */
0121 #define ROUTER_PORT_FLG_SET_CTRL    0x01
0122 #define ROUTER_PORT_FLG_GET_CTRL    0x02
0123 #define ROUTER_PORT_FLG_SET_STS 0x04
0124 #define ROUTER_PORT_FLG_GET_STS 0x08
0125 #define ROUTER_PORT_FLG_SET_CTRL2   0x10
0126 #define ROUTER_PORT_FLG_GET_CTRL2   0x20
0127 #define ROUTER_PORT_FLG_SET_TIMER   0x40
0128 #define ROUTER_PORT_FLG_GET_TIMER   0x80
0129 #define ROUTER_PORT_FLG_SET_PKTLEN  0x100
0130 #define ROUTER_PORT_FLG_GET_PKTLEN  0x200
0131 struct router_port {
0132     uint32_t flag;
0133     /* Port control */
0134     uint32_t ctrl;
0135     /* Port status */
0136     uint32_t sts;
0137     /* Port control 2 */
0138     uint32_t ctrl2;
0139     /* Timer  Reload */
0140     uint32_t timer_reload;
0141     /* Maximum packet length */
0142     uint32_t packet_length;
0143 };
0144
0145 /* Register GRSPW Router driver to Driver Manager */
0146 void router_register_drv(void);
0147
0148 extern void *router_open(unsigned int dev_no);
0149 extern int router_close(void *d);
0150 extern int router_print(void *d);
0151 extern int router_hwinfo_get(void *d, struct router_hw_info *hwinfo);
0152
0153 /* Router general config */
0154 extern int router_config_set(void *d, struct router_config *cfg);
0155 extern int router_config_get(void *d, struct router_config *cfg);
0156
0157 /* Routing table config */
0158 extern int router_routing_table_set(void *d,
0159         struct router_routing_table *cfg);
0160 extern int router_routing_table_get(void *d,
0161         struct router_routing_table *cfg);
0162
0163 /*
0164  * ROUTER PCTRL register fields
0165  */
0166 #define PCTRL_RD (0xff << PCTRL_RD_BIT)
0167 #define PCTRL_ST (0x1 << PCTRL_ST_BIT)
0168 #define PCTRL_SR (0x1 << PCTRL_SR_BIT)
0169 #define PCTRL_AD (0x1 << PCTRL_AD_BIT)
0170 #define PCTRL_LR (0x1 << PCTRL_LR_BIT)
0171 #define PCTRL_PL (0x1 << PCTRL_PL_BIT)
0172 #define PCTRL_TS (0x1 << PCTRL_TS_BIT)
0173 #define PCTRL_IC (0x1 << PCTRL_IC_BIT)
0174 #define PCTRL_ET (0x1 << PCTRL_ET_BIT)
0175 #define PCTRL_NP (0x1 << PCTRL_NP_BIT)
0176 #define PCTRL_PS (0x1 << PCTRL_PS_BIT)
0177 #define PCTRL_BE (0x1 << PCTRL_BE_BIT)
0178 #define PCTRL_DI (0x1 << PCTRL_DI_BIT)
0179 #define PCTRL_TR (0x1 << PCTRL_TR_BIT)
0180 #define PCTRL_PR (0x1 << PCTRL_PR_BIT)
0181 #define PCTRL_TF (0x1 << PCTRL_TF_BIT)
0182 #define PCTRL_RS (0x1 << PCTRL_RS_BIT)
0183 #define PCTRL_TE (0x1 << PCTRL_TE_BIT)
0184 #define PCTRL_CE (0x1 << PCTRL_CE_BIT)
0185 #define PCTRL_AS (0x1 << PCTRL_AS_BIT)
0186 #define PCTRL_LS (0x1 << PCTRL_LS_BIT)
0187 #define PCTRL_LD (0x1 << PCTRL_LD_BIT)
0188
0189 #define PCTRL_RD_BIT 24
0190 #define PCTRL_ST_BIT 21
0191 #define PCTRL_SR_BIT 20
0192 #define PCTRL_AD_BIT 19
0193 #define PCTRL_LR_BIT 18
0194 #define PCTRL_PL_BIT 17
0195 #define PCTRL_TS_BIT 16
0196 #define PCTRL_IC_BIT 15
0197 #define PCTRL_ET_BIT 14
0198 #define PCTRL_NP_BIT 13
0199 #define PCTRL_PS_BIT 12
0200 #define PCTRL_BE_BIT 11
0201 #define PCTRL_DI_BIT 10
0202 #define PCTRL_TR_BIT 9
0203 #define PCTRL_PR_BIT 8
0204 #define PCTRL_TF_BIT 7
0205 #define PCTRL_RS_BIT 6
0206 #define PCTRL_TE_BIT 5
0207 #define PCTRL_CE_BIT 3
0208 #define PCTRL_AS_BIT 2
0209 #define PCTRL_LS_BIT 1
0210 #define PCTRL_LD_BIT 0
0211
0212 /*
0213  * ROUTER PCTRL2 register fields
0214  */
0215 #define PCTRL2_SM (0xff << PCTRL2_SM_BIT)
0216 #define PCTRL2_SV (0xff << PCTRL2_SV_BIT)
0217 #define PCTRL2_OR (0x1 << PCTRL2_OR_BIT)
0218 #define PCTRL2_UR (0x1 << PCTRL2_UR_BIT)
0219 #define PCTRL2_AT (0x1 << PCTRL2_AT_BIT)
0220 #define PCTRL2_AR (0x1 << PCTRL2_AR_BIT)
0221 #define PCTRL2_IT (0x1 << PCTRL2_IT_BIT)
0222 #define PCTRL2_IR (0x1 << PCTRL2_IR_BIT)
0223 #define PCTRL2_SD (0x1f << PCTRL2_SD_BIT)
0224 #define PCTRL2_SC (0x1f << PCTRL2_SC_BIT)
0225
0226 #define PCTRL2_SM_BIT 24
0227 #define PCTRL2_SV_BIT 16
0228 #define PCTRL2_OR_BIT 15
0229 #define PCTRL2_UR_BIT 14
0230 #define PCTRL2_AT_BIT 12
0231 #define PCTRL2_AR_BIT 11
0232 #define PCTRL2_IT_BIT 10
0233 #define PCTRL2_IR_BIT 9
0234 #define PCTRL2_SD_BIT 1
0235 #define PCTRL2_SC_BIT 0
0236
0237 /* Router Set/Get Port configuration */
0238 extern int router_port_ioc(void *d, int port, struct router_port *cfg);
0239
0240 /* Read-modify-write Port Control register */
0241 extern int router_port_ctrl_rmw(void *d, int port, uint32_t *oldvalue, uint32_t bitmask, uint32_t value);
0242 /* Read-modify-write Port Control2 register */
0243 extern int router_port_ctrl2_rmw(void *d, int port, uint32_t *oldvalue, uint32_t bitmask, uint32_t value);
0244 /* Read Port Control register */
0245 extern int router_port_ctrl_get(void *d, int port, uint32_t *ctrl);
0246 /* Read Port Control2 register */
0247 extern int router_port_ctrl2_get(void *d, int port, uint32_t *ctrl2);
0248 /* Write Port Control Register */
0249 extern int router_port_ctrl_set(void *d, int port, uint32_t mask, uint32_t ctrl);
0250 /* Write Port Control2 Register */
0251 extern int router_port_ctrl2_set(void *d, int port, uint32_t mask, uint32_t ctrl2);
0252 /* Set Timer Reload Value for a specific port */
0253 extern int router_port_treload_set(void *d, int port, uint32_t reload);
0254 /* Get Timer Reload Value for a specific port */
0255 extern int router_port_treload_get(void *d, int port, uint32_t *reload);
0256 /* Get Maximum packet length for a specific port */
0257 extern int router_port_maxplen_get(void *d, int port, uint32_t *length);
0258 /* Set Maximum packet length for a specific port */
0259 extern int router_port_maxplen_set(void *d, int port, uint32_t length);
0260
0261 /*
0262  * ROUTER PSTSCFG register fields
0263  */
0264 #define PSTSCFG_EO (0x1 << PSTSCFG_EO_BIT)
0265 #define PSTSCFG_EE (0x1 << PSTSCFG_EE_BIT)
0266 #define PSTSCFG_PL (0x1 << PSTSCFG_PL_BIT)
0267 #define PSTSCFG_TT (0x1 << PSTSCFG_TT_BIT)
0268 #define PSTSCFG_PT (0x1 << PSTSCFG_PT_BIT)
0269 #define PSTSCFG_HC (0x1 << PSTSCFG_HC_BIT)
0270 #define PSTSCFG_PI (0x1 << PSTSCFG_PI_BIT)
0271 #define PSTSCFG_CE (0x1 << PSTSCFG_CE_BIT)
0272 #define PSTSCFG_EC (0xf << PSTSCFG_EC_BIT)
0273 #define PSTSCFG_TS (0x1 << PSTSCFG_TS_BIT)
0274 #define PSTSCFG_ME (0x1 << PSTSCFG_ME_BIT)
0275 #define PSTSCFG_IP (0x1f << PSTSCFG_IP_BIT)
0276 #define PSTSCFG_CP (0x1 << PSTSCFG_CP_BIT)
0277 #define PSTSCFG_PC (0xf << PSTSCFG_PC_BIT)
0278 #define PSTSCFG_WCLEAR (PSTSCFG_EO | PSTSCFG_EE | PSTSCFG_PL | \
0279                         PSTSCFG_TT | PSTSCFG_PT | PSTSCFG_HC | \
0280                         PSTSCFG_PI | PSTSCFG_CE | PSTSCFG_TS | \
0281                         PSTSCFG_ME | PSTSCFG_CP)
0282 #define PSTSCFG_WCLEAR2 (PSTSCFG_CE | PSTSCFG_CP)
0283
0284 #define PSTSCFG_EO_BIT 31
0285 #define PSTSCFG_EE_BIT 30
0286 #define PSTSCFG_PL_BIT 29
0287 #define PSTSCFG_TT_BIT 28
0288 #define PSTSCFG_PT_BIT 27
0289 #define PSTSCFG_HC_BIT 26
0290 #define PSTSCFG_PI_BIT 25
0291 #define PSTSCFG_CE_BIT 24
0292 #define PSTSCFG_EC_BIT 20
0293 #define PSTSCFG_TS_BIT 18
0294 #define PSTSCFG_ME_BIT 17
0295 #define PSTSCFG_IP_BIT 7
0296 #define PSTSCFG_CP_BIT 4
0297 #define PSTSCFG_PC_BIT 0
0298
0299 /*
0300  * ROUTER PSTS register fields
0301  */
0302 #define PSTS_PT (0x3 << PSTS_PT_BIT)
0303 #define PSTS_PL (0x1 << PSTS_PL_BIT)
0304 #define PSTS_TT (0x1 << PSTS_TT_BIT)
0305 #define PSTS_RS (0x1 << PSTS_RS_BIT)
0306 #define PSTS_SR (0x1 << PSTS_SR_BIT)
0307 #define PSTS_LR (0x1 << PSTS_LR_BIT)
0308 #define PSTS_SP (0x1 << PSTS_SP_BIT)
0309 #define PSTS_AC (0x1 << PSTS_AC_BIT)
0310 #define PSTS_TS (0x1 << PSTS_TS_BIT)
0311 #define PSTS_ME (0x1 << PSTS_ME_BIT)
0312 #define PSTS_TF (0x1 << PSTS_TF_BIT)
0313 #define PSTS_RE (0x1 << PSTS_RE_BIT)
0314 #define PSTS_LS (0x7 << PSTS_LS_BIT)
0315 #define PSTS_IP (0x1f << PSTS_IP_BIT)
0316 #define PSTS_PR (0x1 << PSTS_PR_BIT)
0317 #define PSTS_PB (0x1 << PSTS_PB_BIT)
0318 #define PSTS_IA (0x1 << PSTS_IA_BIT)
0319 #define PSTS_CE (0x1 << PSTS_CE_BIT)
0320 #define PSTS_ER (0x1 << PSTS_ER_BIT)
0321 #define PSTS_DE (0x1 << PSTS_DE_BIT)
0322 #define PSTS_PE (0x1 << PSTS_PE_BIT)
0323 #define PSTS_WCLEAR (PSTS_PL | PSTS_TT | PSTS_RS | PSTS_SR | \
0324                      PSTS_TS | PSTS_ME | PSTS_IA | PSTS_CE | \
0325                      PSTS_ER | PSTS_DE | PSTS_PE)
0326
0327 #define PSTS_PT_BIT 30
0328 #define PSTS_PL_BIT 29
0329 #define PSTS_TT_BIT 28
0330 #define PSTS_RS_BIT 27
0331 #define PSTS_SR_BIT 26
0332 #define PSTS_LR_BIT 22
0333 #define PSTS_SP_BIT 21
0334 #define PSTS_AC_BIT 20
0335 #define PSTS_TS_BIT 18
0336 #define PSTS_ME_BIT 17
0337 #define PSTS_TF_BIT 16
0338 #define PSTS_RE_BIT 15
0339 #define PSTS_LS_BIT 12
0340 #define PSTS_IP_BIT 7
0341 #define PSTS_PR_BIT 6
0342 #define PSTS_PB_BIT 5
0343 #define PSTS_IA_BIT 4
0344 #define PSTS_CE_BIT 3
0345 #define PSTS_ER_BIT 2
0346 #define PSTS_DE_BIT 1
0347 #define PSTS_PE_BIT 0
0348
0349 /* Check Port Status register and clear errors if there are */
0350 extern int router_port_status(void *d, int port, uint32_t *sts, uint32_t clrmsk);
0351
0352 #define ROUTER_LINK_STATUS_ERROR_RESET 0
0353 #define ROUTER_LINK_STATUS_ERROR_WAIT 1
0354 #define ROUTER_LINK_STATUS_READY 2
0355 #define ROUTER_LINK_STATUS_STARTED 3
0356 #define ROUTER_LINK_STATUS_CONNECTING 4
0357 #define ROUTER_LINK_STATUS_RUN_STATE 5
0358 /* Get Link status */
0359 extern int router_port_link_status(void *d, int port);
0360 /* Operate a Link */
0361 extern int router_port_enable(void *d, int port);
0362 extern int router_port_disable(void *d, int port);
0363 extern int router_port_link_stop(void *d, int port);
0364 extern int router_port_link_start(void *d, int port);
0365 extern int router_port_link_div(void *d, int port, int rundiv);
0366 extern int router_port_link_receive_spill(void *d, int port);
0367 extern int router_port_link_transmit_reset(void *d, int port);
0368
0369 /* Get port credit counter register */
0370 extern int router_port_cred_get(void *d, int port, uint32_t *cred);
0371
0372 /*
0373  * ROUTER RTACTRL register fields
0374  */
0375 #define RTACTRL_SR (0x1 << RTACTRL_SR_BIT)
0376 #define RTACTRL_EN (0x1 << RTACTRL_EN_BIT)
0377 #define RTACTRL_PR (0x1 << RTACTRL_PR_BIT)
0378 #define RTACTRL_HD (0x1 << RTACTRL_HD_BIT)
0379
0380 #define RTACTRL_SR_BIT 3
0381 #define RTACTRL_EN_BIT 2
0382 #define RTACTRL_PR_BIT 1
0383 #define RTACTRL_HD_BIT 0
0384
0385 /* Individual route modification */
0386 #define ROUTER_ROUTE_PACKETDISTRIBUTION_ENABLE (0x1 << 16)
0387 #define ROUTER_ROUTE_PACKETDISTRIBUTION_DISABLE (0x0 << 16)
0388 #define ROUTER_ROUTE_SPILLIFNOTREADY_ENABLE RTACTRL_SR
0389 #define ROUTER_ROUTE_SPILLIFNOTREADY_DISABLE 0
0390 #define ROUTER_ROUTE_ENABLE RTACTRL_EN
0391 #define ROUTER_ROUTE_DISABLE 0
0392 #define ROUTER_ROUTE_PRIORITY_HIGH RTACTRL_PR
0393 #define ROUTER_ROUTE_PRIORITY_LOW 0
0394 #define ROUTER_ROUTE_HEADERDELETION_ENABLE RTACTRL_HD
0395 #define ROUTER_ROUTE_HEADERDELETION_DISABLE 0
0396 struct router_route {
0397     uint8_t from_address;
0398     uint8_t to_port[32];
0399     int count;
0400     int options;
0401 };
0402 extern int router_route_set(void *d, struct router_route *route);
0403 extern int router_route_get(void *d, struct router_route *route);
0404
0405 /* Router configuration port write enable */
0406 extern int router_write_enable(void *d);
0407 extern int router_write_disable(void *d);
0408
0409 /* Router reset */
0410 extern int router_reset(void *d);
0411
0412 /* Set Instance ID */
0413 extern int router_instance_set(void *d, uint8_t iid);
0414 /* Get Instance ID */
0415 extern int router_instance_get(void *d, uint8_t *iid);
0416
0417 /* Set SpaceWire Link Initialization Clock Divisor */
0418 extern int router_idiv_set(void *d, uint8_t idiv);
0419 /* Get SpaceWire Link Initialization Clock Divisor */
0420 extern int router_idiv_get(void *d, uint8_t *idiv);
0421
0422 /* Set Timer Prescaler */
0423 extern int router_tpresc_set(void *d, uint32_t prescaler);
0424 /* Get Timer Prescaler */
0425 extern int router_tpresc_get(void *d, uint32_t *prescaler);
0426
0427 /* Set/get Router configuration */
0428 extern int router_cfgsts_set(void *d, uint32_t cfgsts);
0429 extern int router_cfgsts_get(void *d, uint32_t *cfgsts);
0430
0431 /* Router timecode */
0432 extern int router_tc_enable(void *d);
0433 extern int router_tc_disable(void *d);
0434 extern int router_tc_reset(void *d);
0435 extern int router_tc_get(void *d);
0436
0437 /* Router Interrupts */
0438 /*
0439  * ROUTER IMASK register fields
0440  */
0441 #define IMASK_PE (0x1 << IMASK_PE_BIT)
0442 #define IMASK_SR (0x1 << IMASK_SR_BIT)
0443 #define IMASK_RS (0x1 << IMASK_RS_BIT)
0444 #define IMASK_TT (0x1 << IMASK_TT_BIT)
0445 #define IMASK_PL (0x1 << IMASK_PL_BIT)
0446 #define IMASK_TS (0x1 << IMASK_TS_BIT)
0447 #define IMASK_AC (0x1 << IMASK_AC_BIT)
0448 #define IMASK_RE (0x1 << IMASK_RE_BIT)
0449 #define IMASK_IA (0x1 << IMASK_IA_BIT)
0450 #define IMASK_LE (0x1 << IMASK_LE_BIT)
0451 #define IMASK_ME (0x1 << IMASK_ME_BIT)
0452 #define IMASK_ALL ( IMASK_PE | IMASK_SR | IMASK_RS | IMASK_TT \
0453         IMASK_PL | IMASK_TS | IMASK_AC | IMASK_RE | IMASK_IA \
0454         IMASK_LE | IMASK_ME)
0455
0456 #define IMASK_PE_BIT 10
0457 #define IMASK_SR_BIT 9
0458 #define IMASK_RS_BIT 8
0459 #define IMASK_TT_BIT 7
0460 #define IMASK_PL_BIT 6
0461 #define IMASK_TS_BIT 5
0462 #define IMASK_AC_BIT 4
0463 #define IMASK_RE_BIT 3
0464 #define IMASK_IA_BIT 2
0465 #define IMASK_LE_BIT 1
0466 #define IMASK_ME_BIT 0
0467
0468 #define ROUTER_INTERRUPT_ALL IMASK_ALL
0469 #define ROUTER_INTERRUPT_SPWPNP_ERROR IMASK_PE
0470 #define ROUTER_INTERRUPT_SPILLED IMASK_SR
0471 #define ROUTER_INTERRUPT_RUNSTATE IMASK_RS
0472 #define ROUTER_INTERRUPT_TC_TRUNCATION IMASK_TT
0473 #define ROUTER_INTERRUPT_PACKET_TRUNCATION IMASK_PL
0474 #define ROUTER_INTERRUPT_TIMEOUT IMASK_TS
0475 #define ROUTER_INTERRUPT_CFGPORT IMASK_AC
0476 #define ROUTER_INTERRUPT_RMAP_ERROR IMASK_RE
0477 #define ROUTER_INTERRUPT_INVALID_ADDRESS IMASK_IA
0478 #define ROUTER_INTERRUPT_LINK_ERROR IMASK_LE
0479 #define ROUTER_INTERRUPT_MEMORY_ERROR IMASK_ME
0480 extern int router_port_interrupt_unmask(void *d, int port);
0481 extern int router_port_interrupt_mask(void *d, int port);
0482 extern int router_interrupt_unmask(void *d, int options);
0483 extern int router_interrupt_mask(void *d, int options);
0484
0485 /* Router Interrupt code generation */
0486 /*
0487  * ROUTER ICODEGEN register fields
0488  */
0489 #define ICODEGEN_UA (0x1 << ICODEGEN_UA_BIT)
0490 #define ICODEGEN_AH (0x1 << ICODEGEN_AH_BIT)
0491 #define ICODEGEN_IT (0x1 << ICODEGEN_IT_BIT)
0492 #define ICODEGEN_TE (0x1 << ICODEGEN_TE_BIT)
0493 #define ICODEGEN_EN (0x1 << ICODEGEN_EN_BIT)
0494 #define ICODEGEN_IN (0x1f << ICODEGEN_IN_BIT)
0495
0496 #define ICODEGEN_UA_BIT 20
0497 #define ICODEGEN_AH_BIT 19
0498 #define ICODEGEN_IT_BIT 18
0499 #define ICODEGEN_TE_BIT 17
0500 #define ICODEGEN_EN_BIT 16
0501 #define ICODEGEN_IN_BIT 0
0502
0503 #define ROUTER_ICODEGEN_ITYPE_EDGE ICODEGEN_IT
0504 #define ROUTER_ICODEGEN_ITYPE_LEVEL 0
0505 #define ROUTER_ICODEGEN_AUTOUNACK_ENABLE ICODEGEN_UA
0506 #define ROUTER_ICODEGEN_AUTOUNACK_DISABLE 0
0507 #define ROUTER_ICODEGEN_AUTOACK_ENABLE ICODEGEN_AH
0508 #define ROUTER_ICODEGEN_AUTOACK_DISABLE 0
0509 extern int router_icodegen_enable(void *d, uint8_t intn, uint32_t aitimer,
0510         int options);
0511 extern int router_icodegen_disable(void *d);
0512
0513 /* Router interrupt change timers */
0514 extern int router_isrctimer_set(void *d, uint32_t reloadvalue);
0515 extern int router_isrctimer_get(void *d, uint32_t *reloadvalue);
0516
0517 /* Router interrupt timers */
0518 extern int router_isrtimer_set(void *d, uint32_t reloadvalue);
0519 extern int router_isrtimer_get(void *d, uint32_t *reloadvalue);
0520
0521 #ifdef __cplusplus
0522 }
0523 #endif
0524
0525 #endif