include/grlib/grspw2-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRSPW2
0007  *
0008  * @brief This header file defines the GRSPW2 register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/grspw2-header */
0054
0055 #ifndef _GRLIB_GRSPW2_REGS_H
0056 #define _GRLIB_GRSPW2_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/grspw2-dma */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRSPW2DMA GRSPW2 DMA
0068  *
0069  * @ingroup RTEMSDeviceGRSPW2
0070  *
0071  * @brief This group contains the GRSPW2 DMA interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRSPW2DMADMACTRL DMA control/status (DMACTRL)
0078  *
0079  * @brief This group contains register bit definitions.
0080  *
0081  * @{
0082  */
0083
0084 #define GRSPW2_DMACTRL_INTNUM_SHIFT 26
0085 #define GRSPW2_DMACTRL_INTNUM_MASK 0xfc000000U
0086 #define GRSPW2_DMACTRL_INTNUM_GET( _reg ) \
0087   ( ( ( _reg ) & GRSPW2_DMACTRL_INTNUM_MASK ) >> \
0088     GRSPW2_DMACTRL_INTNUM_SHIFT )
0089 #define GRSPW2_DMACTRL_INTNUM_SET( _reg, _val ) \
0090   ( ( ( _reg ) & ~GRSPW2_DMACTRL_INTNUM_MASK ) | \
0091     ( ( ( _val ) << GRSPW2_DMACTRL_INTNUM_SHIFT ) & \
0092       GRSPW2_DMACTRL_INTNUM_MASK ) )
0093 #define GRSPW2_DMACTRL_INTNUM( _val ) \
0094   ( ( ( _val ) << GRSPW2_DMACTRL_INTNUM_SHIFT ) & \
0095     GRSPW2_DMACTRL_INTNUM_MASK )
0096
0097 #define GRSPW2_DMACTRL_RES_SHIFT 24
0098 #define GRSPW2_DMACTRL_RES_MASK 0x3000000U
0099 #define GRSPW2_DMACTRL_RES_GET( _reg ) \
0100   ( ( ( _reg ) & GRSPW2_DMACTRL_RES_MASK ) >> \
0101     GRSPW2_DMACTRL_RES_SHIFT )
0102 #define GRSPW2_DMACTRL_RES_SET( _reg, _val ) \
0103   ( ( ( _reg ) & ~GRSPW2_DMACTRL_RES_MASK ) | \
0104     ( ( ( _val ) << GRSPW2_DMACTRL_RES_SHIFT ) & \
0105       GRSPW2_DMACTRL_RES_MASK ) )
0106 #define GRSPW2_DMACTRL_RES( _val ) \
0107   ( ( ( _val ) << GRSPW2_DMACTRL_RES_SHIFT ) & \
0108     GRSPW2_DMACTRL_RES_MASK )
0109
0110 #define GRSPW2_DMACTRL_EP 0x800000U
0111
0112 #define GRSPW2_DMACTRL_TR 0x400000U
0113
0114 #define GRSPW2_DMACTRL_IE 0x200000U
0115
0116 #define GRSPW2_DMACTRL_IT 0x100000U
0117
0118 #define GRSPW2_DMACTRL_RP 0x80000U
0119
0120 #define GRSPW2_DMACTRL_TP 0x40000U
0121
0122 #define GRSPW2_DMACTRL_TL 0x20000U
0123
0124 #define GRSPW2_DMACTRL_LE 0x10000U
0125
0126 #define GRSPW2_DMACTRL_SP 0x8000U
0127
0128 #define GRSPW2_DMACTRL_SA 0x4000U
0129
0130 #define GRSPW2_DMACTRL_EN 0x2000U
0131
0132 #define GRSPW2_DMACTRL_NS 0x1000U
0133
0134 #define GRSPW2_DMACTRL_RD 0x800U
0135
0136 #define GRSPW2_DMACTRL_RX 0x400U
0137
0138 #define GRSPW2_DMACTRL_AT 0x200U
0139
0140 #define GRSPW2_DMACTRL_RA 0x100U
0141
0142 #define GRSPW2_DMACTRL_TA 0x80U
0143
0144 #define GRSPW2_DMACTRL_PR 0x40U
0145
0146 #define GRSPW2_DMACTRL_PS 0x20U
0147
0148 #define GRSPW2_DMACTRL_AI 0x10U
0149
0150 #define GRSPW2_DMACTRL_RI 0x8U
0151
0152 #define GRSPW2_DMACTRL_TI 0x4U
0153
0154 #define GRSPW2_DMACTRL_RE 0x2U
0155
0156 #define GRSPW2_DMACTRL_TE 0x1U
0157
0158 /** @} */
0159
0160 /**
0161  * @defgroup RTEMSDeviceGRSPW2DMADMAMAXLEN DMA RX maximum length (DMAMAXLEN)
0162  *
0163  * @brief This group contains register bit definitions.
0164  *
0165  * @{
0166  */
0167
0168 #define GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT 2
0169 #define GRSPW2_DMAMAXLEN_RXMAXLEN_MASK 0x1fffffcU
0170 #define GRSPW2_DMAMAXLEN_RXMAXLEN_GET( _reg ) \
0171   ( ( ( _reg ) & GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) >> \
0172     GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT )
0173 #define GRSPW2_DMAMAXLEN_RXMAXLEN_SET( _reg, _val ) \
0174   ( ( ( _reg ) & ~GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) | \
0175     ( ( ( _val ) << GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT ) & \
0176       GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) )
0177 #define GRSPW2_DMAMAXLEN_RXMAXLEN( _val ) \
0178   ( ( ( _val ) << GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT ) & \
0179     GRSPW2_DMAMAXLEN_RXMAXLEN_MASK )
0180
0181 #define GRSPW2_DMAMAXLEN_RES_SHIFT 0
0182 #define GRSPW2_DMAMAXLEN_RES_MASK 0x3U
0183 #define GRSPW2_DMAMAXLEN_RES_GET( _reg ) \
0184   ( ( ( _reg ) & GRSPW2_DMAMAXLEN_RES_MASK ) >> \
0185     GRSPW2_DMAMAXLEN_RES_SHIFT )
0186 #define GRSPW2_DMAMAXLEN_RES_SET( _reg, _val ) \
0187   ( ( ( _reg ) & ~GRSPW2_DMAMAXLEN_RES_MASK ) | \
0188     ( ( ( _val ) << GRSPW2_DMAMAXLEN_RES_SHIFT ) & \
0189       GRSPW2_DMAMAXLEN_RES_MASK ) )
0190 #define GRSPW2_DMAMAXLEN_RES( _val ) \
0191   ( ( ( _val ) << GRSPW2_DMAMAXLEN_RES_SHIFT ) & \
0192     GRSPW2_DMAMAXLEN_RES_MASK )
0193
0194 /** @} */
0195
0196 /**
0197  * @defgroup RTEMSDeviceGRSPW2DMADMATXDESC \
0198  *   DMA transmit descriptor table address (DMATXDESC)
0199  *
0200  * @brief This group contains register bit definitions.
0201  *
0202  * @{
0203  */
0204
0205 #define GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT 0
0206 #define GRSPW2_DMATXDESC_DESCBASEADDR_MASK 0xffffffffU
0207 #define GRSPW2_DMATXDESC_DESCBASEADDR_GET( _reg ) \
0208   ( ( ( _reg ) & GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) >> \
0209     GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT )
0210 #define GRSPW2_DMATXDESC_DESCBASEADDR_SET( _reg, _val ) \
0211   ( ( ( _reg ) & ~GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) | \
0212     ( ( ( _val ) << GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT ) & \
0213       GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) )
0214 #define GRSPW2_DMATXDESC_DESCBASEADDR( _val ) \
0215   ( ( ( _val ) << GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT ) & \
0216     GRSPW2_DMATXDESC_DESCBASEADDR_MASK )
0217
0218 #define GRSPW2_DMATXDESC_DESCSEL_SHIFT 4
0219 #define GRSPW2_DMATXDESC_DESCSEL_MASK 0xfffffff0U
0220 #define GRSPW2_DMATXDESC_DESCSEL_GET( _reg ) \
0221   ( ( ( _reg ) & GRSPW2_DMATXDESC_DESCSEL_MASK ) >> \
0222     GRSPW2_DMATXDESC_DESCSEL_SHIFT )
0223 #define GRSPW2_DMATXDESC_DESCSEL_SET( _reg, _val ) \
0224   ( ( ( _reg ) & ~GRSPW2_DMATXDESC_DESCSEL_MASK ) | \
0225     ( ( ( _val ) << GRSPW2_DMATXDESC_DESCSEL_SHIFT ) & \
0226       GRSPW2_DMATXDESC_DESCSEL_MASK ) )
0227 #define GRSPW2_DMATXDESC_DESCSEL( _val ) \
0228   ( ( ( _val ) << GRSPW2_DMATXDESC_DESCSEL_SHIFT ) & \
0229     GRSPW2_DMATXDESC_DESCSEL_MASK )
0230
0231 /** @} */
0232
0233 /**
0234  * @defgroup RTEMSDeviceGRSPW2DMADMARXDESC \
0235  *   DMA receive descriptor table address (DMARXDESC)
0236  *
0237  * @brief This group contains register bit definitions.
0238  *
0239  * @{
0240  */
0241
0242 #define GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT 10
0243 #define GRSPW2_DMARXDESC_DESCBASEADDR_MASK 0xfffffc00U
0244 #define GRSPW2_DMARXDESC_DESCBASEADDR_GET( _reg ) \
0245   ( ( ( _reg ) & GRSPW2_DMARXDESC_DESCBASEADDR_MASK ) >> \
0246     GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT )
0247 #define GRSPW2_DMARXDESC_DESCBASEADDR_SET( _reg, _val ) \
0248   ( ( ( _reg ) & ~GRSPW2_DMARXDESC_DESCBASEADDR_MASK ) | \
0249     ( ( ( _val ) << GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT ) & \
0250       GRSPW2_DMARXDESC_DESCBASEADDR_MASK ) )
0251 #define GRSPW2_DMARXDESC_DESCBASEADDR( _val ) \
0252   ( ( ( _val ) << GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT ) & \
0253     GRSPW2_DMARXDESC_DESCBASEADDR_MASK )
0254
0255 #define GRSPW2_DMARXDESC_DESCSEL_SHIFT 3
0256 #define GRSPW2_DMARXDESC_DESCSEL_MASK 0x3f8U
0257 #define GRSPW2_DMARXDESC_DESCSEL_GET( _reg ) \
0258   ( ( ( _reg ) & GRSPW2_DMARXDESC_DESCSEL_MASK ) >> \
0259     GRSPW2_DMARXDESC_DESCSEL_SHIFT )
0260 #define GRSPW2_DMARXDESC_DESCSEL_SET( _reg, _val ) \
0261   ( ( ( _reg ) & ~GRSPW2_DMARXDESC_DESCSEL_MASK ) | \
0262     ( ( ( _val ) << GRSPW2_DMARXDESC_DESCSEL_SHIFT ) & \
0263       GRSPW2_DMARXDESC_DESCSEL_MASK ) )
0264 #define GRSPW2_DMARXDESC_DESCSEL( _val ) \
0265   ( ( ( _val ) << GRSPW2_DMARXDESC_DESCSEL_SHIFT ) & \
0266     GRSPW2_DMARXDESC_DESCSEL_MASK )
0267
0268 /** @} */
0269
0270 /**
0271  * @defgroup RTEMSDeviceGRSPW2DMADMAADDR DMA address (DMAADDR)
0272  *
0273  * @brief This group contains register bit definitions.
0274  *
0275  * @{
0276  */
0277
0278 #define GRSPW2_DMAADDR_MASK_SHIFT 8
0279 #define GRSPW2_DMAADDR_MASK_MASK 0xff00U
0280 #define GRSPW2_DMAADDR_MASK_GET( _reg ) \
0281   ( ( ( _reg ) & GRSPW2_DMAADDR_MASK_MASK ) >> \
0282     GRSPW2_DMAADDR_MASK_SHIFT )
0283 #define GRSPW2_DMAADDR_MASK_SET( _reg, _val ) \
0284   ( ( ( _reg ) & ~GRSPW2_DMAADDR_MASK_MASK ) | \
0285     ( ( ( _val ) << GRSPW2_DMAADDR_MASK_SHIFT ) & \
0286       GRSPW2_DMAADDR_MASK_MASK ) )
0287 #define GRSPW2_DMAADDR_MASK( _val ) \
0288   ( ( ( _val ) << GRSPW2_DMAADDR_MASK_SHIFT ) & \
0289     GRSPW2_DMAADDR_MASK_MASK )
0290
0291 #define GRSPW2_DMAADDR_ADDR_SHIFT 0
0292 #define GRSPW2_DMAADDR_ADDR_MASK 0xffU
0293 #define GRSPW2_DMAADDR_ADDR_GET( _reg ) \
0294   ( ( ( _reg ) & GRSPW2_DMAADDR_ADDR_MASK ) >> \
0295     GRSPW2_DMAADDR_ADDR_SHIFT )
0296 #define GRSPW2_DMAADDR_ADDR_SET( _reg, _val ) \
0297   ( ( ( _reg ) & ~GRSPW2_DMAADDR_ADDR_MASK ) | \
0298     ( ( ( _val ) << GRSPW2_DMAADDR_ADDR_SHIFT ) & \
0299       GRSPW2_DMAADDR_ADDR_MASK ) )
0300 #define GRSPW2_DMAADDR_ADDR( _val ) \
0301   ( ( ( _val ) << GRSPW2_DMAADDR_ADDR_SHIFT ) & \
0302     GRSPW2_DMAADDR_ADDR_MASK )
0303
0304 /** @} */
0305
0306 /**
0307  * @brief This structure defines the GRSPW2 DMA register block memory map.
0308  */
0309 typedef struct grspw2_dma {
0310   /**
0311    * @brief See @ref RTEMSDeviceGRSPW2DMADMACTRL.
0312    */
0313   uint32_t dmactrl;
0314
0315   /**
0316    * @brief See @ref RTEMSDeviceGRSPW2DMADMAMAXLEN.
0317    */
0318   uint32_t dmamaxlen;
0319
0320   /**
0321    * @brief See @ref RTEMSDeviceGRSPW2DMADMATXDESC.
0322    */
0323   uint32_t dmatxdesc;
0324
0325   /**
0326    * @brief See @ref RTEMSDeviceGRSPW2DMADMARXDESC.
0327    */
0328   uint32_t dmarxdesc;
0329
0330   /**
0331    * @brief See @ref RTEMSDeviceGRSPW2DMADMAADDR.
0332    */
0333   uint32_t dmaaddr;
0334
0335   uint32_t reserved_14_20[ 3 ];
0336 } grspw2_dma;
0337
0338 /** @} */
0339
0340 /* Generated from spec:/dev/grlib/if/grspw2 */
0341
0342 /**
0343  * @defgroup RTEMSDeviceGRSPW2 GRSPW2
0344  *
0345  * @ingroup RTEMSDeviceGRLIB
0346  *
0347  * @brief This group contains the GRSPW2 interfaces.
0348  *
0349  * @{
0350  */
0351
0352 /**
0353  * @defgroup RTEMSDeviceGRSPW2CTRL Control (CTRL)
0354  *
0355  * @brief This group contains register bit definitions.
0356  *
0357  * @{
0358  */
0359
0360 #define GRSPW2_CTRL_RA 0x80000000U
0361
0362 #define GRSPW2_CTRL_RX 0x40000000U
0363
0364 #define GRSPW2_CTRL_RC 0x20000000U
0365
0366 #define GRSPW2_CTRL_NCH_SHIFT 27
0367 #define GRSPW2_CTRL_NCH_MASK 0x18000000U
0368 #define GRSPW2_CTRL_NCH_GET( _reg ) \
0369   ( ( ( _reg ) & GRSPW2_CTRL_NCH_MASK ) >> \
0370     GRSPW2_CTRL_NCH_SHIFT )
0371 #define GRSPW2_CTRL_NCH_SET( _reg, _val ) \
0372   ( ( ( _reg ) & ~GRSPW2_CTRL_NCH_MASK ) | \
0373     ( ( ( _val ) << GRSPW2_CTRL_NCH_SHIFT ) & \
0374       GRSPW2_CTRL_NCH_MASK ) )
0375 #define GRSPW2_CTRL_NCH( _val ) \
0376   ( ( ( _val ) << GRSPW2_CTRL_NCH_SHIFT ) & \
0377     GRSPW2_CTRL_NCH_MASK )
0378
0379 #define GRSPW2_CTRL_PO 0x4000000U
0380
0381 #define GRSPW2_CTRL_CC 0x2000000U
0382
0383 #define GRSPW2_CTRL_ID 0x1000000U
0384
0385 #define GRSPW2_CTRL_R 0x800000U
0386
0387 #define GRSPW2_CTRL_LE 0x400000U
0388
0389 #define GRSPW2_CTRL_PS 0x200000U
0390
0391 #define GRSPW2_CTRL_NP 0x100000U
0392
0393 #define GRSPW2_CTRL_PNPA_SHIFT 18
0394 #define GRSPW2_CTRL_PNPA_MASK 0xc0000U
0395 #define GRSPW2_CTRL_PNPA_GET( _reg ) \
0396   ( ( ( _reg ) & GRSPW2_CTRL_PNPA_MASK ) >> \
0397     GRSPW2_CTRL_PNPA_SHIFT )
0398 #define GRSPW2_CTRL_PNPA_SET( _reg, _val ) \
0399   ( ( ( _reg ) & ~GRSPW2_CTRL_PNPA_MASK ) | \
0400     ( ( ( _val ) << GRSPW2_CTRL_PNPA_SHIFT ) & \
0401       GRSPW2_CTRL_PNPA_MASK ) )
0402 #define GRSPW2_CTRL_PNPA( _val ) \
0403   ( ( ( _val ) << GRSPW2_CTRL_PNPA_SHIFT ) & \
0404     GRSPW2_CTRL_PNPA_MASK )
0405
0406 #define GRSPW2_CTRL_RD 0x20000U
0407
0408 #define GRSPW2_CTRL_RE 0x10000U
0409
0410 #define GRSPW2_CTRL_PE 0x8000U
0411
0412 #define GRSPW2_CTRL_R 0x4000U
0413
0414 #define GRSPW2_CTRL_TL 0x2000U
0415
0416 #define GRSPW2_CTRL_TF 0x1000U
0417
0418 #define GRSPW2_CTRL_TR 0x800U
0419
0420 #define GRSPW2_CTRL_TT 0x400U
0421
0422 #define GRSPW2_CTRL_LI 0x200U
0423
0424 #define GRSPW2_CTRL_TQ 0x100U
0425
0426 #define GRSPW2_CTRL_R 0x80U
0427
0428 #define GRSPW2_CTRL_RS 0x40U
0429
0430 #define GRSPW2_CTRL_PM 0x20U
0431
0432 #define GRSPW2_CTRL_TI 0x10U
0433
0434 #define GRSPW2_CTRL_IE 0x8U
0435
0436 #define GRSPW2_CTRL_AS 0x4U
0437
0438 #define GRSPW2_CTRL_LS 0x2U
0439
0440 #define GRSPW2_CTRL_LD 0x1U
0441
0442 /** @} */
0443
0444 /**
0445  * @defgroup RTEMSDeviceGRSPW2STS Status (STS)
0446  *
0447  * @brief This group contains register bit definitions.
0448  *
0449  * @{
0450  */
0451
0452 #define GRSPW2_STS_NRXD_SHIFT 26
0453 #define GRSPW2_STS_NRXD_MASK 0xc000000U
0454 #define GRSPW2_STS_NRXD_GET( _reg ) \
0455   ( ( ( _reg ) & GRSPW2_STS_NRXD_MASK ) >> \
0456     GRSPW2_STS_NRXD_SHIFT )
0457 #define GRSPW2_STS_NRXD_SET( _reg, _val ) \
0458   ( ( ( _reg ) & ~GRSPW2_STS_NRXD_MASK ) | \
0459     ( ( ( _val ) << GRSPW2_STS_NRXD_SHIFT ) & \
0460       GRSPW2_STS_NRXD_MASK ) )
0461 #define GRSPW2_STS_NRXD( _val ) \
0462   ( ( ( _val ) << GRSPW2_STS_NRXD_SHIFT ) & \
0463     GRSPW2_STS_NRXD_MASK )
0464
0465 #define GRSPW2_STS_NTXD 0x2000000U
0466
0467 #define GRSPW2_STS_LS_SHIFT 21
0468 #define GRSPW2_STS_LS_MASK 0xe00000U
0469 #define GRSPW2_STS_LS_GET( _reg ) \
0470   ( ( ( _reg ) & GRSPW2_STS_LS_MASK ) >> \
0471     GRSPW2_STS_LS_SHIFT )
0472 #define GRSPW2_STS_LS_SET( _reg, _val ) \
0473   ( ( ( _reg ) & ~GRSPW2_STS_LS_MASK ) | \
0474     ( ( ( _val ) << GRSPW2_STS_LS_SHIFT ) & \
0475       GRSPW2_STS_LS_MASK ) )
0476 #define GRSPW2_STS_LS( _val ) \
0477   ( ( ( _val ) << GRSPW2_STS_LS_SHIFT ) & \
0478     GRSPW2_STS_LS_MASK )
0479
0480 #define GRSPW2_STS_AP 0x200U
0481
0482 #define GRSPW2_STS_EE 0x100U
0483
0484 #define GRSPW2_STS_IA 0x80U
0485
0486 #define GRSPW2_STS_RES_SHIFT 5
0487 #define GRSPW2_STS_RES_MASK 0x60U
0488 #define GRSPW2_STS_RES_GET( _reg ) \
0489   ( ( ( _reg ) & GRSPW2_STS_RES_MASK ) >> \
0490     GRSPW2_STS_RES_SHIFT )
0491 #define GRSPW2_STS_RES_SET( _reg, _val ) \
0492   ( ( ( _reg ) & ~GRSPW2_STS_RES_MASK ) | \
0493     ( ( ( _val ) << GRSPW2_STS_RES_SHIFT ) & \
0494       GRSPW2_STS_RES_MASK ) )
0495 #define GRSPW2_STS_RES( _val ) \
0496   ( ( ( _val ) << GRSPW2_STS_RES_SHIFT ) & \
0497     GRSPW2_STS_RES_MASK )
0498
0499 #define GRSPW2_STS_PE 0x10U
0500
0501 #define GRSPW2_STS_DE 0x8U
0502
0503 #define GRSPW2_STS_ER 0x4U
0504
0505 #define GRSPW2_STS_CE 0x2U
0506
0507 #define GRSPW2_STS_TO 0x1U
0508
0509 /** @} */
0510
0511 /**
0512  * @defgroup RTEMSDeviceGRSPW2DEFADDR Default address (DEFADDR)
0513  *
0514  * @brief This group contains register bit definitions.
0515  *
0516  * @{
0517  */
0518
0519 #define GRSPW2_DEFADDR_DEFMASK_SHIFT 8
0520 #define GRSPW2_DEFADDR_DEFMASK_MASK 0xff00U
0521 #define GRSPW2_DEFADDR_DEFMASK_GET( _reg ) \
0522   ( ( ( _reg ) & GRSPW2_DEFADDR_DEFMASK_MASK ) >> \
0523     GRSPW2_DEFADDR_DEFMASK_SHIFT )
0524 #define GRSPW2_DEFADDR_DEFMASK_SET( _reg, _val ) \
0525   ( ( ( _reg ) & ~GRSPW2_DEFADDR_DEFMASK_MASK ) | \
0526     ( ( ( _val ) << GRSPW2_DEFADDR_DEFMASK_SHIFT ) & \
0527       GRSPW2_DEFADDR_DEFMASK_MASK ) )
0528 #define GRSPW2_DEFADDR_DEFMASK( _val ) \
0529   ( ( ( _val ) << GRSPW2_DEFADDR_DEFMASK_SHIFT ) & \
0530     GRSPW2_DEFADDR_DEFMASK_MASK )
0531
0532 #define GRSPW2_DEFADDR_DEFADDR_SHIFT 0
0533 #define GRSPW2_DEFADDR_DEFADDR_MASK 0xffU
0534 #define GRSPW2_DEFADDR_DEFADDR_GET( _reg ) \
0535   ( ( ( _reg ) & GRSPW2_DEFADDR_DEFADDR_MASK ) >> \
0536     GRSPW2_DEFADDR_DEFADDR_SHIFT )
0537 #define GRSPW2_DEFADDR_DEFADDR_SET( _reg, _val ) \
0538   ( ( ( _reg ) & ~GRSPW2_DEFADDR_DEFADDR_MASK ) | \
0539     ( ( ( _val ) << GRSPW2_DEFADDR_DEFADDR_SHIFT ) & \
0540       GRSPW2_DEFADDR_DEFADDR_MASK ) )
0541 #define GRSPW2_DEFADDR_DEFADDR( _val ) \
0542   ( ( ( _val ) << GRSPW2_DEFADDR_DEFADDR_SHIFT ) & \
0543     GRSPW2_DEFADDR_DEFADDR_MASK )
0544
0545 /** @} */
0546
0547 /**
0548  * @defgroup RTEMSDeviceGRSPW2CLKDIV Clock divisor (CLKDIV)
0549  *
0550  * @brief This group contains register bit definitions.
0551  *
0552  * @{
0553  */
0554
0555 #define GRSPW2_CLKDIV_CLKDIVSTART_SHIFT 8
0556 #define GRSPW2_CLKDIV_CLKDIVSTART_MASK 0xff00U
0557 #define GRSPW2_CLKDIV_CLKDIVSTART_GET( _reg ) \
0558   ( ( ( _reg ) & GRSPW2_CLKDIV_CLKDIVSTART_MASK ) >> \
0559     GRSPW2_CLKDIV_CLKDIVSTART_SHIFT )
0560 #define GRSPW2_CLKDIV_CLKDIVSTART_SET( _reg, _val ) \
0561   ( ( ( _reg ) & ~GRSPW2_CLKDIV_CLKDIVSTART_MASK ) | \
0562     ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVSTART_SHIFT ) & \
0563       GRSPW2_CLKDIV_CLKDIVSTART_MASK ) )
0564 #define GRSPW2_CLKDIV_CLKDIVSTART( _val ) \
0565   ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVSTART_SHIFT ) & \
0566     GRSPW2_CLKDIV_CLKDIVSTART_MASK )
0567
0568 #define GRSPW2_CLKDIV_CLKDIVRUN_SHIFT 0
0569 #define GRSPW2_CLKDIV_CLKDIVRUN_MASK 0xffU
0570 #define GRSPW2_CLKDIV_CLKDIVRUN_GET( _reg ) \
0571   ( ( ( _reg ) & GRSPW2_CLKDIV_CLKDIVRUN_MASK ) >> \
0572     GRSPW2_CLKDIV_CLKDIVRUN_SHIFT )
0573 #define GRSPW2_CLKDIV_CLKDIVRUN_SET( _reg, _val ) \
0574   ( ( ( _reg ) & ~GRSPW2_CLKDIV_CLKDIVRUN_MASK ) | \
0575     ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVRUN_SHIFT ) & \
0576       GRSPW2_CLKDIV_CLKDIVRUN_MASK ) )
0577 #define GRSPW2_CLKDIV_CLKDIVRUN( _val ) \
0578   ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVRUN_SHIFT ) & \
0579     GRSPW2_CLKDIV_CLKDIVRUN_MASK )
0580
0581 /** @} */
0582
0583 /**
0584  * @defgroup RTEMSDeviceGRSPW2DKEY Destination key (DKEY)
0585  *
0586  * @brief This group contains register bit definitions.
0587  *
0588  * @{
0589  */
0590
0591 #define GRSPW2_DKEY_DESTKEY_SHIFT 0
0592 #define GRSPW2_DKEY_DESTKEY_MASK 0xffU
0593 #define GRSPW2_DKEY_DESTKEY_GET( _reg ) \
0594   ( ( ( _reg ) & GRSPW2_DKEY_DESTKEY_MASK ) >> \
0595     GRSPW2_DKEY_DESTKEY_SHIFT )
0596 #define GRSPW2_DKEY_DESTKEY_SET( _reg, _val ) \
0597   ( ( ( _reg ) & ~GRSPW2_DKEY_DESTKEY_MASK ) | \
0598     ( ( ( _val ) << GRSPW2_DKEY_DESTKEY_SHIFT ) & \
0599       GRSPW2_DKEY_DESTKEY_MASK ) )
0600 #define GRSPW2_DKEY_DESTKEY( _val ) \
0601   ( ( ( _val ) << GRSPW2_DKEY_DESTKEY_SHIFT ) & \
0602     GRSPW2_DKEY_DESTKEY_MASK )
0603
0604 /** @} */
0605
0606 /**
0607  * @defgroup RTEMSDeviceGRSPW2TC Time-code (TC)
0608  *
0609  * @brief This group contains register bit definitions.
0610  *
0611  * @{
0612  */
0613
0614 #define GRSPW2_TC_TCTRL_SHIFT 6
0615 #define GRSPW2_TC_TCTRL_MASK 0xc0U
0616 #define GRSPW2_TC_TCTRL_GET( _reg ) \
0617   ( ( ( _reg ) & GRSPW2_TC_TCTRL_MASK ) >> \
0618     GRSPW2_TC_TCTRL_SHIFT )
0619 #define GRSPW2_TC_TCTRL_SET( _reg, _val ) \
0620   ( ( ( _reg ) & ~GRSPW2_TC_TCTRL_MASK ) | \
0621     ( ( ( _val ) << GRSPW2_TC_TCTRL_SHIFT ) & \
0622       GRSPW2_TC_TCTRL_MASK ) )
0623 #define GRSPW2_TC_TCTRL( _val ) \
0624   ( ( ( _val ) << GRSPW2_TC_TCTRL_SHIFT ) & \
0625     GRSPW2_TC_TCTRL_MASK )
0626
0627 #define GRSPW2_TC_TIMECNT_SHIFT 0
0628 #define GRSPW2_TC_TIMECNT_MASK 0x3fU
0629 #define GRSPW2_TC_TIMECNT_GET( _reg ) \
0630   ( ( ( _reg ) & GRSPW2_TC_TIMECNT_MASK ) >> \
0631     GRSPW2_TC_TIMECNT_SHIFT )
0632 #define GRSPW2_TC_TIMECNT_SET( _reg, _val ) \
0633   ( ( ( _reg ) & ~GRSPW2_TC_TIMECNT_MASK ) | \
0634     ( ( ( _val ) << GRSPW2_TC_TIMECNT_SHIFT ) & \
0635       GRSPW2_TC_TIMECNT_MASK ) )
0636 #define GRSPW2_TC_TIMECNT( _val ) \
0637   ( ( ( _val ) << GRSPW2_TC_TIMECNT_SHIFT ) & \
0638     GRSPW2_TC_TIMECNT_MASK )
0639
0640 /** @} */
0641
0642 /**
0643  * @defgroup RTEMSDeviceGRSPW2INTCTRL Interrupt distribution control (INTCTRL)
0644  *
0645  * @brief This group contains register bit definitions.
0646  *
0647  * @{
0648  */
0649
0650 #define GRSPW2_INTCTRL_INTNUM_SHIFT 26
0651 #define GRSPW2_INTCTRL_INTNUM_MASK 0xfc000000U
0652 #define GRSPW2_INTCTRL_INTNUM_GET( _reg ) \
0653   ( ( ( _reg ) & GRSPW2_INTCTRL_INTNUM_MASK ) >> \
0654     GRSPW2_INTCTRL_INTNUM_SHIFT )
0655 #define GRSPW2_INTCTRL_INTNUM_SET( _reg, _val ) \
0656   ( ( ( _reg ) & ~GRSPW2_INTCTRL_INTNUM_MASK ) | \
0657     ( ( ( _val ) << GRSPW2_INTCTRL_INTNUM_SHIFT ) & \
0658       GRSPW2_INTCTRL_INTNUM_MASK ) )
0659 #define GRSPW2_INTCTRL_INTNUM( _val ) \
0660   ( ( ( _val ) << GRSPW2_INTCTRL_INTNUM_SHIFT ) & \
0661     GRSPW2_INTCTRL_INTNUM_MASK )
0662
0663 #define GRSPW2_INTCTRL_RS 0x2000000U
0664
0665 #define GRSPW2_INTCTRL_EE 0x1000000U
0666
0667 #define GRSPW2_INTCTRL_IA 0x800000U
0668
0669 #define GRSPW2_INTCTRL_RES 0x2U
0670
0671 #define GRSPW2_INTCTRL_TQ_SHIFT 21
0672 #define GRSPW2_INTCTRL_TQ_MASK 0x600000U
0673 #define GRSPW2_INTCTRL_TQ_GET( _reg ) \
0674   ( ( ( _reg ) & GRSPW2_INTCTRL_TQ_MASK ) >> \
0675     GRSPW2_INTCTRL_TQ_SHIFT )
0676 #define GRSPW2_INTCTRL_TQ_SET( _reg, _val ) \
0677   ( ( ( _reg ) & ~GRSPW2_INTCTRL_TQ_MASK ) | \
0678     ( ( ( _val ) << GRSPW2_INTCTRL_TQ_SHIFT ) & \
0679       GRSPW2_INTCTRL_TQ_MASK ) )
0680 #define GRSPW2_INTCTRL_TQ( _val ) \
0681   ( ( ( _val ) << GRSPW2_INTCTRL_TQ_SHIFT ) & \
0682     GRSPW2_INTCTRL_TQ_MASK )
0683
0684 #define GRSPW2_INTCTRL_AQ 0x100000U
0685
0686 #define GRSPW2_INTCTRL_IQ 0x80000U
0687
0688 #define GRSPW2_INTCTRL_RES 0x40000U
0689
0690 #define GRSPW2_INTCTRL_AA_SHIFT 16
0691 #define GRSPW2_INTCTRL_AA_MASK 0x30000U
0692 #define GRSPW2_INTCTRL_AA_GET( _reg ) \
0693   ( ( ( _reg ) & GRSPW2_INTCTRL_AA_MASK ) >> \
0694     GRSPW2_INTCTRL_AA_SHIFT )
0695 #define GRSPW2_INTCTRL_AA_SET( _reg, _val ) \
0696   ( ( ( _reg ) & ~GRSPW2_INTCTRL_AA_MASK ) | \
0697     ( ( ( _val ) << GRSPW2_INTCTRL_AA_SHIFT ) & \
0698       GRSPW2_INTCTRL_AA_MASK ) )
0699 #define GRSPW2_INTCTRL_AA( _val ) \
0700   ( ( ( _val ) << GRSPW2_INTCTRL_AA_SHIFT ) & \
0701     GRSPW2_INTCTRL_AA_MASK )
0702
0703 #define GRSPW2_INTCTRL_AT 0x8000U
0704
0705 #define GRSPW2_INTCTRL_IT 0x4000U
0706
0707 #define GRSPW2_INTCTRL_RES 0x2000U
0708
0709 #define GRSPW2_INTCTRL_ID_SHIFT 8
0710 #define GRSPW2_INTCTRL_ID_MASK 0x1f00U
0711 #define GRSPW2_INTCTRL_ID_GET( _reg ) \
0712   ( ( ( _reg ) & GRSPW2_INTCTRL_ID_MASK ) >> \
0713     GRSPW2_INTCTRL_ID_SHIFT )
0714 #define GRSPW2_INTCTRL_ID_SET( _reg, _val ) \
0715   ( ( ( _reg ) & ~GRSPW2_INTCTRL_ID_MASK ) | \
0716     ( ( ( _val ) << GRSPW2_INTCTRL_ID_SHIFT ) & \
0717       GRSPW2_INTCTRL_ID_MASK ) )
0718 #define GRSPW2_INTCTRL_ID( _val ) \
0719   ( ( ( _val ) << GRSPW2_INTCTRL_ID_SHIFT ) & \
0720     GRSPW2_INTCTRL_ID_MASK )
0721
0722 #define GRSPW2_INTCTRL_II 0x80U
0723
0724 #define GRSPW2_INTCTRL_TXINT 0x40U
0725
0726 /** @} */
0727
0728 /**
0729  * @defgroup RTEMSDeviceGRSPW2INTRX Interrupt-code receive (INTRX)
0730  *
0731  * @brief This group contains register bit definitions.
0732  *
0733  * @{
0734  */
0735
0736 #define GRSPW2_INTRX_RXIRQ_SHIFT 0
0737 #define GRSPW2_INTRX_RXIRQ_MASK 0xffffffffU
0738 #define GRSPW2_INTRX_RXIRQ_GET( _reg ) \
0739   ( ( ( _reg ) & GRSPW2_INTRX_RXIRQ_MASK ) >> \
0740     GRSPW2_INTRX_RXIRQ_SHIFT )
0741 #define GRSPW2_INTRX_RXIRQ_SET( _reg, _val ) \
0742   ( ( ( _reg ) & ~GRSPW2_INTRX_RXIRQ_MASK ) | \
0743     ( ( ( _val ) << GRSPW2_INTRX_RXIRQ_SHIFT ) & \
0744       GRSPW2_INTRX_RXIRQ_MASK ) )
0745 #define GRSPW2_INTRX_RXIRQ( _val ) \
0746   ( ( ( _val ) << GRSPW2_INTRX_RXIRQ_SHIFT ) & \
0747     GRSPW2_INTRX_RXIRQ_MASK )
0748
0749 /** @} */
0750
0751 /**
0752  * @defgroup RTEMSDeviceGRSPW2INTTO Interrupt timeout (INTTO)
0753  *
0754  * @brief This group contains register bit definitions.
0755  *
0756  * @{
0757  */
0758
0759 #define GRSPW2_INTTO_INTTO_SHIFT 0
0760 #define GRSPW2_INTTO_INTTO_MASK 0xffffffffU
0761 #define GRSPW2_INTTO_INTTO_GET( _reg ) \
0762   ( ( ( _reg ) & GRSPW2_INTTO_INTTO_MASK ) >> \
0763     GRSPW2_INTTO_INTTO_SHIFT )
0764 #define GRSPW2_INTTO_INTTO_SET( _reg, _val ) \
0765   ( ( ( _reg ) & ~GRSPW2_INTTO_INTTO_MASK ) | \
0766     ( ( ( _val ) << GRSPW2_INTTO_INTTO_SHIFT ) & \
0767       GRSPW2_INTTO_INTTO_MASK ) )
0768 #define GRSPW2_INTTO_INTTO( _val ) \
0769   ( ( ( _val ) << GRSPW2_INTTO_INTTO_SHIFT ) & \
0770     GRSPW2_INTTO_INTTO_MASK )
0771
0772 /** @} */
0773
0774 /**
0775  * @defgroup RTEMSDeviceGRSPW2INTTOEXT Interrupt timeout extended (INTTOEXT)
0776  *
0777  * @brief This group contains register bit definitions.
0778  *
0779  * @{
0780  */
0781
0782 #define GRSPW2_INTTOEXT_INTTOEXT_SHIFT 0
0783 #define GRSPW2_INTTOEXT_INTTOEXT_MASK 0xffffffffU
0784 #define GRSPW2_INTTOEXT_INTTOEXT_GET( _reg ) \
0785   ( ( ( _reg ) & GRSPW2_INTTOEXT_INTTOEXT_MASK ) >> \
0786     GRSPW2_INTTOEXT_INTTOEXT_SHIFT )
0787 #define GRSPW2_INTTOEXT_INTTOEXT_SET( _reg, _val ) \
0788   ( ( ( _reg ) & ~GRSPW2_INTTOEXT_INTTOEXT_MASK ) | \
0789     ( ( ( _val ) << GRSPW2_INTTOEXT_INTTOEXT_SHIFT ) & \
0790       GRSPW2_INTTOEXT_INTTOEXT_MASK ) )
0791 #define GRSPW2_INTTOEXT_INTTOEXT( _val ) \
0792   ( ( ( _val ) << GRSPW2_INTTOEXT_INTTOEXT_SHIFT ) & \
0793     GRSPW2_INTTOEXT_INTTOEXT_MASK )
0794
0795 /** @} */
0796
0797 /**
0798  * @defgroup RTEMSDeviceGRSPW2TICKMASK Interrupt tick-out mask (TICKMASK)
0799  *
0800  * @brief This group contains register bit definitions.
0801  *
0802  * @{
0803  */
0804
0805 #define GRSPW2_TICKMASK_MASK_SHIFT 0
0806 #define GRSPW2_TICKMASK_MASK_MASK 0xffffffffU
0807 #define GRSPW2_TICKMASK_MASK_GET( _reg ) \
0808   ( ( ( _reg ) & GRSPW2_TICKMASK_MASK_MASK ) >> \
0809     GRSPW2_TICKMASK_MASK_SHIFT )
0810 #define GRSPW2_TICKMASK_MASK_SET( _reg, _val ) \
0811   ( ( ( _reg ) & ~GRSPW2_TICKMASK_MASK_MASK ) | \
0812     ( ( ( _val ) << GRSPW2_TICKMASK_MASK_SHIFT ) & \
0813       GRSPW2_TICKMASK_MASK_MASK ) )
0814 #define GRSPW2_TICKMASK_MASK( _val ) \
0815   ( ( ( _val ) << GRSPW2_TICKMASK_MASK_SHIFT ) & \
0816     GRSPW2_TICKMASK_MASK_MASK )
0817
0818 /** @} */
0819
0820 /**
0821  * @defgroup RTEMSDeviceGRSPW2AUTOACKTICKMASKEXT \
0822  *   Interrupt-code auto acknowledge mask / interrupt tick-out mask extended (AUTOACK_TICKMASKEXT)
0823  *
0824  * @brief This group contains register bit definitions.
0825  *
0826  * @{
0827  */
0828
0829 #define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT 0
0830 #define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK 0xffffffffU
0831 #define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_GET( _reg ) \
0832   ( ( ( _reg ) & GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK ) >> \
0833     GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT )
0834 #define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SET( _reg, _val ) \
0835   ( ( ( _reg ) & ~GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK ) | \
0836     ( ( ( _val ) << GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT ) & \
0837       GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK ) )
0838 #define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK( _val ) \
0839   ( ( ( _val ) << GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT ) & \
0840     GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK )
0841
0842 /** @} */
0843
0844 /**
0845  * @defgroup RTEMSDeviceGRSPW2INTCFG \
0846  *   Interrupt distribution configuration (INTCFG)
0847  *
0848  * @brief This group contains register bit definitions.
0849  *
0850  * @{
0851  */
0852
0853 #define GRSPW2_INTCFG_INTNUM3_SHIFT 26
0854 #define GRSPW2_INTCFG_INTNUM3_MASK 0xfc000000U
0855 #define GRSPW2_INTCFG_INTNUM3_GET( _reg ) \
0856   ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM3_MASK ) >> \
0857     GRSPW2_INTCFG_INTNUM3_SHIFT )
0858 #define GRSPW2_INTCFG_INTNUM3_SET( _reg, _val ) \
0859   ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM3_MASK ) | \
0860     ( ( ( _val ) << GRSPW2_INTCFG_INTNUM3_SHIFT ) & \
0861       GRSPW2_INTCFG_INTNUM3_MASK ) )
0862 #define GRSPW2_INTCFG_INTNUM3( _val ) \
0863   ( ( ( _val ) << GRSPW2_INTCFG_INTNUM3_SHIFT ) & \
0864     GRSPW2_INTCFG_INTNUM3_MASK )
0865
0866 #define GRSPW2_INTCFG_INTNUM2_SHIFT 20
0867 #define GRSPW2_INTCFG_INTNUM2_MASK 0x3f00000U
0868 #define GRSPW2_INTCFG_INTNUM2_GET( _reg ) \
0869   ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM2_MASK ) >> \
0870     GRSPW2_INTCFG_INTNUM2_SHIFT )
0871 #define GRSPW2_INTCFG_INTNUM2_SET( _reg, _val ) \
0872   ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM2_MASK ) | \
0873     ( ( ( _val ) << GRSPW2_INTCFG_INTNUM2_SHIFT ) & \
0874       GRSPW2_INTCFG_INTNUM2_MASK ) )
0875 #define GRSPW2_INTCFG_INTNUM2( _val ) \
0876   ( ( ( _val ) << GRSPW2_INTCFG_INTNUM2_SHIFT ) & \
0877     GRSPW2_INTCFG_INTNUM2_MASK )
0878
0879 #define GRSPW2_INTCFG_INTNUM1_SHIFT 14
0880 #define GRSPW2_INTCFG_INTNUM1_MASK 0xfc000U
0881 #define GRSPW2_INTCFG_INTNUM1_GET( _reg ) \
0882   ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM1_MASK ) >> \
0883     GRSPW2_INTCFG_INTNUM1_SHIFT )
0884 #define GRSPW2_INTCFG_INTNUM1_SET( _reg, _val ) \
0885   ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM1_MASK ) | \
0886     ( ( ( _val ) << GRSPW2_INTCFG_INTNUM1_SHIFT ) & \
0887       GRSPW2_INTCFG_INTNUM1_MASK ) )
0888 #define GRSPW2_INTCFG_INTNUM1( _val ) \
0889   ( ( ( _val ) << GRSPW2_INTCFG_INTNUM1_SHIFT ) & \
0890     GRSPW2_INTCFG_INTNUM1_MASK )
0891
0892 #define GRSPW2_INTCFG_INTNUM0_SHIFT 8
0893 #define GRSPW2_INTCFG_INTNUM0_MASK 0x3f00U
0894 #define GRSPW2_INTCFG_INTNUM0_GET( _reg ) \
0895   ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM0_MASK ) >> \
0896     GRSPW2_INTCFG_INTNUM0_SHIFT )
0897 #define GRSPW2_INTCFG_INTNUM0_SET( _reg, _val ) \
0898   ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM0_MASK ) | \
0899     ( ( ( _val ) << GRSPW2_INTCFG_INTNUM0_SHIFT ) & \
0900       GRSPW2_INTCFG_INTNUM0_MASK ) )
0901 #define GRSPW2_INTCFG_INTNUM0( _val ) \
0902   ( ( ( _val ) << GRSPW2_INTCFG_INTNUM0_SHIFT ) & \
0903     GRSPW2_INTCFG_INTNUM0_MASK )
0904
0905 #define GRSPW2_INTCFG_NUMINT_SHIFT 4
0906 #define GRSPW2_INTCFG_NUMINT_MASK 0xf0U
0907 #define GRSPW2_INTCFG_NUMINT_GET( _reg ) \
0908   ( ( ( _reg ) & GRSPW2_INTCFG_NUMINT_MASK ) >> \
0909     GRSPW2_INTCFG_NUMINT_SHIFT )
0910 #define GRSPW2_INTCFG_NUMINT_SET( _reg, _val ) \
0911   ( ( ( _reg ) & ~GRSPW2_INTCFG_NUMINT_MASK ) | \
0912     ( ( ( _val ) << GRSPW2_INTCFG_NUMINT_SHIFT ) & \
0913       GRSPW2_INTCFG_NUMINT_MASK ) )
0914 #define GRSPW2_INTCFG_NUMINT( _val ) \
0915   ( ( ( _val ) << GRSPW2_INTCFG_NUMINT_SHIFT ) & \
0916     GRSPW2_INTCFG_NUMINT_MASK )
0917
0918 #define GRSPW2_INTCFG_PR 0x8U
0919
0920 #define GRSPW2_INTCFG_IR 0x4U
0921
0922 #define GRSPW2_INTCFG_IT 0x2U
0923
0924 #define GRSPW2_INTCFG_EE 0x1U
0925
0926 /** @} */
0927
0928 /**
0929  * @defgroup RTEMSDeviceGRSPW2ISR Interrupt distribution ISR (ISR)
0930  *
0931  * @brief This group contains register bit definitions.
0932  *
0933  * @{
0934  */
0935
0936 #define GRSPW2_ISR_ISR_SHIFT 0
0937 #define GRSPW2_ISR_ISR_MASK 0xffffffffU
0938 #define GRSPW2_ISR_ISR_GET( _reg ) \
0939   ( ( ( _reg ) & GRSPW2_ISR_ISR_MASK ) >> \
0940     GRSPW2_ISR_ISR_SHIFT )
0941 #define GRSPW2_ISR_ISR_SET( _reg, _val ) \
0942   ( ( ( _reg ) & ~GRSPW2_ISR_ISR_MASK ) | \
0943     ( ( ( _val ) << GRSPW2_ISR_ISR_SHIFT ) & \
0944       GRSPW2_ISR_ISR_MASK ) )
0945 #define GRSPW2_ISR_ISR( _val ) \
0946   ( ( ( _val ) << GRSPW2_ISR_ISR_SHIFT ) & \
0947     GRSPW2_ISR_ISR_MASK )
0948
0949 /** @} */
0950
0951 /**
0952  * @defgroup RTEMSDeviceGRSPW2ISREXT \
0953  *   Interrupt distribution ISR extended (ISREXT)
0954  *
0955  * @brief This group contains register bit definitions.
0956  *
0957  * @{
0958  */
0959
0960 #define GRSPW2_ISREXT_ISR_SHIFT 0
0961 #define GRSPW2_ISREXT_ISR_MASK 0xffffffffU
0962 #define GRSPW2_ISREXT_ISR_GET( _reg ) \
0963   ( ( ( _reg ) & GRSPW2_ISREXT_ISR_MASK ) >> \
0964     GRSPW2_ISREXT_ISR_SHIFT )
0965 #define GRSPW2_ISREXT_ISR_SET( _reg, _val ) \
0966   ( ( ( _reg ) & ~GRSPW2_ISREXT_ISR_MASK ) | \
0967     ( ( ( _val ) << GRSPW2_ISREXT_ISR_SHIFT ) & \
0968       GRSPW2_ISREXT_ISR_MASK ) )
0969 #define GRSPW2_ISREXT_ISR( _val ) \
0970   ( ( ( _val ) << GRSPW2_ISREXT_ISR_SHIFT ) & \
0971     GRSPW2_ISREXT_ISR_MASK )
0972
0973 /** @} */
0974
0975 /**
0976  * @defgroup RTEMSDeviceGRSPW2PRESCALER \
0977  *   Interrupt distribution prescaler reload (PRESCALER)
0978  *
0979  * @brief This group contains register bit definitions.
0980  *
0981  * @{
0982  */
0983
0984 #define GRSPW2_PRESCALER_R 0x80000000U
0985
0986 #define GRSPW2_PRESCALER_RL_SHIFT 0
0987 #define GRSPW2_PRESCALER_RL_MASK 0x7fffffffU
0988 #define GRSPW2_PRESCALER_RL_GET( _reg ) \
0989   ( ( ( _reg ) & GRSPW2_PRESCALER_RL_MASK ) >> \
0990     GRSPW2_PRESCALER_RL_SHIFT )
0991 #define GRSPW2_PRESCALER_RL_SET( _reg, _val ) \
0992   ( ( ( _reg ) & ~GRSPW2_PRESCALER_RL_MASK ) | \
0993     ( ( ( _val ) << GRSPW2_PRESCALER_RL_SHIFT ) & \
0994       GRSPW2_PRESCALER_RL_MASK ) )
0995 #define GRSPW2_PRESCALER_RL( _val ) \
0996   ( ( ( _val ) << GRSPW2_PRESCALER_RL_SHIFT ) & \
0997     GRSPW2_PRESCALER_RL_MASK )
0998
0999 /** @} */
1000
1001 /**
1002  * @defgroup RTEMSDeviceGRSPW2ISRTIMER \
1003  *   Interrupt distribution ISR timer reload (ISRTIMER)
1004  *
1005  * @brief This group contains register bit definitions.
1006  *
1007  * @{
1008  */
1009
1010 #define GRSPW2_ISRTIMER_EN 0x80000000U
1011
1012 #define GRSPW2_ISRTIMER_RL_SHIFT 0
1013 #define GRSPW2_ISRTIMER_RL_MASK 0x7fffffffU
1014 #define GRSPW2_ISRTIMER_RL_GET( _reg ) \
1015   ( ( ( _reg ) & GRSPW2_ISRTIMER_RL_MASK ) >> \
1016     GRSPW2_ISRTIMER_RL_SHIFT )
1017 #define GRSPW2_ISRTIMER_RL_SET( _reg, _val ) \
1018   ( ( ( _reg ) & ~GRSPW2_ISRTIMER_RL_MASK ) | \
1019     ( ( ( _val ) << GRSPW2_ISRTIMER_RL_SHIFT ) & \
1020       GRSPW2_ISRTIMER_RL_MASK ) )
1021 #define GRSPW2_ISRTIMER_RL( _val ) \
1022   ( ( ( _val ) << GRSPW2_ISRTIMER_RL_SHIFT ) & \
1023     GRSPW2_ISRTIMER_RL_MASK )
1024
1025 /** @} */
1026
1027 /**
1028  * @defgroup RTEMSDeviceGRSPW2IATIMER \
1029  *   Interrupt distribution INT / ACK timer reload (IATIMER)
1030  *
1031  * @brief This group contains register bit definitions.
1032  *
1033  * @{
1034  */
1035
1036 #define GRSPW2_IATIMER_EN 0x80000000U
1037
1038 #define GRSPW2_IATIMER_RL_SHIFT 0
1039 #define GRSPW2_IATIMER_RL_MASK 0x7fffffffU
1040 #define GRSPW2_IATIMER_RL_GET( _reg ) \
1041   ( ( ( _reg ) & GRSPW2_IATIMER_RL_MASK ) >> \
1042     GRSPW2_IATIMER_RL_SHIFT )
1043 #define GRSPW2_IATIMER_RL_SET( _reg, _val ) \
1044   ( ( ( _reg ) & ~GRSPW2_IATIMER_RL_MASK ) | \
1045     ( ( ( _val ) << GRSPW2_IATIMER_RL_SHIFT ) & \
1046       GRSPW2_IATIMER_RL_MASK ) )
1047 #define GRSPW2_IATIMER_RL( _val ) \
1048   ( ( ( _val ) << GRSPW2_IATIMER_RL_SHIFT ) & \
1049     GRSPW2_IATIMER_RL_MASK )
1050
1051 /** @} */
1052
1053 /**
1054  * @defgroup RTEMSDeviceGRSPW2ICTIMER \
1055  *   Interrupt distribution change timer reload (ICTIMER)
1056  *
1057  * @brief This group contains register bit definitions.
1058  *
1059  * @{
1060  */
1061
1062 #define GRSPW2_ICTIMER_EN 0x80000000U
1063
1064 #define GRSPW2_ICTIMER_RL_SHIFT 0
1065 #define GRSPW2_ICTIMER_RL_MASK 0x7fffffffU
1066 #define GRSPW2_ICTIMER_RL_GET( _reg ) \
1067   ( ( ( _reg ) & GRSPW2_ICTIMER_RL_MASK ) >> \
1068     GRSPW2_ICTIMER_RL_SHIFT )
1069 #define GRSPW2_ICTIMER_RL_SET( _reg, _val ) \
1070   ( ( ( _reg ) & ~GRSPW2_ICTIMER_RL_MASK ) | \
1071     ( ( ( _val ) << GRSPW2_ICTIMER_RL_SHIFT ) & \
1072       GRSPW2_ICTIMER_RL_MASK ) )
1073 #define GRSPW2_ICTIMER_RL( _val ) \
1074   ( ( ( _val ) << GRSPW2_ICTIMER_RL_SHIFT ) & \
1075     GRSPW2_ICTIMER_RL_MASK )
1076
1077 /** @} */
1078
1079 /**
1080  * @defgroup RTEMSDeviceGRSPW2PNPVEND \
1081  *   SpaceWire Plug-and-Play - Device Vendor and Product ID (PNPVEND)
1082  *
1083  * @brief This group contains register bit definitions.
1084  *
1085  * @{
1086  */
1087
1088 #define GRSPW2_PNPVEND_VEND_SHIFT 16
1089 #define GRSPW2_PNPVEND_VEND_MASK 0xffff0000U
1090 #define GRSPW2_PNPVEND_VEND_GET( _reg ) \
1091   ( ( ( _reg ) & GRSPW2_PNPVEND_VEND_MASK ) >> \
1092     GRSPW2_PNPVEND_VEND_SHIFT )
1093 #define GRSPW2_PNPVEND_VEND_SET( _reg, _val ) \
1094   ( ( ( _reg ) & ~GRSPW2_PNPVEND_VEND_MASK ) | \
1095     ( ( ( _val ) << GRSPW2_PNPVEND_VEND_SHIFT ) & \
1096       GRSPW2_PNPVEND_VEND_MASK ) )
1097 #define GRSPW2_PNPVEND_VEND( _val ) \
1098   ( ( ( _val ) << GRSPW2_PNPVEND_VEND_SHIFT ) & \
1099     GRSPW2_PNPVEND_VEND_MASK )
1100
1101 #define GRSPW2_PNPVEND_PROD_SHIFT 0
1102 #define GRSPW2_PNPVEND_PROD_MASK 0xffffU
1103 #define GRSPW2_PNPVEND_PROD_GET( _reg ) \
1104   ( ( ( _reg ) & GRSPW2_PNPVEND_PROD_MASK ) >> \
1105     GRSPW2_PNPVEND_PROD_SHIFT )
1106 #define GRSPW2_PNPVEND_PROD_SET( _reg, _val ) \
1107   ( ( ( _reg ) & ~GRSPW2_PNPVEND_PROD_MASK ) | \
1108     ( ( ( _val ) << GRSPW2_PNPVEND_PROD_SHIFT ) & \
1109       GRSPW2_PNPVEND_PROD_MASK ) )
1110 #define GRSPW2_PNPVEND_PROD( _val ) \
1111   ( ( ( _val ) << GRSPW2_PNPVEND_PROD_SHIFT ) & \
1112     GRSPW2_PNPVEND_PROD_MASK )
1113
1114 /** @} */
1115
1116 /**
1117  * @defgroup RTEMSDeviceGRSPW2PNPOA0 \
1118  *   SpaceWire Plug-and-Play - Owner Address 0 (PNPOA0)
1119  *
1120  * @brief This group contains register bit definitions.
1121  *
1122  * @{
1123  */
1124
1125 #define GRSPW2_PNPOA0_RA_SHIFT 0
1126 #define GRSPW2_PNPOA0_RA_MASK 0xffffffffU
1127 #define GRSPW2_PNPOA0_RA_GET( _reg ) \
1128   ( ( ( _reg ) & GRSPW2_PNPOA0_RA_MASK ) >> \
1129     GRSPW2_PNPOA0_RA_SHIFT )
1130 #define GRSPW2_PNPOA0_RA_SET( _reg, _val ) \
1131   ( ( ( _reg ) & ~GRSPW2_PNPOA0_RA_MASK ) | \
1132     ( ( ( _val ) << GRSPW2_PNPOA0_RA_SHIFT ) & \
1133       GRSPW2_PNPOA0_RA_MASK ) )
1134 #define GRSPW2_PNPOA0_RA( _val ) \
1135   ( ( ( _val ) << GRSPW2_PNPOA0_RA_SHIFT ) & \
1136     GRSPW2_PNPOA0_RA_MASK )
1137
1138 /** @} */
1139
1140 /**
1141  * @defgroup RTEMSDeviceGRSPW2PNPOA1 \
1142  *   SpaceWire Plug-and-Play - Owner Address 1 (PNPOA1)
1143  *
1144  * @brief This group contains register bit definitions.
1145  *
1146  * @{
1147  */
1148
1149 #define GRSPW2_PNPOA1_RA_SHIFT 0
1150 #define GRSPW2_PNPOA1_RA_MASK 0xffffffffU
1151 #define GRSPW2_PNPOA1_RA_GET( _reg ) \
1152   ( ( ( _reg ) & GRSPW2_PNPOA1_RA_MASK ) >> \
1153     GRSPW2_PNPOA1_RA_SHIFT )
1154 #define GRSPW2_PNPOA1_RA_SET( _reg, _val ) \
1155   ( ( ( _reg ) & ~GRSPW2_PNPOA1_RA_MASK ) | \
1156     ( ( ( _val ) << GRSPW2_PNPOA1_RA_SHIFT ) & \
1157       GRSPW2_PNPOA1_RA_MASK ) )
1158 #define GRSPW2_PNPOA1_RA( _val ) \
1159   ( ( ( _val ) << GRSPW2_PNPOA1_RA_SHIFT ) & \
1160     GRSPW2_PNPOA1_RA_MASK )
1161
1162 /** @} */
1163
1164 /**
1165  * @defgroup RTEMSDeviceGRSPW2PNPOA2 \
1166  *   SpaceWire Plug-and-Play - Owner Address 2 (PNPOA2)
1167  *
1168  * @brief This group contains register bit definitions.
1169  *
1170  * @{
1171  */
1172
1173 #define GRSPW2_PNPOA2_RA_SHIFT 0
1174 #define GRSPW2_PNPOA2_RA_MASK 0xffffffffU
1175 #define GRSPW2_PNPOA2_RA_GET( _reg ) \
1176   ( ( ( _reg ) & GRSPW2_PNPOA2_RA_MASK ) >> \
1177     GRSPW2_PNPOA2_RA_SHIFT )
1178 #define GRSPW2_PNPOA2_RA_SET( _reg, _val ) \
1179   ( ( ( _reg ) & ~GRSPW2_PNPOA2_RA_MASK ) | \
1180     ( ( ( _val ) << GRSPW2_PNPOA2_RA_SHIFT ) & \
1181       GRSPW2_PNPOA2_RA_MASK ) )
1182 #define GRSPW2_PNPOA2_RA( _val ) \
1183   ( ( ( _val ) << GRSPW2_PNPOA2_RA_SHIFT ) & \
1184     GRSPW2_PNPOA2_RA_MASK )
1185
1186 /** @} */
1187
1188 /**
1189  * @defgroup RTEMSDeviceGRSPW2PNPDEVID \
1190  *   SpaceWire Plug-and-Play - Device ID (PNPDEVID)
1191  *
1192  * @brief This group contains register bit definitions.
1193  *
1194  * @{
1195  */
1196
1197 #define GRSPW2_PNPDEVID_DID_SHIFT 0
1198 #define GRSPW2_PNPDEVID_DID_MASK 0xffffffffU
1199 #define GRSPW2_PNPDEVID_DID_GET( _reg ) \
1200   ( ( ( _reg ) & GRSPW2_PNPDEVID_DID_MASK ) >> \
1201     GRSPW2_PNPDEVID_DID_SHIFT )
1202 #define GRSPW2_PNPDEVID_DID_SET( _reg, _val ) \
1203   ( ( ( _reg ) & ~GRSPW2_PNPDEVID_DID_MASK ) | \
1204     ( ( ( _val ) << GRSPW2_PNPDEVID_DID_SHIFT ) & \
1205       GRSPW2_PNPDEVID_DID_MASK ) )
1206 #define GRSPW2_PNPDEVID_DID( _val ) \
1207   ( ( ( _val ) << GRSPW2_PNPDEVID_DID_SHIFT ) & \
1208     GRSPW2_PNPDEVID_DID_MASK )
1209
1210 /** @} */
1211
1212 /**
1213  * @defgroup RTEMSDeviceGRSPW2PNPUVEND \
1214  *   SpaceWire Plug-and-Play - Unit Vendor and Product ID (PNPUVEND)
1215  *
1216  * @brief This group contains register bit definitions.
1217  *
1218  * @{
1219  */
1220
1221 #define GRSPW2_PNPUVEND_VEND_SHIFT 16
1222 #define GRSPW2_PNPUVEND_VEND_MASK 0xffff0000U
1223 #define GRSPW2_PNPUVEND_VEND_GET( _reg ) \
1224   ( ( ( _reg ) & GRSPW2_PNPUVEND_VEND_MASK ) >> \
1225     GRSPW2_PNPUVEND_VEND_SHIFT )
1226 #define GRSPW2_PNPUVEND_VEND_SET( _reg, _val ) \
1227   ( ( ( _reg ) & ~GRSPW2_PNPUVEND_VEND_MASK ) | \
1228     ( ( ( _val ) << GRSPW2_PNPUVEND_VEND_SHIFT ) & \
1229       GRSPW2_PNPUVEND_VEND_MASK ) )
1230 #define GRSPW2_PNPUVEND_VEND( _val ) \
1231   ( ( ( _val ) << GRSPW2_PNPUVEND_VEND_SHIFT ) & \
1232     GRSPW2_PNPUVEND_VEND_MASK )
1233
1234 #define GRSPW2_PNPUVEND_PROD_SHIFT 0
1235 #define GRSPW2_PNPUVEND_PROD_MASK 0xffffU
1236 #define GRSPW2_PNPUVEND_PROD_GET( _reg ) \
1237   ( ( ( _reg ) & GRSPW2_PNPUVEND_PROD_MASK ) >> \
1238     GRSPW2_PNPUVEND_PROD_SHIFT )
1239 #define GRSPW2_PNPUVEND_PROD_SET( _reg, _val ) \
1240   ( ( ( _reg ) & ~GRSPW2_PNPUVEND_PROD_MASK ) | \
1241     ( ( ( _val ) << GRSPW2_PNPUVEND_PROD_SHIFT ) & \
1242       GRSPW2_PNPUVEND_PROD_MASK ) )
1243 #define GRSPW2_PNPUVEND_PROD( _val ) \
1244   ( ( ( _val ) << GRSPW2_PNPUVEND_PROD_SHIFT ) & \
1245     GRSPW2_PNPUVEND_PROD_MASK )
1246
1247 /** @} */
1248
1249 /**
1250  * @defgroup RTEMSDeviceGRSPW2PNPUSN \
1251  *   SpaceWire Plug-and-Play - Unit Serial Number (PNPUSN)
1252  *
1253  * @brief This group contains register bit definitions.
1254  *
1255  * @{
1256  */
1257
1258 #define GRSPW2_PNPUSN_USN_SHIFT 0
1259 #define GRSPW2_PNPUSN_USN_MASK 0xffffffffU
1260 #define GRSPW2_PNPUSN_USN_GET( _reg ) \
1261   ( ( ( _reg ) & GRSPW2_PNPUSN_USN_MASK ) >> \
1262     GRSPW2_PNPUSN_USN_SHIFT )
1263 #define GRSPW2_PNPUSN_USN_SET( _reg, _val ) \
1264   ( ( ( _reg ) & ~GRSPW2_PNPUSN_USN_MASK ) | \
1265     ( ( ( _val ) << GRSPW2_PNPUSN_USN_SHIFT ) & \
1266       GRSPW2_PNPUSN_USN_MASK ) )
1267 #define GRSPW2_PNPUSN_USN( _val ) \
1268   ( ( ( _val ) << GRSPW2_PNPUSN_USN_SHIFT ) & \
1269     GRSPW2_PNPUSN_USN_MASK )
1270
1271 /** @} */
1272
1273 /**
1274  * @brief This structure defines the GRSPW2 register block memory map.
1275  */
1276 typedef struct grspw2 {
1277   /**
1278    * @brief See @ref RTEMSDeviceGRSPW2CTRL.
1279    */
1280   uint32_t ctrl;
1281
1282   /**
1283    * @brief See @ref RTEMSDeviceGRSPW2STS.
1284    */
1285   uint32_t sts;
1286
1287   /**
1288    * @brief See @ref RTEMSDeviceGRSPW2DEFADDR.
1289    */
1290   uint32_t defaddr;
1291
1292   /**
1293    * @brief See @ref RTEMSDeviceGRSPW2CLKDIV.
1294    */
1295   uint32_t clkdiv;
1296
1297   /**
1298    * @brief See @ref RTEMSDeviceGRSPW2DKEY.
1299    */
1300   uint32_t dkey;
1301
1302   /**
1303    * @brief See @ref RTEMSDeviceGRSPW2TC.
1304    */
1305   uint32_t tc;
1306
1307   uint32_t reserved_18_20[ 2 ];
1308
1309   /**
1310    * @brief See @ref RTEMSDeviceGRSPW2DMA.
1311    */
1312   grspw2_dma dma[ 4 ];
1313
1314   /**
1315    * @brief See @ref RTEMSDeviceGRSPW2INTCTRL.
1316    */
1317   uint32_t intctrl;
1318
1319   /**
1320    * @brief See @ref RTEMSDeviceGRSPW2INTRX.
1321    */
1322   uint32_t intrx;
1323
1324   uint32_t reserved_a8_ac;
1325
1326   /**
1327    * @brief See @ref RTEMSDeviceGRSPW2INTTO.
1328    */
1329   uint32_t intto;
1330
1331   /**
1332    * @brief See @ref RTEMSDeviceGRSPW2INTTOEXT.
1333    */
1334   uint32_t inttoext;
1335
1336   /**
1337    * @brief See @ref RTEMSDeviceGRSPW2TICKMASK.
1338    */
1339   uint32_t tickmask;
1340
1341   /**
1342    * @brief See @ref RTEMSDeviceGRSPW2AUTOACKTICKMASKEXT.
1343    */
1344   uint32_t autoack_tickmaskext;
1345
1346   /**
1347    * @brief See @ref RTEMSDeviceGRSPW2INTCFG.
1348    */
1349   uint32_t intcfg;
1350
1351   uint32_t reserved_c0_c4;
1352
1353   /**
1354    * @brief See @ref RTEMSDeviceGRSPW2ISR.
1355    */
1356   uint32_t isr;
1357
1358   /**
1359    * @brief See @ref RTEMSDeviceGRSPW2ISREXT.
1360    */
1361   uint32_t isrext;
1362
1363   uint32_t reserved_cc_d0;
1364
1365   /**
1366    * @brief See @ref RTEMSDeviceGRSPW2PRESCALER.
1367    */
1368   uint32_t prescaler;
1369
1370   /**
1371    * @brief See @ref RTEMSDeviceGRSPW2ISRTIMER.
1372    */
1373   uint32_t isrtimer;
1374
1375   /**
1376    * @brief See @ref RTEMSDeviceGRSPW2IATIMER.
1377    */
1378   uint32_t iatimer;
1379
1380   /**
1381    * @brief See @ref RTEMSDeviceGRSPW2ICTIMER.
1382    */
1383   uint32_t ictimer;
1384
1385   /**
1386    * @brief See @ref RTEMSDeviceGRSPW2PNPVEND.
1387    */
1388   uint32_t pnpvend;
1389
1390   uint32_t reserved_e4_e8;
1391
1392   /**
1393    * @brief See @ref RTEMSDeviceGRSPW2PNPOA0.
1394    */
1395   uint32_t pnpoa0;
1396
1397   /**
1398    * @brief See @ref RTEMSDeviceGRSPW2PNPOA1.
1399    */
1400   uint32_t pnpoa1;
1401
1402   /**
1403    * @brief See @ref RTEMSDeviceGRSPW2PNPOA2.
1404    */
1405   uint32_t pnpoa2;
1406
1407   /**
1408    * @brief See @ref RTEMSDeviceGRSPW2PNPDEVID.
1409    */
1410   uint32_t pnpdevid;
1411
1412   /**
1413    * @brief See @ref RTEMSDeviceGRSPW2PNPUVEND.
1414    */
1415   uint32_t pnpuvend;
1416
1417   /**
1418    * @brief See @ref RTEMSDeviceGRSPW2PNPUSN.
1419    */
1420   uint32_t pnpusn;
1421 } grspw2;
1422
1423 /** @} */
1424
1425 #ifdef __cplusplus
1426 }
1427 #endif
1428
1429 #endif /* _GRLIB_GRSPW2_REGS_H */