include/grlib/grpwm.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  *  GRPWM PWM Driver interface.
0005  *
0006  *  COPYRIGHT (c) 2009.
0007  *  Cobham Gaisler AB.
0008  *
0009  * Redistribution and use in source and binary forms, with or without
0010  * modification, are permitted provided that the following conditions
0011  * are met:
0012  * 1. Redistributions of source code must retain the above copyright
0013  *    notice, this list of conditions and the following disclaimer.
0014  * 2. Redistributions in binary form must reproduce the above copyright
0015  *    notice, this list of conditions and the following disclaimer in the
0016  *    documentation and/or other materials provided with the distribution.
0017  *
0018  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0019  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0020  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0021  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0022  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0023  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0024  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0025  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0026  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0027  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0028  * POSSIBILITY OF SUCH DAMAGE.
0029  */
0030
0031 #ifndef __GRPWM_H__
0032 #define __GRPWM_H__
0033
0034 #ifdef __cplusplus
0035 extern "C" {
0036 #endif
0037
0038 extern void grpwm_register_drv (void);
0039
0040 #define GRPWM_IOCTL_GET_CAP 1   /* Get Capabilities */
0041 #define GRPWM_IOCTL_SET_CONFIG  2   /* Configure one PWM Channel */
0042 #define GRPWM_IOCTL_SET_SCALER  3   /* Set one scaler */
0043 #define GRPWM_IOCTL_UPDATE  4   /* Set current period and compare value */
0044 #define GRPWM_IOCTL_IRQ     5   /* Set up IRQ handling */
0045
0046 /*** Argument for GRPWM_IOCTL_GET_CAP ***/
0047
0048 /* The Capability of the PWM core */
0049 struct grpwm_ioctl_cap {
0050     int     channel_cnt;    /* Number of channels */
0051     unsigned int    pwm;        /* Capability1 register */
0052     unsigned int    wave;       /* Capability2 register, Wave form capabilities of last PWM channel, otherwise 0 */
0053 };
0054
0055 /*** Argument for GRPWM_IOCTL_GET_CONFIG and GRPWM_IOCTL_SET_CONFIG ***/
0056
0057 /* Config One PWM */
0058 struct grpwm_ioctl_config {
0059     unsigned int    channel;    /* Select channel to configure */
0060
0061     /* Specific for one PWM channel */
0062     unsigned int    options;    /* PWM options */
0063     unsigned char   dbscaler;   /* value greater than 15 disable Dead band */
0064     unsigned char   scaler_index;   /* Select scaler used by PWM channel */
0065
0066     /* IRQ Setup */
0067     unsigned char   irqscaler;  /* IRQ scaler */
0068     void        *isr_arg;   /* Argument of IRQ handler */
0069     void        (*isr)(int channel, void *arg); /* Interrupt service routine for this PWM Channel */
0070
0071     /* Waveform set up */
0072     int     wave_activate;      /* Enables Waveform functionality */
0073     unsigned int    wave_synccfg;       /* Bits [29,30,31] is written into Wave-Config register */
0074     unsigned int    wave_sync;      /* Sets sync compare register */
0075     unsigned int    *wave_data;     /* If not NULL, the Wave RAM is filled with data */
0076     unsigned int    wave_data_length;   /* Length of Wave RAM Data, Also used for wstopaddr */
0077 };
0078
0079 #define GRPWM_CONFIG_OPTION_FLIP        0x04000000  /* Set this to Flip PWM output pair */
0080 #define GRPWM_CONFIG_OPTION_DEAD_BAND       0x00200000  /* Dead Band enable */
0081 #define GRPWM_CONFIG_OPTION_SYMMETRIC       0x00000040  /* If not defined, asymmetric */
0082 #define GRPWM_CONFIG_OPTION_ASYMMERTIC      0
0083 #define GRPWM_CONFIG_OPTION_DUAL        0x00000020  /* Dual Compare Enable */
0084 #define GRPWM_CONFIG_OPTION_PAIR        0x00000004  /* PWM Pair Enable */
0085 #define GRPWM_CONFIG_OPTION_SINGLE      0x00000000  /* PWM Pair Disable */
0086 #define GRPWM_CONFIG_OPTION_POLARITY_HIGH   0x00000002  /* PWM Polarity HIGH */
0087 #define GRPWM_CONFIG_OPTION_POLARITY_LOW    0x00000000  /* PWM Polarity LOW */
0088
0089 #define GRPWM_CONFIG_OPTION_MASK ( \
0090     GRPWM_CONFIG_OPTION_DEAD_BAND | GRPWM_CONFIG_OPTION_SYMMETRIC | \
0091     GRPWM_CONFIG_OPTION_DUAL | GRPWM_CONFIG_OPTION_PAIR | \
0092     GRPWM_CONFIG_OPTION_POLARITY_HIGH \
0093     )
0094
0095 /*** Argument for GPPWM_IOCTL_SET_SCALER ***/
0096
0097 struct grpwm_ioctl_scaler {
0098     unsigned int index_mask;/* Scaler update index mask, bit 0 = Scaler 0, bit 1 = Scaler 1 */
0099     unsigned int values[8]; /* Scaler update values, values[N] is stored into scaler N, if mask & 1<<N is set */
0100 };
0101
0102 /*** Argument for GRPWM_IOCTL_UPDATE ***/
0103
0104 #define GRPWM_UPDATE_OPTION_ENABLE  0x01    /* Enable the PWM core */
0105 #define GRPWM_UPDATE_OPTION_DISABLE 0x02    /* Disable the PWM core */
0106 #define GRPWM_UPDATE_OPTION_PERIOD  0x04    /* Update period register */
0107 #define GRPWM_UPDATE_OPTION_COMP    0x08    /* Update Compare register */
0108 #define GRPWM_UPDATE_OPTION_DBCOMP  0x10    /* Update Dead band register */
0109 #define GRPWM_UPDATE_OPTION_FIX     0x20    /* Update fix output pins (bypass PWM) */
0110
0111 /* FIX PIN bit-mask */
0112 #define GRPWM_UPDATE_FIX_ENABLE     1   /* Enable force ouput */
0113 #define GRPWM_UPDATE_FIX_DISABLE    0   /* Disable force ouput */
0114 #define GRPWM_UPDATE_FIX_0_LOW      0   /* PIN 0 OUPUT: LOW */
0115 #define GRPWM_UPDATE_FIX_0_HIGH     2   /* PIN 0 OUPUT: HIGH */
0116 #define GRPWM_UPDATE_FIX_1_LOW      0   /* PIN 1 OUPUT: LOW */
0117 #define GRPWM_UPDATE_FIX_1_HIGH     4   /* PIN 1 OUPUT: HIGH */
0118
0119 struct grpwm_ioctl_update_chan {
0120     unsigned int    options;    /* Select what is updated */
0121     unsigned int    period;     /* Period register content */
0122     unsigned int    compare;    /* Compare register content */
0123     unsigned int    dbcomp;     /* Dead band register content */
0124     unsigned char   fix;        /* Bit-mask that select output on one or two PWM
0125                      * output pins. Depends on PAIR config value.
0126                      */
0127 };
0128 struct grpwm_ioctl_update {
0129     unsigned char           chanmask; /* Bit Mask select channels */
0130     struct grpwm_ioctl_update_chan  channels[8]; /*  */
0131 };
0132
0133 /*** Argument for GPPWM_IOCTL_IRQ ***/
0134
0135 #define GRPWM_IRQ_DISABLE   0   /* Disable IRQ */
0136 #define GRPWM_IRQ_PERIOD    1   /* Enable IRQ on period match */
0137 #define GRPWM_IRQ_COMPARE   3   /* Enable IRQ on Compare Match */
0138 #define GRPWM_IRQ_CLEAR     0x10    /* Clear any pending IRQ on GRPWM and IRQ controller */
0139
0140 #define GRPWM_IRQ_CHAN      0x100   /* Channel N is selected, by adding 0x100*N */
0141
0142 #ifdef __cplusplus
0143 }
0144 #endif
0145
0146 #endif