include/grlib/grpci2-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRPCI2
0007  *
0008  * @brief This header file defines the GRPCI2 register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/grpci2-header */
0054
0055 #ifndef _GRLIB_GRPCI2_REGS_H
0056 #define _GRLIB_GRPCI2_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/grpci2 */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRPCI2 GRPCI2
0068  *
0069  * @ingroup RTEMSDeviceGRLIB
0070  *
0071  * @brief This group contains the GRPCI2 interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRPCI2CTRL Control register (CTRL)
0078  *
0079  * @brief This group contains register bit definitions.
0080  *
0081  * @{
0082  */
0083
0084 #define GRPCI2_CTRL_RE 0x80000000U
0085
0086 #define GRPCI2_CTRL_MR 0x40000000U
0087
0088 #define GRPCI2_CTRL_TR 0x20000000U
0089
0090 #define GRPCI2_CTRL_SI 0x8000000U
0091
0092 #define GRPCI2_CTRL_PE 0x4000000U
0093
0094 #define GRPCI2_CTRL_ER 0x2000000U
0095
0096 #define GRPCI2_CTRL_EI 0x1000000U
0097
0098 #define GRPCI2_CTRL_BUS_NUMBER_SHIFT 16
0099 #define GRPCI2_CTRL_BUS_NUMBER_MASK 0xff0000U
0100 #define GRPCI2_CTRL_BUS_NUMBER_GET( _reg ) \
0101   ( ( ( _reg ) & GRPCI2_CTRL_BUS_NUMBER_MASK ) >> \
0102     GRPCI2_CTRL_BUS_NUMBER_SHIFT )
0103 #define GRPCI2_CTRL_BUS_NUMBER_SET( _reg, _val ) \
0104   ( ( ( _reg ) & ~GRPCI2_CTRL_BUS_NUMBER_MASK ) | \
0105     ( ( ( _val ) << GRPCI2_CTRL_BUS_NUMBER_SHIFT ) & \
0106       GRPCI2_CTRL_BUS_NUMBER_MASK ) )
0107 #define GRPCI2_CTRL_BUS_NUMBER( _val ) \
0108   ( ( ( _val ) << GRPCI2_CTRL_BUS_NUMBER_SHIFT ) & \
0109     GRPCI2_CTRL_BUS_NUMBER_MASK )
0110
0111 #define GRPCI2_CTRL_DFA 0x800U
0112
0113 #define GRPCI2_CTRL_IB 0x400U
0114
0115 #define GRPCI2_CTRL_CB 0x200U
0116
0117 #define GRPCI2_CTRL_DIF 0x100U
0118
0119 #define GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT 4
0120 #define GRPCI2_CTRL_DEVICE_INT_MASK_MASK 0xf0U
0121 #define GRPCI2_CTRL_DEVICE_INT_MASK_GET( _reg ) \
0122   ( ( ( _reg ) & GRPCI2_CTRL_DEVICE_INT_MASK_MASK ) >> \
0123     GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT )
0124 #define GRPCI2_CTRL_DEVICE_INT_MASK_SET( _reg, _val ) \
0125   ( ( ( _reg ) & ~GRPCI2_CTRL_DEVICE_INT_MASK_MASK ) | \
0126     ( ( ( _val ) << GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT ) & \
0127       GRPCI2_CTRL_DEVICE_INT_MASK_MASK ) )
0128 #define GRPCI2_CTRL_DEVICE_INT_MASK( _val ) \
0129   ( ( ( _val ) << GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT ) & \
0130     GRPCI2_CTRL_DEVICE_INT_MASK_MASK )
0131
0132 #define GRPCI2_CTRL_HOST_INT_MASK_SHIFT 0
0133 #define GRPCI2_CTRL_HOST_INT_MASK_MASK 0xfU
0134 #define GRPCI2_CTRL_HOST_INT_MASK_GET( _reg ) \
0135   ( ( ( _reg ) & GRPCI2_CTRL_HOST_INT_MASK_MASK ) >> \
0136     GRPCI2_CTRL_HOST_INT_MASK_SHIFT )
0137 #define GRPCI2_CTRL_HOST_INT_MASK_SET( _reg, _val ) \
0138   ( ( ( _reg ) & ~GRPCI2_CTRL_HOST_INT_MASK_MASK ) | \
0139     ( ( ( _val ) << GRPCI2_CTRL_HOST_INT_MASK_SHIFT ) & \
0140       GRPCI2_CTRL_HOST_INT_MASK_MASK ) )
0141 #define GRPCI2_CTRL_HOST_INT_MASK( _val ) \
0142   ( ( ( _val ) << GRPCI2_CTRL_HOST_INT_MASK_SHIFT ) & \
0143     GRPCI2_CTRL_HOST_INT_MASK_MASK )
0144
0145 /** @} */
0146
0147 /**
0148  * @defgroup RTEMSDeviceGRPCI2STATCAP Status and Capability register (STATCAP)
0149  *
0150  * @brief This group contains register bit definitions.
0151  *
0152  * @{
0153  */
0154
0155 #define GRPCI2_STATCAP_HOST 0x80000000U
0156
0157 #define GRPCI2_STATCAP_MST 0x40000000U
0158
0159 #define GRPCI2_STATCAP_TAR 0x20000000U
0160
0161 #define GRPCI2_STATCAP_DMA 0x10000000U
0162
0163 #define GRPCI2_STATCAP_DI 0x8000000U
0164
0165 #define GRPCI2_STATCAP_HI 0x4000000U
0166
0167 #define GRPCI2_STATCAP_IRQ_MODE_SHIFT 24
0168 #define GRPCI2_STATCAP_IRQ_MODE_MASK 0x3000000U
0169 #define GRPCI2_STATCAP_IRQ_MODE_GET( _reg ) \
0170   ( ( ( _reg ) & GRPCI2_STATCAP_IRQ_MODE_MASK ) >> \
0171     GRPCI2_STATCAP_IRQ_MODE_SHIFT )
0172 #define GRPCI2_STATCAP_IRQ_MODE_SET( _reg, _val ) \
0173   ( ( ( _reg ) & ~GRPCI2_STATCAP_IRQ_MODE_MASK ) | \
0174     ( ( ( _val ) << GRPCI2_STATCAP_IRQ_MODE_SHIFT ) & \
0175       GRPCI2_STATCAP_IRQ_MODE_MASK ) )
0176 #define GRPCI2_STATCAP_IRQ_MODE( _val ) \
0177   ( ( ( _val ) << GRPCI2_STATCAP_IRQ_MODE_SHIFT ) & \
0178     GRPCI2_STATCAP_IRQ_MODE_MASK )
0179
0180 #define GRPCI2_STATCAP_TRACE 0x800000U
0181
0182 #define GRPCI2_STATCAP_CFGDO 0x100000U
0183
0184 #define GRPCI2_STATCAP_CFGER 0x80000U
0185
0186 #define GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT 12
0187 #define GRPCI2_STATCAP_CORE_INT_STATUS_MASK 0x7f000U
0188 #define GRPCI2_STATCAP_CORE_INT_STATUS_GET( _reg ) \
0189   ( ( ( _reg ) & GRPCI2_STATCAP_CORE_INT_STATUS_MASK ) >> \
0190     GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT )
0191 #define GRPCI2_STATCAP_CORE_INT_STATUS_SET( _reg, _val ) \
0192   ( ( ( _reg ) & ~GRPCI2_STATCAP_CORE_INT_STATUS_MASK ) | \
0193     ( ( ( _val ) << GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT ) & \
0194       GRPCI2_STATCAP_CORE_INT_STATUS_MASK ) )
0195 #define GRPCI2_STATCAP_CORE_INT_STATUS( _val ) \
0196   ( ( ( _val ) << GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT ) & \
0197     GRPCI2_STATCAP_CORE_INT_STATUS_MASK )
0198
0199 #define GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT 8
0200 #define GRPCI2_STATCAP_HOST_INT_STATUS_MASK 0xf00U
0201 #define GRPCI2_STATCAP_HOST_INT_STATUS_GET( _reg ) \
0202   ( ( ( _reg ) & GRPCI2_STATCAP_HOST_INT_STATUS_MASK ) >> \
0203     GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT )
0204 #define GRPCI2_STATCAP_HOST_INT_STATUS_SET( _reg, _val ) \
0205   ( ( ( _reg ) & ~GRPCI2_STATCAP_HOST_INT_STATUS_MASK ) | \
0206     ( ( ( _val ) << GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT ) & \
0207       GRPCI2_STATCAP_HOST_INT_STATUS_MASK ) )
0208 #define GRPCI2_STATCAP_HOST_INT_STATUS( _val ) \
0209   ( ( ( _val ) << GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT ) & \
0210     GRPCI2_STATCAP_HOST_INT_STATUS_MASK )
0211
0212 #define GRPCI2_STATCAP_FDEPTH_SHIFT 2
0213 #define GRPCI2_STATCAP_FDEPTH_MASK 0x1cU
0214 #define GRPCI2_STATCAP_FDEPTH_GET( _reg ) \
0215   ( ( ( _reg ) & GRPCI2_STATCAP_FDEPTH_MASK ) >> \
0216     GRPCI2_STATCAP_FDEPTH_SHIFT )
0217 #define GRPCI2_STATCAP_FDEPTH_SET( _reg, _val ) \
0218   ( ( ( _reg ) & ~GRPCI2_STATCAP_FDEPTH_MASK ) | \
0219     ( ( ( _val ) << GRPCI2_STATCAP_FDEPTH_SHIFT ) & \
0220       GRPCI2_STATCAP_FDEPTH_MASK ) )
0221 #define GRPCI2_STATCAP_FDEPTH( _val ) \
0222   ( ( ( _val ) << GRPCI2_STATCAP_FDEPTH_SHIFT ) & \
0223     GRPCI2_STATCAP_FDEPTH_MASK )
0224
0225 #define GRPCI2_STATCAP_FNUM_SHIFT 0
0226 #define GRPCI2_STATCAP_FNUM_MASK 0x3U
0227 #define GRPCI2_STATCAP_FNUM_GET( _reg ) \
0228   ( ( ( _reg ) & GRPCI2_STATCAP_FNUM_MASK ) >> \
0229     GRPCI2_STATCAP_FNUM_SHIFT )
0230 #define GRPCI2_STATCAP_FNUM_SET( _reg, _val ) \
0231   ( ( ( _reg ) & ~GRPCI2_STATCAP_FNUM_MASK ) | \
0232     ( ( ( _val ) << GRPCI2_STATCAP_FNUM_SHIFT ) & \
0233       GRPCI2_STATCAP_FNUM_MASK ) )
0234 #define GRPCI2_STATCAP_FNUM( _val ) \
0235   ( ( ( _val ) << GRPCI2_STATCAP_FNUM_SHIFT ) & \
0236     GRPCI2_STATCAP_FNUM_MASK )
0237
0238 /** @} */
0239
0240 /**
0241  * @defgroup RTEMSDeviceGRPCI2BCIM PCI master prefetch burst limit (BCIM)
0242  *
0243  * @brief This group contains register bit definitions.
0244  *
0245  * @{
0246  */
0247
0248 #define GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT 16
0249 #define GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK 0xffff0000U
0250 #define GRPCI2_BCIM_AHB_MASTER_UNMASK_GET( _reg ) \
0251   ( ( ( _reg ) & GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK ) >> \
0252     GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT )
0253 #define GRPCI2_BCIM_AHB_MASTER_UNMASK_SET( _reg, _val ) \
0254   ( ( ( _reg ) & ~GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK ) | \
0255     ( ( ( _val ) << GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT ) & \
0256       GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK ) )
0257 #define GRPCI2_BCIM_AHB_MASTER_UNMASK( _val ) \
0258   ( ( ( _val ) << GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT ) & \
0259     GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK )
0260
0261 #define GRPCI2_BCIM_BURST_LENGTH_SHIFT 0
0262 #define GRPCI2_BCIM_BURST_LENGTH_MASK 0xffU
0263 #define GRPCI2_BCIM_BURST_LENGTH_GET( _reg ) \
0264   ( ( ( _reg ) & GRPCI2_BCIM_BURST_LENGTH_MASK ) >> \
0265     GRPCI2_BCIM_BURST_LENGTH_SHIFT )
0266 #define GRPCI2_BCIM_BURST_LENGTH_SET( _reg, _val ) \
0267   ( ( ( _reg ) & ~GRPCI2_BCIM_BURST_LENGTH_MASK ) | \
0268     ( ( ( _val ) << GRPCI2_BCIM_BURST_LENGTH_SHIFT ) & \
0269       GRPCI2_BCIM_BURST_LENGTH_MASK ) )
0270 #define GRPCI2_BCIM_BURST_LENGTH( _val ) \
0271   ( ( ( _val ) << GRPCI2_BCIM_BURST_LENGTH_SHIFT ) & \
0272     GRPCI2_BCIM_BURST_LENGTH_MASK )
0273
0274 /** @} */
0275
0276 /**
0277  * @defgroup RTEMSDeviceGRPCI2AHB2PCI AHB to PCI mapping for PCI IO (AHB2PCI)
0278  *
0279  * @brief This group contains register bit definitions.
0280  *
0281  * @{
0282  */
0283
0284 #define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT 16
0285 #define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK 0xffff0000U
0286 #define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_GET( _reg ) \
0287   ( ( ( _reg ) & GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK ) >> \
0288     GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT )
0289 #define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SET( _reg, _val ) \
0290   ( ( ( _reg ) & ~GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK ) | \
0291     ( ( ( _val ) << GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT ) & \
0292       GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK ) )
0293 #define GRPCI2_AHB2PCI_AHB_TO_PCI_IO( _val ) \
0294   ( ( ( _val ) << GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT ) & \
0295     GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK )
0296
0297 /** @} */
0298
0299 /**
0300  * @defgroup RTEMSDeviceGRPCI2DMACTRL DMA control and status register (DMACTRL)
0301  *
0302  * @brief This group contains register bit definitions.
0303  *
0304  * @{
0305  */
0306
0307 #define GRPCI2_DMACTRL_SAFE 0x80000000U
0308
0309 #define GRPCI2_DMACTRL_CHIRQ_SHIFT 12
0310 #define GRPCI2_DMACTRL_CHIRQ_MASK 0xff000U
0311 #define GRPCI2_DMACTRL_CHIRQ_GET( _reg ) \
0312   ( ( ( _reg ) & GRPCI2_DMACTRL_CHIRQ_MASK ) >> \
0313     GRPCI2_DMACTRL_CHIRQ_SHIFT )
0314 #define GRPCI2_DMACTRL_CHIRQ_SET( _reg, _val ) \
0315   ( ( ( _reg ) & ~GRPCI2_DMACTRL_CHIRQ_MASK ) | \
0316     ( ( ( _val ) << GRPCI2_DMACTRL_CHIRQ_SHIFT ) & \
0317       GRPCI2_DMACTRL_CHIRQ_MASK ) )
0318 #define GRPCI2_DMACTRL_CHIRQ( _val ) \
0319   ( ( ( _val ) << GRPCI2_DMACTRL_CHIRQ_SHIFT ) & \
0320     GRPCI2_DMACTRL_CHIRQ_MASK )
0321
0322 #define GRPCI2_DMACTRL_MA 0x800U
0323
0324 #define GRPCI2_DMACTRL_TA 0x400U
0325
0326 #define GRPCI2_DMACTRL_PE 0x200U
0327
0328 #define GRPCI2_DMACTRL_AE 0x100U
0329
0330 #define GRPCI2_DMACTRL_DE 0x80U
0331
0332 #define GRPCI2_DMACTRL_NUMCH_SHIFT 4
0333 #define GRPCI2_DMACTRL_NUMCH_MASK 0x70U
0334 #define GRPCI2_DMACTRL_NUMCH_GET( _reg ) \
0335   ( ( ( _reg ) & GRPCI2_DMACTRL_NUMCH_MASK ) >> \
0336     GRPCI2_DMACTRL_NUMCH_SHIFT )
0337 #define GRPCI2_DMACTRL_NUMCH_SET( _reg, _val ) \
0338   ( ( ( _reg ) & ~GRPCI2_DMACTRL_NUMCH_MASK ) | \
0339     ( ( ( _val ) << GRPCI2_DMACTRL_NUMCH_SHIFT ) & \
0340       GRPCI2_DMACTRL_NUMCH_MASK ) )
0341 #define GRPCI2_DMACTRL_NUMCH( _val ) \
0342   ( ( ( _val ) << GRPCI2_DMACTRL_NUMCH_SHIFT ) & \
0343     GRPCI2_DMACTRL_NUMCH_MASK )
0344
0345 #define GRPCI2_DMACTRL_ACTIVE 0x8U
0346
0347 #define GRPCI2_DMACTRL_DIS 0x4U
0348
0349 #define GRPCI2_DMACTRL_IE 0x2U
0350
0351 #define GRPCI2_DMACTRL_EN 0x1U
0352
0353 /** @} */
0354
0355 /**
0356  * @defgroup RTEMSDeviceGRPCI2DMABASE \
0357  *   DMA descriptor base address register (DMABASE)
0358  *
0359  * @brief This group contains register bit definitions.
0360  *
0361  * @{
0362  */
0363
0364 #define GRPCI2_DMABASE_BASE_SHIFT 0
0365 #define GRPCI2_DMABASE_BASE_MASK 0xffffffffU
0366 #define GRPCI2_DMABASE_BASE_GET( _reg ) \
0367   ( ( ( _reg ) & GRPCI2_DMABASE_BASE_MASK ) >> \
0368     GRPCI2_DMABASE_BASE_SHIFT )
0369 #define GRPCI2_DMABASE_BASE_SET( _reg, _val ) \
0370   ( ( ( _reg ) & ~GRPCI2_DMABASE_BASE_MASK ) | \
0371     ( ( ( _val ) << GRPCI2_DMABASE_BASE_SHIFT ) & \
0372       GRPCI2_DMABASE_BASE_MASK ) )
0373 #define GRPCI2_DMABASE_BASE( _val ) \
0374   ( ( ( _val ) << GRPCI2_DMABASE_BASE_SHIFT ) & \
0375     GRPCI2_DMABASE_BASE_MASK )
0376
0377 /** @} */
0378
0379 /**
0380  * @defgroup RTEMSDeviceGRPCI2DMACHAN DMA channel active register (DMACHAN)
0381  *
0382  * @brief This group contains register bit definitions.
0383  *
0384  * @{
0385  */
0386
0387 #define GRPCI2_DMACHAN_CHAN_SHIFT 0
0388 #define GRPCI2_DMACHAN_CHAN_MASK 0xffffffffU
0389 #define GRPCI2_DMACHAN_CHAN_GET( _reg ) \
0390   ( ( ( _reg ) & GRPCI2_DMACHAN_CHAN_MASK ) >> \
0391     GRPCI2_DMACHAN_CHAN_SHIFT )
0392 #define GRPCI2_DMACHAN_CHAN_SET( _reg, _val ) \
0393   ( ( ( _reg ) & ~GRPCI2_DMACHAN_CHAN_MASK ) | \
0394     ( ( ( _val ) << GRPCI2_DMACHAN_CHAN_SHIFT ) & \
0395       GRPCI2_DMACHAN_CHAN_MASK ) )
0396 #define GRPCI2_DMACHAN_CHAN( _val ) \
0397   ( ( ( _val ) << GRPCI2_DMACHAN_CHAN_SHIFT ) & \
0398     GRPCI2_DMACHAN_CHAN_MASK )
0399
0400 /** @} */
0401
0402 /**
0403  * @defgroup RTEMSDeviceGRPCI2PCI2AHB \
0404  *   PCI BAR to AHB address mapping register (PCI2AHB)
0405  *
0406  * @brief This group contains register bit definitions.
0407  *
0408  * @{
0409  */
0410
0411 #define GRPCI2_PCI2AHB_ADDR_SHIFT 0
0412 #define GRPCI2_PCI2AHB_ADDR_MASK 0xffffffffU
0413 #define GRPCI2_PCI2AHB_ADDR_GET( _reg ) \
0414   ( ( ( _reg ) & GRPCI2_PCI2AHB_ADDR_MASK ) >> \
0415     GRPCI2_PCI2AHB_ADDR_SHIFT )
0416 #define GRPCI2_PCI2AHB_ADDR_SET( _reg, _val ) \
0417   ( ( ( _reg ) & ~GRPCI2_PCI2AHB_ADDR_MASK ) | \
0418     ( ( ( _val ) << GRPCI2_PCI2AHB_ADDR_SHIFT ) & \
0419       GRPCI2_PCI2AHB_ADDR_MASK ) )
0420 #define GRPCI2_PCI2AHB_ADDR( _val ) \
0421   ( ( ( _val ) << GRPCI2_PCI2AHB_ADDR_SHIFT ) & \
0422     GRPCI2_PCI2AHB_ADDR_MASK )
0423
0424 /** @} */
0425
0426 /**
0427  * @defgroup RTEMSDeviceGRPCI2AHBM2PCI \
0428  *   AHB master to PCI memory address mapping register (AHBM2PCI)
0429  *
0430  * @brief This group contains register bit definitions.
0431  *
0432  * @{
0433  */
0434
0435 #define GRPCI2_AHBM2PCI_ADDR_SHIFT 0
0436 #define GRPCI2_AHBM2PCI_ADDR_MASK 0xffffffffU
0437 #define GRPCI2_AHBM2PCI_ADDR_GET( _reg ) \
0438   ( ( ( _reg ) & GRPCI2_AHBM2PCI_ADDR_MASK ) >> \
0439     GRPCI2_AHBM2PCI_ADDR_SHIFT )
0440 #define GRPCI2_AHBM2PCI_ADDR_SET( _reg, _val ) \
0441   ( ( ( _reg ) & ~GRPCI2_AHBM2PCI_ADDR_MASK ) | \
0442     ( ( ( _val ) << GRPCI2_AHBM2PCI_ADDR_SHIFT ) & \
0443       GRPCI2_AHBM2PCI_ADDR_MASK ) )
0444 #define GRPCI2_AHBM2PCI_ADDR( _val ) \
0445   ( ( ( _val ) << GRPCI2_AHBM2PCI_ADDR_SHIFT ) & \
0446     GRPCI2_AHBM2PCI_ADDR_MASK )
0447
0448 /** @} */
0449
0450 /**
0451  * @defgroup RTEMSDeviceGRPCI2TCTRC \
0452  *   PCI trace Control and Status register (TCTRC)
0453  *
0454  * @brief This group contains register bit definitions.
0455  *
0456  * @{
0457  */
0458
0459 #define GRPCI2_TCTRC_TRIG_INDEX_SHIFT 16
0460 #define GRPCI2_TCTRC_TRIG_INDEX_MASK 0xffff0000U
0461 #define GRPCI2_TCTRC_TRIG_INDEX_GET( _reg ) \
0462   ( ( ( _reg ) & GRPCI2_TCTRC_TRIG_INDEX_MASK ) >> \
0463     GRPCI2_TCTRC_TRIG_INDEX_SHIFT )
0464 #define GRPCI2_TCTRC_TRIG_INDEX_SET( _reg, _val ) \
0465   ( ( ( _reg ) & ~GRPCI2_TCTRC_TRIG_INDEX_MASK ) | \
0466     ( ( ( _val ) << GRPCI2_TCTRC_TRIG_INDEX_SHIFT ) & \
0467       GRPCI2_TCTRC_TRIG_INDEX_MASK ) )
0468 #define GRPCI2_TCTRC_TRIG_INDEX( _val ) \
0469   ( ( ( _val ) << GRPCI2_TCTRC_TRIG_INDEX_SHIFT ) & \
0470     GRPCI2_TCTRC_TRIG_INDEX_MASK )
0471
0472 #define GRPCI2_TCTRC_AR 0x8000U
0473
0474 #define GRPCI2_TCTRC_EN 0x4000U
0475
0476 #define GRPCI2_TCTRC_DEPTH_SHIFT 4
0477 #define GRPCI2_TCTRC_DEPTH_MASK 0xff0U
0478 #define GRPCI2_TCTRC_DEPTH_GET( _reg ) \
0479   ( ( ( _reg ) & GRPCI2_TCTRC_DEPTH_MASK ) >> \
0480     GRPCI2_TCTRC_DEPTH_SHIFT )
0481 #define GRPCI2_TCTRC_DEPTH_SET( _reg, _val ) \
0482   ( ( ( _reg ) & ~GRPCI2_TCTRC_DEPTH_MASK ) | \
0483     ( ( ( _val ) << GRPCI2_TCTRC_DEPTH_SHIFT ) & \
0484       GRPCI2_TCTRC_DEPTH_MASK ) )
0485 #define GRPCI2_TCTRC_DEPTH( _val ) \
0486   ( ( ( _val ) << GRPCI2_TCTRC_DEPTH_SHIFT ) & \
0487     GRPCI2_TCTRC_DEPTH_MASK )
0488
0489 #define GRPCI2_TCTRC_SO 0x2U
0490
0491 #define GRPCI2_TCTRC_SA 0x1U
0492
0493 /** @} */
0494
0495 /**
0496  * @defgroup RTEMSDeviceGRPCI2TMODE PCI trace counter and mode register (TMODE)
0497  *
0498  * @brief This group contains register bit definitions.
0499  *
0500  * @{
0501  */
0502
0503 #define GRPCI2_TMODE_TRACING_MODE_SHIFT 24
0504 #define GRPCI2_TMODE_TRACING_MODE_MASK 0xf000000U
0505 #define GRPCI2_TMODE_TRACING_MODE_GET( _reg ) \
0506   ( ( ( _reg ) & GRPCI2_TMODE_TRACING_MODE_MASK ) >> \
0507     GRPCI2_TMODE_TRACING_MODE_SHIFT )
0508 #define GRPCI2_TMODE_TRACING_MODE_SET( _reg, _val ) \
0509   ( ( ( _reg ) & ~GRPCI2_TMODE_TRACING_MODE_MASK ) | \
0510     ( ( ( _val ) << GRPCI2_TMODE_TRACING_MODE_SHIFT ) & \
0511       GRPCI2_TMODE_TRACING_MODE_MASK ) )
0512 #define GRPCI2_TMODE_TRACING_MODE( _val ) \
0513   ( ( ( _val ) << GRPCI2_TMODE_TRACING_MODE_SHIFT ) & \
0514     GRPCI2_TMODE_TRACING_MODE_MASK )
0515
0516 #define GRPCI2_TMODE_TRIG_COUNT_SHIFT 16
0517 #define GRPCI2_TMODE_TRIG_COUNT_MASK 0xff0000U
0518 #define GRPCI2_TMODE_TRIG_COUNT_GET( _reg ) \
0519   ( ( ( _reg ) & GRPCI2_TMODE_TRIG_COUNT_MASK ) >> \
0520     GRPCI2_TMODE_TRIG_COUNT_SHIFT )
0521 #define GRPCI2_TMODE_TRIG_COUNT_SET( _reg, _val ) \
0522   ( ( ( _reg ) & ~GRPCI2_TMODE_TRIG_COUNT_MASK ) | \
0523     ( ( ( _val ) << GRPCI2_TMODE_TRIG_COUNT_SHIFT ) & \
0524       GRPCI2_TMODE_TRIG_COUNT_MASK ) )
0525 #define GRPCI2_TMODE_TRIG_COUNT( _val ) \
0526   ( ( ( _val ) << GRPCI2_TMODE_TRIG_COUNT_SHIFT ) & \
0527     GRPCI2_TMODE_TRIG_COUNT_MASK )
0528
0529 #define GRPCI2_TMODE_DELAYED_STOP_SHIFT 0
0530 #define GRPCI2_TMODE_DELAYED_STOP_MASK 0xffffU
0531 #define GRPCI2_TMODE_DELAYED_STOP_GET( _reg ) \
0532   ( ( ( _reg ) & GRPCI2_TMODE_DELAYED_STOP_MASK ) >> \
0533     GRPCI2_TMODE_DELAYED_STOP_SHIFT )
0534 #define GRPCI2_TMODE_DELAYED_STOP_SET( _reg, _val ) \
0535   ( ( ( _reg ) & ~GRPCI2_TMODE_DELAYED_STOP_MASK ) | \
0536     ( ( ( _val ) << GRPCI2_TMODE_DELAYED_STOP_SHIFT ) & \
0537       GRPCI2_TMODE_DELAYED_STOP_MASK ) )
0538 #define GRPCI2_TMODE_DELAYED_STOP( _val ) \
0539   ( ( ( _val ) << GRPCI2_TMODE_DELAYED_STOP_SHIFT ) & \
0540     GRPCI2_TMODE_DELAYED_STOP_MASK )
0541
0542 /** @} */
0543
0544 /**
0545  * @defgroup RTEMSDeviceGRPCI2TADP PCI trace AD pattern register (TADP)
0546  *
0547  * @brief This group contains register bit definitions.
0548  *
0549  * @{
0550  */
0551
0552 #define GRPCI2_TADP_PATTERN_SHIFT 0
0553 #define GRPCI2_TADP_PATTERN_MASK 0xffffffffU
0554 #define GRPCI2_TADP_PATTERN_GET( _reg ) \
0555   ( ( ( _reg ) & GRPCI2_TADP_PATTERN_MASK ) >> \
0556     GRPCI2_TADP_PATTERN_SHIFT )
0557 #define GRPCI2_TADP_PATTERN_SET( _reg, _val ) \
0558   ( ( ( _reg ) & ~GRPCI2_TADP_PATTERN_MASK ) | \
0559     ( ( ( _val ) << GRPCI2_TADP_PATTERN_SHIFT ) & \
0560       GRPCI2_TADP_PATTERN_MASK ) )
0561 #define GRPCI2_TADP_PATTERN( _val ) \
0562   ( ( ( _val ) << GRPCI2_TADP_PATTERN_SHIFT ) & \
0563     GRPCI2_TADP_PATTERN_MASK )
0564
0565 /** @} */
0566
0567 /**
0568  * @defgroup RTEMSDeviceGRPCI2TADM PCI trace AD mask register (TADM)
0569  *
0570  * @brief This group contains register bit definitions.
0571  *
0572  * @{
0573  */
0574
0575 #define GRPCI2_TADM_MASK_SHIFT 0
0576 #define GRPCI2_TADM_MASK_MASK 0xffffffffU
0577 #define GRPCI2_TADM_MASK_GET( _reg ) \
0578   ( ( ( _reg ) & GRPCI2_TADM_MASK_MASK ) >> \
0579     GRPCI2_TADM_MASK_SHIFT )
0580 #define GRPCI2_TADM_MASK_SET( _reg, _val ) \
0581   ( ( ( _reg ) & ~GRPCI2_TADM_MASK_MASK ) | \
0582     ( ( ( _val ) << GRPCI2_TADM_MASK_SHIFT ) & \
0583       GRPCI2_TADM_MASK_MASK ) )
0584 #define GRPCI2_TADM_MASK( _val ) \
0585   ( ( ( _val ) << GRPCI2_TADM_MASK_SHIFT ) & \
0586     GRPCI2_TADM_MASK_MASK )
0587
0588 /** @} */
0589
0590 /**
0591  * @defgroup RTEMSDeviceGRPCI2TCP PCI trace Ctrl signal pattern register (TCP)
0592  *
0593  * @brief This group contains register bit definitions.
0594  *
0595  * @{
0596  */
0597
0598 #define GRPCI2_TCP_CBE_3_0_SHIFT 16
0599 #define GRPCI2_TCP_CBE_3_0_MASK 0xf0000U
0600 #define GRPCI2_TCP_CBE_3_0_GET( _reg ) \
0601   ( ( ( _reg ) & GRPCI2_TCP_CBE_3_0_MASK ) >> \
0602     GRPCI2_TCP_CBE_3_0_SHIFT )
0603 #define GRPCI2_TCP_CBE_3_0_SET( _reg, _val ) \
0604   ( ( ( _reg ) & ~GRPCI2_TCP_CBE_3_0_MASK ) | \
0605     ( ( ( _val ) << GRPCI2_TCP_CBE_3_0_SHIFT ) & \
0606       GRPCI2_TCP_CBE_3_0_MASK ) )
0607 #define GRPCI2_TCP_CBE_3_0( _val ) \
0608   ( ( ( _val ) << GRPCI2_TCP_CBE_3_0_SHIFT ) & \
0609     GRPCI2_TCP_CBE_3_0_MASK )
0610
0611 #define GRPCI2_TCP_FRAME 0x8000U
0612
0613 #define GRPCI2_TCP_IRDY 0x4000U
0614
0615 #define GRPCI2_TCP_TRDY 0x2000U
0616
0617 #define GRPCI2_TCP_STOP 0x1000U
0618
0619 #define GRPCI2_TCP_DEVSEL 0x800U
0620
0621 #define GRPCI2_TCP_PAR 0x400U
0622
0623 #define GRPCI2_TCP_PERR 0x200U
0624
0625 #define GRPCI2_TCP_SERR 0x100U
0626
0627 #define GRPCI2_TCP_IDSEL 0x80U
0628
0629 #define GRPCI2_TCP_REQ 0x40U
0630
0631 #define GRPCI2_TCP_GNT 0x20U
0632
0633 #define GRPCI2_TCP_LOCK 0x10U
0634
0635 #define GRPCI2_TCP_RST 0x8U
0636
0637 /** @} */
0638
0639 /**
0640  * @defgroup RTEMSDeviceGRPCI2TCM PCI trace Ctrl signal mask register (TCM)
0641  *
0642  * @brief This group contains register bit definitions.
0643  *
0644  * @{
0645  */
0646
0647 #define GRPCI2_TCM_CBE_3_0_SHIFT 16
0648 #define GRPCI2_TCM_CBE_3_0_MASK 0xf0000U
0649 #define GRPCI2_TCM_CBE_3_0_GET( _reg ) \
0650   ( ( ( _reg ) & GRPCI2_TCM_CBE_3_0_MASK ) >> \
0651     GRPCI2_TCM_CBE_3_0_SHIFT )
0652 #define GRPCI2_TCM_CBE_3_0_SET( _reg, _val ) \
0653   ( ( ( _reg ) & ~GRPCI2_TCM_CBE_3_0_MASK ) | \
0654     ( ( ( _val ) << GRPCI2_TCM_CBE_3_0_SHIFT ) & \
0655       GRPCI2_TCM_CBE_3_0_MASK ) )
0656 #define GRPCI2_TCM_CBE_3_0( _val ) \
0657   ( ( ( _val ) << GRPCI2_TCM_CBE_3_0_SHIFT ) & \
0658     GRPCI2_TCM_CBE_3_0_MASK )
0659
0660 #define GRPCI2_TCM_FRAME 0x8000U
0661
0662 #define GRPCI2_TCM_IRDY 0x4000U
0663
0664 #define GRPCI2_TCM_TRDY 0x2000U
0665
0666 #define GRPCI2_TCM_STOP 0x1000U
0667
0668 #define GRPCI2_TCM_DEVSEL 0x800U
0669
0670 #define GRPCI2_TCM_PAR 0x400U
0671
0672 #define GRPCI2_TCM_PERR 0x200U
0673
0674 #define GRPCI2_TCM_SERR 0x100U
0675
0676 #define GRPCI2_TCM_IDSEL 0x80U
0677
0678 #define GRPCI2_TCM_REQ 0x40U
0679
0680 #define GRPCI2_TCM_GNT 0x20U
0681
0682 #define GRPCI2_TCM_LOCK 0x10U
0683
0684 #define GRPCI2_TCM_RST 0x8U
0685
0686 /** @} */
0687
0688 /**
0689  * @defgroup RTEMSDeviceGRPCI2TADS PCI trace PCI AD state register (TADS)
0690  *
0691  * @brief This group contains register bit definitions.
0692  *
0693  * @{
0694  */
0695
0696 #define GRPCI2_TADS_SIGNAL_SHIFT 0
0697 #define GRPCI2_TADS_SIGNAL_MASK 0xffffffffU
0698 #define GRPCI2_TADS_SIGNAL_GET( _reg ) \
0699   ( ( ( _reg ) & GRPCI2_TADS_SIGNAL_MASK ) >> \
0700     GRPCI2_TADS_SIGNAL_SHIFT )
0701 #define GRPCI2_TADS_SIGNAL_SET( _reg, _val ) \
0702   ( ( ( _reg ) & ~GRPCI2_TADS_SIGNAL_MASK ) | \
0703     ( ( ( _val ) << GRPCI2_TADS_SIGNAL_SHIFT ) & \
0704       GRPCI2_TADS_SIGNAL_MASK ) )
0705 #define GRPCI2_TADS_SIGNAL( _val ) \
0706   ( ( ( _val ) << GRPCI2_TADS_SIGNAL_SHIFT ) & \
0707     GRPCI2_TADS_SIGNAL_MASK )
0708
0709 /** @} */
0710
0711 /**
0712  * @defgroup RTEMSDeviceGRPCI2TCS \
0713  *   PCI trace PCI Ctrl signal state register (TCS)
0714  *
0715  * @brief This group contains register bit definitions.
0716  *
0717  * @{
0718  */
0719
0720 #define GRPCI2_TCS_CBE_3_0_SHIFT 16
0721 #define GRPCI2_TCS_CBE_3_0_MASK 0xf0000U
0722 #define GRPCI2_TCS_CBE_3_0_GET( _reg ) \
0723   ( ( ( _reg ) & GRPCI2_TCS_CBE_3_0_MASK ) >> \
0724     GRPCI2_TCS_CBE_3_0_SHIFT )
0725 #define GRPCI2_TCS_CBE_3_0_SET( _reg, _val ) \
0726   ( ( ( _reg ) & ~GRPCI2_TCS_CBE_3_0_MASK ) | \
0727     ( ( ( _val ) << GRPCI2_TCS_CBE_3_0_SHIFT ) & \
0728       GRPCI2_TCS_CBE_3_0_MASK ) )
0729 #define GRPCI2_TCS_CBE_3_0( _val ) \
0730   ( ( ( _val ) << GRPCI2_TCS_CBE_3_0_SHIFT ) & \
0731     GRPCI2_TCS_CBE_3_0_MASK )
0732
0733 #define GRPCI2_TCS_FRAME 0x8000U
0734
0735 #define GRPCI2_TCS_IRDY 0x4000U
0736
0737 #define GRPCI2_TCS_TRDY 0x2000U
0738
0739 #define GRPCI2_TCS_STOP 0x1000U
0740
0741 #define GRPCI2_TCS_DEVSEL 0x800U
0742
0743 #define GRPCI2_TCS_PAR 0x400U
0744
0745 #define GRPCI2_TCS_PERR 0x200U
0746
0747 #define GRPCI2_TCS_SERR 0x100U
0748
0749 #define GRPCI2_TCS_IDSEL 0x80U
0750
0751 #define GRPCI2_TCS_REQ 0x40U
0752
0753 #define GRPCI2_TCS_GNT 0x20U
0754
0755 #define GRPCI2_TCS_LOCK 0x10U
0756
0757 #define GRPCI2_TCS_RST 0x8U
0758
0759 /** @} */
0760
0761 /**
0762  * @brief This structure defines the GRPCI2 register block memory map.
0763  */
0764 typedef struct grpci2 {
0765   /**
0766    * @brief See @ref RTEMSDeviceGRPCI2CTRL.
0767    */
0768   uint32_t ctrl;
0769
0770   /**
0771    * @brief See @ref RTEMSDeviceGRPCI2STATCAP.
0772    */
0773   uint32_t statcap;
0774
0775   /**
0776    * @brief See @ref RTEMSDeviceGRPCI2BCIM.
0777    */
0778   uint32_t bcim;
0779
0780   /**
0781    * @brief See @ref RTEMSDeviceGRPCI2AHB2PCI.
0782    */
0783   uint32_t ahb2pci;
0784
0785   /**
0786    * @brief See @ref RTEMSDeviceGRPCI2DMACTRL.
0787    */
0788   uint32_t dmactrl;
0789
0790   /**
0791    * @brief See @ref RTEMSDeviceGRPCI2DMABASE.
0792    */
0793   uint32_t dmabase;
0794
0795   /**
0796    * @brief See @ref RTEMSDeviceGRPCI2DMACHAN.
0797    */
0798   uint32_t dmachan;
0799
0800   uint32_t reserved_1c_20;
0801
0802   /**
0803    * @brief See @ref RTEMSDeviceGRPCI2PCI2AHB.
0804    */
0805   uint32_t pci2ahb_0;
0806
0807   uint32_t reserved_24_34[ 4 ];
0808
0809   /**
0810    * @brief See @ref RTEMSDeviceGRPCI2PCI2AHB.
0811    */
0812   uint32_t pci2ahb_1;
0813
0814   uint32_t reserved_38_40[ 2 ];
0815
0816   /**
0817    * @brief See @ref RTEMSDeviceGRPCI2AHBM2PCI.
0818    */
0819   uint32_t ahbm2pci_0;
0820
0821   uint32_t reserved_44_7c[ 14 ];
0822
0823   /**
0824    * @brief See @ref RTEMSDeviceGRPCI2AHBM2PCI.
0825    */
0826   uint32_t ahbm2pci_1;
0827
0828   /**
0829    * @brief See @ref RTEMSDeviceGRPCI2TCTRC.
0830    */
0831   uint32_t tctrc;
0832
0833   /**
0834    * @brief See @ref RTEMSDeviceGRPCI2TMODE.
0835    */
0836   uint32_t tmode;
0837
0838   /**
0839    * @brief See @ref RTEMSDeviceGRPCI2TADP.
0840    */
0841   uint32_t tadp;
0842
0843   /**
0844    * @brief See @ref RTEMSDeviceGRPCI2TADM.
0845    */
0846   uint32_t tadm;
0847
0848   /**
0849    * @brief See @ref RTEMSDeviceGRPCI2TCP.
0850    */
0851   uint32_t tcp;
0852
0853   /**
0854    * @brief See @ref RTEMSDeviceGRPCI2TCM.
0855    */
0856   uint32_t tcm;
0857
0858   /**
0859    * @brief See @ref RTEMSDeviceGRPCI2TADS.
0860    */
0861   uint32_t tads;
0862
0863   /**
0864    * @brief See @ref RTEMSDeviceGRPCI2TCS.
0865    */
0866   uint32_t tcs;
0867 } grpci2;
0868
0869 /** @} */
0870
0871 #ifdef __cplusplus
0872 }
0873 #endif
0874
0875 #endif /* _GRLIB_GRPCI2_REGS_H */