include/grlib/grlib.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  * @ingroup amba
0006  * @brief Common GRLIB AMBA Core Register definitions
0007  */
0008
0009 /*
0010  *  COPYRIGHT (c) 2012
0011  *  Aeroflex Gaisler
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  * 1. Redistributions of source code must retain the above copyright
0017  *    notice, this list of conditions and the following disclaimer.
0018  * 2. Redistributions in binary form must reproduce the above copyright
0019  *    notice, this list of conditions and the following disclaimer in the
0020  *    documentation and/or other materials provided with the distribution.
0021  *
0022  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0023  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0024  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0025  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0026  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0027  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0028  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0029  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0030  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0031  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0032  * POSSIBILITY OF SUCH DAMAGE.
0033  */
0034
0035 #ifndef __GRLIB_H__
0036 #define __GRLIB_H__
0037
0038 #include <stdbool.h>
0039
0040 #ifdef __cplusplus
0041 extern "C" {
0042 #endif
0043
0044 /**
0045  * @defgroup RTEMSBSPsSharedGRLIB GRLIB
0046  *
0047  * @ingroup RTEMSBSPsShared
0048  *
0049  * @brief Driver support for GRLIB IP Library.
0050  */
0051
0052 /* ESA MEMORY CONTROLLER */
0053 struct mctrl_regs {
0054   unsigned int mcfg1;
0055   unsigned int mcfg2;
0056   unsigned int mcfg3;
0057 };
0058
0059 /* APB UART */
0060 struct apbuart_regs {
0061   volatile unsigned int data;
0062   volatile unsigned int status;
0063   volatile unsigned int ctrl;
0064   volatile unsigned int scaler;
0065 };
0066
0067 /* IRQMP and IRQAMP interrupt controller timestamps */
0068 struct irqmp_timestamp_regs {
0069   volatile unsigned int counter;     /* 0x00 */
0070   volatile unsigned int control;     /* 0x04 */
0071   volatile unsigned int assertion;   /* 0x08 */
0072   volatile unsigned int ack;         /* 0x0c */
0073 };
0074
0075 static inline bool irqmp_has_timestamp(
0076   volatile struct irqmp_timestamp_regs *irqmp_ts
0077 )
0078 {
0079   return (irqmp_ts->control >> 27) > 0;
0080 }
0081
0082 /* IRQMP and IRQAMP interrupt controllers */
0083 struct irqmp_regs {
0084   volatile unsigned int ilevel;      /* 0x00 */
0085   volatile unsigned int ipend;       /* 0x04 */
0086   volatile unsigned int iforce;      /* 0x08 */
0087   volatile unsigned int iclear;      /* 0x0c */
0088   volatile unsigned int mpstat;      /* 0x10 */
0089   volatile unsigned int bcast;       /* 0x14 */
0090   volatile unsigned int notused02;   /* 0x18 */
0091   volatile unsigned int wdgctrl;     /* 0x1c */
0092   volatile unsigned int ampctrl;     /* 0x20 */
0093   volatile unsigned int icsel[2];    /* 0x24,0x28 */
0094   volatile unsigned int notused13;   /* 0x2c */
0095   volatile unsigned int notused20;   /* 0x30 */
0096   volatile unsigned int notused21;   /* 0x34 */
0097   volatile unsigned int notused22;   /* 0x38 */
0098   volatile unsigned int notused23;   /* 0x3c */
0099   volatile unsigned int mask[16];    /* 0x40 */
0100   volatile unsigned int force[16];   /* 0x80 */
0101   /* Extended IRQ registers */
0102   volatile unsigned int intid[16];   /* 0xc0 */
0103   volatile struct irqmp_timestamp_regs timestamp[16]; /* 0x100 */
0104   volatile unsigned int resetaddr[4]; /* 0x200 */
0105   volatile unsigned int resv0[12];    /* 0x210 - 0x23C */
0106   volatile unsigned int pboot;        /* 0x240 */
0107   volatile unsigned int resv1[47];    /* 0x244 - 0x2FC */
0108   volatile unsigned int irqmap[8];    /* 0x300 - 0x31C */
0109   volatile unsigned int resv2[824];   /* 0x320 - 0x1000 */
0110 };
0111
0112 /* GPTIMER Timer instance */
0113 struct gptimer_timer_regs {
0114   volatile unsigned int value;
0115   volatile unsigned int reload;
0116   volatile unsigned int ctrl;
0117   volatile unsigned int notused;
0118 };
0119
0120 #define GPTIMER_TIMER_CTRL_EN 0x00000001U
0121 #define GPTIMER_TIMER_CTRL_RS 0x00000002U
0122 #define GPTIMER_TIMER_CTRL_LD 0x00000004U
0123 #define GPTIMER_TIMER_CTRL_IE 0x00000008U
0124 #define GPTIMER_TIMER_CTRL_IP 0x00000010U
0125 #define GPTIMER_TIMER_CTRL_CH 0x00000020U
0126 #define GPTIMER_TIMER_CTRL_DH 0x00000040U
0127
0128 /* GPTIMER common registers */
0129 struct gptimer_regs {
0130   volatile unsigned int scaler_value;   /* common timer registers */
0131   volatile unsigned int scaler_reload;
0132   volatile unsigned int cfg;
0133   volatile unsigned int notused;
0134   struct gptimer_timer_regs timer[7];
0135 };
0136
0137 /* GRGPIO GPIO */
0138 struct grgpio_regs {
0139   volatile unsigned int data;        /* 0x00 I/O port data register */
0140   volatile unsigned int output;      /* 0x04 I/O port output register */
0141   volatile unsigned int dir;         /* 0x08 I/O port direction register */
0142   volatile unsigned int imask;       /* 0x0C Interrupt mask register */
0143   volatile unsigned int ipol;        /* 0x10 Interrupt polarity register */
0144   volatile unsigned int iedge;       /* 0x14 Interrupt edge register */
0145   volatile unsigned int bypass;      /* 0x18 Bypass register */
0146   volatile unsigned int cap;         /* 0x1C Capability register */
0147   volatile unsigned int irqmap[4];   /* 0x20 - 0x2C Interrupt map registers */
0148   volatile unsigned int res_30;      /* 0x30 Reserved */
0149   volatile unsigned int res_34;      /* 0x34 Reserved */
0150   volatile unsigned int res_38;      /* 0x38 Reserved */
0151   volatile unsigned int res_3C;      /* 0x3C Reserved */
0152   volatile unsigned int iavail;      /* 0x40 Interrupt available register */
0153   volatile unsigned int iflag;       /* 0x44 Interrupt flag register */
0154   volatile unsigned int res_48;      /* 0x48 Reserved */
0155   volatile unsigned int pulse;       /* 0x4C Pulse register */
0156   volatile unsigned int res_50;      /* 0x50 Reserved */
0157   volatile unsigned int output_or;   /* 0x54 I/O port output register, logical-OR */
0158   volatile unsigned int dir_or;      /* 0x58 I/O port direction register, logical-OR */
0159   volatile unsigned int imask_or;    /* 0x5C Interrupt mask register, logical-OR */
0160   volatile unsigned int res_60;      /* 0x60 Reserved */
0161   volatile unsigned int output_and;  /* 0x64 I/O port output register, logical-AND */
0162   volatile unsigned int dir_and;     /* 0x68 I/O port direction register, logical-AND */
0163   volatile unsigned int imask_and;   /* 0x6C Interrupt mask register, logical-AND */
0164   volatile unsigned int res_70;      /* 0x70 Reserved */
0165   volatile unsigned int output_xor;  /* 0x74 I/O port output register, logical-XOR */
0166   volatile unsigned int dir_xor;     /* 0x78 I/O port direction register, logical-XOR */
0167   volatile unsigned int imask_xor;   /* 0x7C Interrupt mask register, logical-XOR */
0168 };
0169
0170 /* L2C - Level 2 Cache Controller registers */
0171 struct l2c_regs {
0172   volatile unsigned int control;                /* 0x00 Control register */
0173   volatile unsigned int status;                 /* 0x04 Status register */
0174   volatile unsigned int flush_mem_addr;         /* 0x08 Flush (Memory address) */
0175   volatile unsigned int flush_set_index;        /* 0x0c Flush (set, index) */
0176   volatile unsigned int access_counter;         /* 0x10 */
0177   volatile unsigned int hit_counter;            /* 0x14 */
0178   volatile unsigned int bus_cycle_counter;      /* 0x18 */
0179   volatile unsigned int bus_usage_counter;      /* 0x1c */
0180   volatile unsigned int error_status_control;   /* 0x20 Error status/control */
0181   volatile unsigned int error_addr;             /* 0x24 Error address */
0182   volatile unsigned int tag_check_bit;          /* 0x28 TAG-check-bit */
0183   volatile unsigned int data_check_bit;         /* 0x2c Data-check-bit */
0184   volatile unsigned int scrub_control_status;   /* 0x30 Scrub Control/Status */
0185   volatile unsigned int scrub_delay;            /* 0x34 Scrub Delay */
0186   volatile unsigned int error_injection;        /* 0x38 Error injection */
0187   volatile unsigned int access_control;         /* 0x3c Access control */
0188   volatile unsigned int reserved_40[16];        /* 0x40 Reserved */
0189   volatile unsigned int mtrr[32];               /* 0x80 - 0xFC MTRR registers */
0190   volatile unsigned int reserved_100[131008];   /* 0x100 Reserved */
0191   volatile unsigned int diag_iface_tag[16384];  /* 0x80000 - 0x8FFFC Diagnostic interface (Tag) */
0192   volatile unsigned int reserved_90000[376832]; /* 0x90000 Reserved */
0193   volatile unsigned int diag_iface_data[524288];/* 0x200000 - 0x3FFFFC Diagnostic interface (Data) */
0194 };
0195
0196 #ifdef __cplusplus
0197 }
0198 #endif
0199
0200 #endif