include/grlib/griommu-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRIOMMU
0007  *
0008  * @brief This header file defines the GRIOMMU register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/griommu-header */
0054
0055 #ifndef _GRLIB_GRIOMMU_REGS_H
0056 #define _GRLIB_GRIOMMU_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/griommu */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRIOMMU GRIOMMU
0068  *
0069  * @ingroup RTEMSDeviceGRLIB
0070  *
0071  * @brief This group contains the GRIOMMU interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRIOMMUCAP0 Capability register 0 (CAP0)
0078  *
0079  * @brief This group contains register bit definitions.
0080  *
0081  * @{
0082  */
0083
0084 #define GRIOMMU_CAP0_A 0x80000000U
0085
0086 #define GRIOMMU_CAP0_AC 0x40000000U
0087
0088 #define GRIOMMU_CAP0_CA 0x20000000U
0089
0090 #define GRIOMMU_CAP0_CP 0x10000000U
0091
0092 #define GRIOMMU_CAP0_NARB_SHIFT 20
0093 #define GRIOMMU_CAP0_NARB_MASK 0xf00000U
0094 #define GRIOMMU_CAP0_NARB_GET( _reg ) \
0095   ( ( ( _reg ) & GRIOMMU_CAP0_NARB_MASK ) >> \
0096     GRIOMMU_CAP0_NARB_SHIFT )
0097 #define GRIOMMU_CAP0_NARB_SET( _reg, _val ) \
0098   ( ( ( _reg ) & ~GRIOMMU_CAP0_NARB_MASK ) | \
0099     ( ( ( _val ) << GRIOMMU_CAP0_NARB_SHIFT ) & \
0100       GRIOMMU_CAP0_NARB_MASK ) )
0101 #define GRIOMMU_CAP0_NARB( _val ) \
0102   ( ( ( _val ) << GRIOMMU_CAP0_NARB_SHIFT ) & \
0103     GRIOMMU_CAP0_NARB_MASK )
0104
0105 #define GRIOMMU_CAP0_CS 0x80000U
0106
0107 #define GRIOMMU_CAP0_FT_SHIFT 17
0108 #define GRIOMMU_CAP0_FT_MASK 0x60000U
0109 #define GRIOMMU_CAP0_FT_GET( _reg ) \
0110   ( ( ( _reg ) & GRIOMMU_CAP0_FT_MASK ) >> \
0111     GRIOMMU_CAP0_FT_SHIFT )
0112 #define GRIOMMU_CAP0_FT_SET( _reg, _val ) \
0113   ( ( ( _reg ) & ~GRIOMMU_CAP0_FT_MASK ) | \
0114     ( ( ( _val ) << GRIOMMU_CAP0_FT_SHIFT ) & \
0115       GRIOMMU_CAP0_FT_MASK ) )
0116 #define GRIOMMU_CAP0_FT( _val ) \
0117   ( ( ( _val ) << GRIOMMU_CAP0_FT_SHIFT ) & \
0118     GRIOMMU_CAP0_FT_MASK )
0119
0120 #define GRIOMMU_CAP0_ST 0x10000U
0121
0122 #define GRIOMMU_CAP0_I 0x8000U
0123
0124 #define GRIOMMU_CAP0_IT 0x4000U
0125
0126 #define GRIOMMU_CAP0_IA 0x2000U
0127
0128 #define GRIOMMU_CAP0_IP 0x1000U
0129
0130 #define GRIOMMU_CAP0_MB 0x100U
0131
0132 #define GRIOMMU_CAP0_GRPS_SHIFT 4
0133 #define GRIOMMU_CAP0_GRPS_MASK 0xf0U
0134 #define GRIOMMU_CAP0_GRPS_GET( _reg ) \
0135   ( ( ( _reg ) & GRIOMMU_CAP0_GRPS_MASK ) >> \
0136     GRIOMMU_CAP0_GRPS_SHIFT )
0137 #define GRIOMMU_CAP0_GRPS_SET( _reg, _val ) \
0138   ( ( ( _reg ) & ~GRIOMMU_CAP0_GRPS_MASK ) | \
0139     ( ( ( _val ) << GRIOMMU_CAP0_GRPS_SHIFT ) & \
0140       GRIOMMU_CAP0_GRPS_MASK ) )
0141 #define GRIOMMU_CAP0_GRPS( _val ) \
0142   ( ( ( _val ) << GRIOMMU_CAP0_GRPS_SHIFT ) & \
0143     GRIOMMU_CAP0_GRPS_MASK )
0144
0145 #define GRIOMMU_CAP0_MSTS_SHIFT 0
0146 #define GRIOMMU_CAP0_MSTS_MASK 0xfU
0147 #define GRIOMMU_CAP0_MSTS_GET( _reg ) \
0148   ( ( ( _reg ) & GRIOMMU_CAP0_MSTS_MASK ) >> \
0149     GRIOMMU_CAP0_MSTS_SHIFT )
0150 #define GRIOMMU_CAP0_MSTS_SET( _reg, _val ) \
0151   ( ( ( _reg ) & ~GRIOMMU_CAP0_MSTS_MASK ) | \
0152     ( ( ( _val ) << GRIOMMU_CAP0_MSTS_SHIFT ) & \
0153       GRIOMMU_CAP0_MSTS_MASK ) )
0154 #define GRIOMMU_CAP0_MSTS( _val ) \
0155   ( ( ( _val ) << GRIOMMU_CAP0_MSTS_SHIFT ) & \
0156     GRIOMMU_CAP0_MSTS_MASK )
0157
0158 /** @} */
0159
0160 /**
0161  * @defgroup RTEMSDeviceGRIOMMUCAP1 Capability register 1 (CAP1)
0162  *
0163  * @brief This group contains register bit definitions.
0164  *
0165  * @{
0166  */
0167
0168 #define GRIOMMU_CAP1_CADDR_SHIFT 20
0169 #define GRIOMMU_CAP1_CADDR_MASK 0xfff00000U
0170 #define GRIOMMU_CAP1_CADDR_GET( _reg ) \
0171   ( ( ( _reg ) & GRIOMMU_CAP1_CADDR_MASK ) >> \
0172     GRIOMMU_CAP1_CADDR_SHIFT )
0173 #define GRIOMMU_CAP1_CADDR_SET( _reg, _val ) \
0174   ( ( ( _reg ) & ~GRIOMMU_CAP1_CADDR_MASK ) | \
0175     ( ( ( _val ) << GRIOMMU_CAP1_CADDR_SHIFT ) & \
0176       GRIOMMU_CAP1_CADDR_MASK ) )
0177 #define GRIOMMU_CAP1_CADDR( _val ) \
0178   ( ( ( _val ) << GRIOMMU_CAP1_CADDR_SHIFT ) & \
0179     GRIOMMU_CAP1_CADDR_MASK )
0180
0181 #define GRIOMMU_CAP1_CMASK_SHIFT 16
0182 #define GRIOMMU_CAP1_CMASK_MASK 0xf0000U
0183 #define GRIOMMU_CAP1_CMASK_GET( _reg ) \
0184   ( ( ( _reg ) & GRIOMMU_CAP1_CMASK_MASK ) >> \
0185     GRIOMMU_CAP1_CMASK_SHIFT )
0186 #define GRIOMMU_CAP1_CMASK_SET( _reg, _val ) \
0187   ( ( ( _reg ) & ~GRIOMMU_CAP1_CMASK_MASK ) | \
0188     ( ( ( _val ) << GRIOMMU_CAP1_CMASK_SHIFT ) & \
0189       GRIOMMU_CAP1_CMASK_MASK ) )
0190 #define GRIOMMU_CAP1_CMASK( _val ) \
0191   ( ( ( _val ) << GRIOMMU_CAP1_CMASK_SHIFT ) & \
0192     GRIOMMU_CAP1_CMASK_MASK )
0193
0194 #define GRIOMMU_CAP1_CTAGBITS_SHIFT 8
0195 #define GRIOMMU_CAP1_CTAGBITS_MASK 0xff00U
0196 #define GRIOMMU_CAP1_CTAGBITS_GET( _reg ) \
0197   ( ( ( _reg ) & GRIOMMU_CAP1_CTAGBITS_MASK ) >> \
0198     GRIOMMU_CAP1_CTAGBITS_SHIFT )
0199 #define GRIOMMU_CAP1_CTAGBITS_SET( _reg, _val ) \
0200   ( ( ( _reg ) & ~GRIOMMU_CAP1_CTAGBITS_MASK ) | \
0201     ( ( ( _val ) << GRIOMMU_CAP1_CTAGBITS_SHIFT ) & \
0202       GRIOMMU_CAP1_CTAGBITS_MASK ) )
0203 #define GRIOMMU_CAP1_CTAGBITS( _val ) \
0204   ( ( ( _val ) << GRIOMMU_CAP1_CTAGBITS_SHIFT ) & \
0205     GRIOMMU_CAP1_CTAGBITS_MASK )
0206
0207 #define GRIOMMU_CAP1_CISIZE_SHIFT 5
0208 #define GRIOMMU_CAP1_CISIZE_MASK 0xe0U
0209 #define GRIOMMU_CAP1_CISIZE_GET( _reg ) \
0210   ( ( ( _reg ) & GRIOMMU_CAP1_CISIZE_MASK ) >> \
0211     GRIOMMU_CAP1_CISIZE_SHIFT )
0212 #define GRIOMMU_CAP1_CISIZE_SET( _reg, _val ) \
0213   ( ( ( _reg ) & ~GRIOMMU_CAP1_CISIZE_MASK ) | \
0214     ( ( ( _val ) << GRIOMMU_CAP1_CISIZE_SHIFT ) & \
0215       GRIOMMU_CAP1_CISIZE_MASK ) )
0216 #define GRIOMMU_CAP1_CISIZE( _val ) \
0217   ( ( ( _val ) << GRIOMMU_CAP1_CISIZE_SHIFT ) & \
0218     GRIOMMU_CAP1_CISIZE_MASK )
0219
0220 #define GRIOMMU_CAP1_CLINES_SHIFT 0
0221 #define GRIOMMU_CAP1_CLINES_MASK 0x1fU
0222 #define GRIOMMU_CAP1_CLINES_GET( _reg ) \
0223   ( ( ( _reg ) & GRIOMMU_CAP1_CLINES_MASK ) >> \
0224     GRIOMMU_CAP1_CLINES_SHIFT )
0225 #define GRIOMMU_CAP1_CLINES_SET( _reg, _val ) \
0226   ( ( ( _reg ) & ~GRIOMMU_CAP1_CLINES_MASK ) | \
0227     ( ( ( _val ) << GRIOMMU_CAP1_CLINES_SHIFT ) & \
0228       GRIOMMU_CAP1_CLINES_MASK ) )
0229 #define GRIOMMU_CAP1_CLINES( _val ) \
0230   ( ( ( _val ) << GRIOMMU_CAP1_CLINES_SHIFT ) & \
0231     GRIOMMU_CAP1_CLINES_MASK )
0232
0233 /** @} */
0234
0235 /**
0236  * @defgroup RTEMSDeviceGRIOMMUCAP2 Capability register 2 (CAP2)
0237  *
0238  * @brief This group contains register bit definitions.
0239  *
0240  * @{
0241  */
0242
0243 #define GRIOMMU_CAP2_TMASK_SHIFT 24
0244 #define GRIOMMU_CAP2_TMASK_MASK 0xff000000U
0245 #define GRIOMMU_CAP2_TMASK_GET( _reg ) \
0246   ( ( ( _reg ) & GRIOMMU_CAP2_TMASK_MASK ) >> \
0247     GRIOMMU_CAP2_TMASK_SHIFT )
0248 #define GRIOMMU_CAP2_TMASK_SET( _reg, _val ) \
0249   ( ( ( _reg ) & ~GRIOMMU_CAP2_TMASK_MASK ) | \
0250     ( ( ( _val ) << GRIOMMU_CAP2_TMASK_SHIFT ) & \
0251       GRIOMMU_CAP2_TMASK_MASK ) )
0252 #define GRIOMMU_CAP2_TMASK( _val ) \
0253   ( ( ( _val ) << GRIOMMU_CAP2_TMASK_SHIFT ) & \
0254     GRIOMMU_CAP2_TMASK_MASK )
0255
0256 #define GRIOMMU_CAP2_MTYPE_SHIFT 18
0257 #define GRIOMMU_CAP2_MTYPE_MASK 0xc0000U
0258 #define GRIOMMU_CAP2_MTYPE_GET( _reg ) \
0259   ( ( ( _reg ) & GRIOMMU_CAP2_MTYPE_MASK ) >> \
0260     GRIOMMU_CAP2_MTYPE_SHIFT )
0261 #define GRIOMMU_CAP2_MTYPE_SET( _reg, _val ) \
0262   ( ( ( _reg ) & ~GRIOMMU_CAP2_MTYPE_MASK ) | \
0263     ( ( ( _val ) << GRIOMMU_CAP2_MTYPE_SHIFT ) & \
0264       GRIOMMU_CAP2_MTYPE_MASK ) )
0265 #define GRIOMMU_CAP2_MTYPE( _val ) \
0266   ( ( ( _val ) << GRIOMMU_CAP2_MTYPE_SHIFT ) & \
0267     GRIOMMU_CAP2_MTYPE_MASK )
0268
0269 #define GRIOMMU_CAP2_TTYPE_SHIFT 16
0270 #define GRIOMMU_CAP2_TTYPE_MASK 0x30000U
0271 #define GRIOMMU_CAP2_TTYPE_GET( _reg ) \
0272   ( ( ( _reg ) & GRIOMMU_CAP2_TTYPE_MASK ) >> \
0273     GRIOMMU_CAP2_TTYPE_SHIFT )
0274 #define GRIOMMU_CAP2_TTYPE_SET( _reg, _val ) \
0275   ( ( ( _reg ) & ~GRIOMMU_CAP2_TTYPE_MASK ) | \
0276     ( ( ( _val ) << GRIOMMU_CAP2_TTYPE_SHIFT ) & \
0277       GRIOMMU_CAP2_TTYPE_MASK ) )
0278 #define GRIOMMU_CAP2_TTYPE( _val ) \
0279   ( ( ( _val ) << GRIOMMU_CAP2_TTYPE_SHIFT ) & \
0280     GRIOMMU_CAP2_TTYPE_MASK )
0281
0282 #define GRIOMMU_CAP2_TTAGBITS_SHIFT 8
0283 #define GRIOMMU_CAP2_TTAGBITS_MASK 0xff00U
0284 #define GRIOMMU_CAP2_TTAGBITS_GET( _reg ) \
0285   ( ( ( _reg ) & GRIOMMU_CAP2_TTAGBITS_MASK ) >> \
0286     GRIOMMU_CAP2_TTAGBITS_SHIFT )
0287 #define GRIOMMU_CAP2_TTAGBITS_SET( _reg, _val ) \
0288   ( ( ( _reg ) & ~GRIOMMU_CAP2_TTAGBITS_MASK ) | \
0289     ( ( ( _val ) << GRIOMMU_CAP2_TTAGBITS_SHIFT ) & \
0290       GRIOMMU_CAP2_TTAGBITS_MASK ) )
0291 #define GRIOMMU_CAP2_TTAGBITS( _val ) \
0292   ( ( ( _val ) << GRIOMMU_CAP2_TTAGBITS_SHIFT ) & \
0293     GRIOMMU_CAP2_TTAGBITS_MASK )
0294
0295 #define GRIOMMU_CAP2_ISIZE_SHIFT 5
0296 #define GRIOMMU_CAP2_ISIZE_MASK 0xe0U
0297 #define GRIOMMU_CAP2_ISIZE_GET( _reg ) \
0298   ( ( ( _reg ) & GRIOMMU_CAP2_ISIZE_MASK ) >> \
0299     GRIOMMU_CAP2_ISIZE_SHIFT )
0300 #define GRIOMMU_CAP2_ISIZE_SET( _reg, _val ) \
0301   ( ( ( _reg ) & ~GRIOMMU_CAP2_ISIZE_MASK ) | \
0302     ( ( ( _val ) << GRIOMMU_CAP2_ISIZE_SHIFT ) & \
0303       GRIOMMU_CAP2_ISIZE_MASK ) )
0304 #define GRIOMMU_CAP2_ISIZE( _val ) \
0305   ( ( ( _val ) << GRIOMMU_CAP2_ISIZE_SHIFT ) & \
0306     GRIOMMU_CAP2_ISIZE_MASK )
0307
0308 #define GRIOMMU_CAP2_TLBENT_SHIFT 0
0309 #define GRIOMMU_CAP2_TLBENT_MASK 0x1fU
0310 #define GRIOMMU_CAP2_TLBENT_GET( _reg ) \
0311   ( ( ( _reg ) & GRIOMMU_CAP2_TLBENT_MASK ) >> \
0312     GRIOMMU_CAP2_TLBENT_SHIFT )
0313 #define GRIOMMU_CAP2_TLBENT_SET( _reg, _val ) \
0314   ( ( ( _reg ) & ~GRIOMMU_CAP2_TLBENT_MASK ) | \
0315     ( ( ( _val ) << GRIOMMU_CAP2_TLBENT_SHIFT ) & \
0316       GRIOMMU_CAP2_TLBENT_MASK ) )
0317 #define GRIOMMU_CAP2_TLBENT( _val ) \
0318   ( ( ( _val ) << GRIOMMU_CAP2_TLBENT_SHIFT ) & \
0319     GRIOMMU_CAP2_TLBENT_MASK )
0320
0321 /** @} */
0322
0323 /**
0324  * @defgroup RTEMSDeviceGRIOMMUCTRL Control register (CTRL)
0325  *
0326  * @brief This group contains register bit definitions.
0327  *
0328  * @{
0329  */
0330
0331 #define GRIOMMU_CTRL_PGSZ_SHIFT 18
0332 #define GRIOMMU_CTRL_PGSZ_MASK 0x1c0000U
0333 #define GRIOMMU_CTRL_PGSZ_GET( _reg ) \
0334   ( ( ( _reg ) & GRIOMMU_CTRL_PGSZ_MASK ) >> \
0335     GRIOMMU_CTRL_PGSZ_SHIFT )
0336 #define GRIOMMU_CTRL_PGSZ_SET( _reg, _val ) \
0337   ( ( ( _reg ) & ~GRIOMMU_CTRL_PGSZ_MASK ) | \
0338     ( ( ( _val ) << GRIOMMU_CTRL_PGSZ_SHIFT ) & \
0339       GRIOMMU_CTRL_PGSZ_MASK ) )
0340 #define GRIOMMU_CTRL_PGSZ( _val ) \
0341   ( ( ( _val ) << GRIOMMU_CTRL_PGSZ_SHIFT ) & \
0342     GRIOMMU_CTRL_PGSZ_MASK )
0343
0344 #define GRIOMMU_CTRL_LB 0x20000U
0345
0346 #define GRIOMMU_CTRL_SP 0x10000U
0347
0348 #define GRIOMMU_CTRL_ITR_SHIFT 12
0349 #define GRIOMMU_CTRL_ITR_MASK 0xf000U
0350 #define GRIOMMU_CTRL_ITR_GET( _reg ) \
0351   ( ( ( _reg ) & GRIOMMU_CTRL_ITR_MASK ) >> \
0352     GRIOMMU_CTRL_ITR_SHIFT )
0353 #define GRIOMMU_CTRL_ITR_SET( _reg, _val ) \
0354   ( ( ( _reg ) & ~GRIOMMU_CTRL_ITR_MASK ) | \
0355     ( ( ( _val ) << GRIOMMU_CTRL_ITR_SHIFT ) & \
0356       GRIOMMU_CTRL_ITR_MASK ) )
0357 #define GRIOMMU_CTRL_ITR( _val ) \
0358   ( ( ( _val ) << GRIOMMU_CTRL_ITR_SHIFT ) & \
0359     GRIOMMU_CTRL_ITR_MASK )
0360
0361 #define GRIOMMU_CTRL_DP 0x800U
0362
0363 #define GRIOMMU_CTRL_SIV 0x400U
0364
0365 #define GRIOMMU_CTRL_HPROT_SHIFT 8
0366 #define GRIOMMU_CTRL_HPROT_MASK 0x300U
0367 #define GRIOMMU_CTRL_HPROT_GET( _reg ) \
0368   ( ( ( _reg ) & GRIOMMU_CTRL_HPROT_MASK ) >> \
0369     GRIOMMU_CTRL_HPROT_SHIFT )
0370 #define GRIOMMU_CTRL_HPROT_SET( _reg, _val ) \
0371   ( ( ( _reg ) & ~GRIOMMU_CTRL_HPROT_MASK ) | \
0372     ( ( ( _val ) << GRIOMMU_CTRL_HPROT_SHIFT ) & \
0373       GRIOMMU_CTRL_HPROT_MASK ) )
0374 #define GRIOMMU_CTRL_HPROT( _val ) \
0375   ( ( ( _val ) << GRIOMMU_CTRL_HPROT_SHIFT ) & \
0376     GRIOMMU_CTRL_HPROT_MASK )
0377
0378 #define GRIOMMU_CTRL_AU 0x80U
0379
0380 #define GRIOMMU_CTRL_WP 0x40U
0381
0382 #define GRIOMMU_CTRL_DM 0x20U
0383
0384 #define GRIOMMU_CTRL_GS 0x10U
0385
0386 #define GRIOMMU_CTRL_CE 0x8U
0387
0388 #define GRIOMMU_CTRL_PM_SHIFT 1
0389 #define GRIOMMU_CTRL_PM_MASK 0x6U
0390 #define GRIOMMU_CTRL_PM_GET( _reg ) \
0391   ( ( ( _reg ) & GRIOMMU_CTRL_PM_MASK ) >> \
0392     GRIOMMU_CTRL_PM_SHIFT )
0393 #define GRIOMMU_CTRL_PM_SET( _reg, _val ) \
0394   ( ( ( _reg ) & ~GRIOMMU_CTRL_PM_MASK ) | \
0395     ( ( ( _val ) << GRIOMMU_CTRL_PM_SHIFT ) & \
0396       GRIOMMU_CTRL_PM_MASK ) )
0397 #define GRIOMMU_CTRL_PM( _val ) \
0398   ( ( ( _val ) << GRIOMMU_CTRL_PM_SHIFT ) & \
0399     GRIOMMU_CTRL_PM_MASK )
0400
0401 #define GRIOMMU_CTRL_EN 0x1U
0402
0403 /** @} */
0404
0405 /**
0406  * @defgroup RTEMSDeviceGRIOMMUFLUSH TLB/cache flush register (FLUSH)
0407  *
0408  * @brief This group contains register bit definitions.
0409  *
0410  * @{
0411  */
0412
0413 #define GRIOMMU_FLUSH_FGRP_SHIFT 4
0414 #define GRIOMMU_FLUSH_FGRP_MASK 0xf0U
0415 #define GRIOMMU_FLUSH_FGRP_GET( _reg ) \
0416   ( ( ( _reg ) & GRIOMMU_FLUSH_FGRP_MASK ) >> \
0417     GRIOMMU_FLUSH_FGRP_SHIFT )
0418 #define GRIOMMU_FLUSH_FGRP_SET( _reg, _val ) \
0419   ( ( ( _reg ) & ~GRIOMMU_FLUSH_FGRP_MASK ) | \
0420     ( ( ( _val ) << GRIOMMU_FLUSH_FGRP_SHIFT ) & \
0421       GRIOMMU_FLUSH_FGRP_MASK ) )
0422 #define GRIOMMU_FLUSH_FGRP( _val ) \
0423   ( ( ( _val ) << GRIOMMU_FLUSH_FGRP_SHIFT ) & \
0424     GRIOMMU_FLUSH_FGRP_MASK )
0425
0426 #define GRIOMMU_FLUSH_GF 0x2U
0427
0428 #define GRIOMMU_FLUSH_F 0x1U
0429
0430 /** @} */
0431
0432 /**
0433  * @defgroup RTEMSDeviceGRIOMMUSTATUS Status register (STATUS)
0434  *
0435  * @brief This group contains register bit definitions.
0436  *
0437  * @{
0438  */
0439
0440 #define GRIOMMU_STATUS_PE 0x20U
0441
0442 #define GRIOMMU_STATUS_DE 0x10U
0443
0444 #define GRIOMMU_STATUS_FC 0x8U
0445
0446 #define GRIOMMU_STATUS_FL 0x4U
0447
0448 #define GRIOMMU_STATUS_AD 0x2U
0449
0450 #define GRIOMMU_STATUS_TE 0x1U
0451
0452 /** @} */
0453
0454 /**
0455  * @defgroup RTEMSDeviceGRIOMMUIMASK Interrupt mask register (IMASK)
0456  *
0457  * @brief This group contains register bit definitions.
0458  *
0459  * @{
0460  */
0461
0462 #define GRIOMMU_IMASK_PEI 0x20U
0463
0464 #define GRIOMMU_IMASK_FCI 0x8U
0465
0466 #define GRIOMMU_IMASK_FLI 0x4U
0467
0468 #define GRIOMMU_IMASK_ADI 0x2U
0469
0470 #define GRIOMMU_IMASK_TEI 0x1U
0471
0472 /** @} */
0473
0474 /**
0475  * @defgroup RTEMSDeviceGRIOMMUAHBFAS AHB failing access register (AHBFAS)
0476  *
0477  * @brief This group contains register bit definitions.
0478  *
0479  * @{
0480  */
0481
0482 #define GRIOMMU_AHBFAS_FADDR_31_5_SHIFT 5
0483 #define GRIOMMU_AHBFAS_FADDR_31_5_MASK 0xffffffe0U
0484 #define GRIOMMU_AHBFAS_FADDR_31_5_GET( _reg ) \
0485   ( ( ( _reg ) & GRIOMMU_AHBFAS_FADDR_31_5_MASK ) >> \
0486     GRIOMMU_AHBFAS_FADDR_31_5_SHIFT )
0487 #define GRIOMMU_AHBFAS_FADDR_31_5_SET( _reg, _val ) \
0488   ( ( ( _reg ) & ~GRIOMMU_AHBFAS_FADDR_31_5_MASK ) | \
0489     ( ( ( _val ) << GRIOMMU_AHBFAS_FADDR_31_5_SHIFT ) & \
0490       GRIOMMU_AHBFAS_FADDR_31_5_MASK ) )
0491 #define GRIOMMU_AHBFAS_FADDR_31_5( _val ) \
0492   ( ( ( _val ) << GRIOMMU_AHBFAS_FADDR_31_5_SHIFT ) & \
0493     GRIOMMU_AHBFAS_FADDR_31_5_MASK )
0494
0495 #define GRIOMMU_AHBFAS_FW 0x10U
0496
0497 #define GRIOMMU_AHBFAS_FMASTER_SHIFT 0
0498 #define GRIOMMU_AHBFAS_FMASTER_MASK 0xfU
0499 #define GRIOMMU_AHBFAS_FMASTER_GET( _reg ) \
0500   ( ( ( _reg ) & GRIOMMU_AHBFAS_FMASTER_MASK ) >> \
0501     GRIOMMU_AHBFAS_FMASTER_SHIFT )
0502 #define GRIOMMU_AHBFAS_FMASTER_SET( _reg, _val ) \
0503   ( ( ( _reg ) & ~GRIOMMU_AHBFAS_FMASTER_MASK ) | \
0504     ( ( ( _val ) << GRIOMMU_AHBFAS_FMASTER_SHIFT ) & \
0505       GRIOMMU_AHBFAS_FMASTER_MASK ) )
0506 #define GRIOMMU_AHBFAS_FMASTER( _val ) \
0507   ( ( ( _val ) << GRIOMMU_AHBFAS_FMASTER_SHIFT ) & \
0508     GRIOMMU_AHBFAS_FMASTER_MASK )
0509
0510 /** @} */
0511
0512 /**
0513  * @defgroup RTEMSDeviceGRIOMMUMSTCFG \
0514  *   Master configuration register 0 - 9 (MSTCFG)
0515  *
0516  * @brief This group contains register bit definitions.
0517  *
0518  * @{
0519  */
0520
0521 #define GRIOMMU_MSTCFG_VENDOR_SHIFT 24
0522 #define GRIOMMU_MSTCFG_VENDOR_MASK 0xff000000U
0523 #define GRIOMMU_MSTCFG_VENDOR_GET( _reg ) \
0524   ( ( ( _reg ) & GRIOMMU_MSTCFG_VENDOR_MASK ) >> \
0525     GRIOMMU_MSTCFG_VENDOR_SHIFT )
0526 #define GRIOMMU_MSTCFG_VENDOR_SET( _reg, _val ) \
0527   ( ( ( _reg ) & ~GRIOMMU_MSTCFG_VENDOR_MASK ) | \
0528     ( ( ( _val ) << GRIOMMU_MSTCFG_VENDOR_SHIFT ) & \
0529       GRIOMMU_MSTCFG_VENDOR_MASK ) )
0530 #define GRIOMMU_MSTCFG_VENDOR( _val ) \
0531   ( ( ( _val ) << GRIOMMU_MSTCFG_VENDOR_SHIFT ) & \
0532     GRIOMMU_MSTCFG_VENDOR_MASK )
0533
0534 #define GRIOMMU_MSTCFG_DEVICE_SHIFT 12
0535 #define GRIOMMU_MSTCFG_DEVICE_MASK 0xfff000U
0536 #define GRIOMMU_MSTCFG_DEVICE_GET( _reg ) \
0537   ( ( ( _reg ) & GRIOMMU_MSTCFG_DEVICE_MASK ) >> \
0538     GRIOMMU_MSTCFG_DEVICE_SHIFT )
0539 #define GRIOMMU_MSTCFG_DEVICE_SET( _reg, _val ) \
0540   ( ( ( _reg ) & ~GRIOMMU_MSTCFG_DEVICE_MASK ) | \
0541     ( ( ( _val ) << GRIOMMU_MSTCFG_DEVICE_SHIFT ) & \
0542       GRIOMMU_MSTCFG_DEVICE_MASK ) )
0543 #define GRIOMMU_MSTCFG_DEVICE( _val ) \
0544   ( ( ( _val ) << GRIOMMU_MSTCFG_DEVICE_SHIFT ) & \
0545     GRIOMMU_MSTCFG_DEVICE_MASK )
0546
0547 #define GRIOMMU_MSTCFG_BS 0x10U
0548
0549 #define GRIOMMU_MSTCFG_GROUP_SHIFT 0
0550 #define GRIOMMU_MSTCFG_GROUP_MASK 0xfU
0551 #define GRIOMMU_MSTCFG_GROUP_GET( _reg ) \
0552   ( ( ( _reg ) & GRIOMMU_MSTCFG_GROUP_MASK ) >> \
0553     GRIOMMU_MSTCFG_GROUP_SHIFT )
0554 #define GRIOMMU_MSTCFG_GROUP_SET( _reg, _val ) \
0555   ( ( ( _reg ) & ~GRIOMMU_MSTCFG_GROUP_MASK ) | \
0556     ( ( ( _val ) << GRIOMMU_MSTCFG_GROUP_SHIFT ) & \
0557       GRIOMMU_MSTCFG_GROUP_MASK ) )
0558 #define GRIOMMU_MSTCFG_GROUP( _val ) \
0559   ( ( ( _val ) << GRIOMMU_MSTCFG_GROUP_SHIFT ) & \
0560     GRIOMMU_MSTCFG_GROUP_MASK )
0561
0562 /** @} */
0563
0564 /**
0565  * @defgroup RTEMSDeviceGRIOMMUGRPCTRL Group control register 0 - 7 (GRPCTRL)
0566  *
0567  * @brief This group contains register bit definitions.
0568  *
0569  * @{
0570  */
0571
0572 #define GRIOMMU_GRPCTRL_BASE_31_4_SHIFT 4
0573 #define GRIOMMU_GRPCTRL_BASE_31_4_MASK 0xfffffff0U
0574 #define GRIOMMU_GRPCTRL_BASE_31_4_GET( _reg ) \
0575   ( ( ( _reg ) & GRIOMMU_GRPCTRL_BASE_31_4_MASK ) >> \
0576     GRIOMMU_GRPCTRL_BASE_31_4_SHIFT )
0577 #define GRIOMMU_GRPCTRL_BASE_31_4_SET( _reg, _val ) \
0578   ( ( ( _reg ) & ~GRIOMMU_GRPCTRL_BASE_31_4_MASK ) | \
0579     ( ( ( _val ) << GRIOMMU_GRPCTRL_BASE_31_4_SHIFT ) & \
0580       GRIOMMU_GRPCTRL_BASE_31_4_MASK ) )
0581 #define GRIOMMU_GRPCTRL_BASE_31_4( _val ) \
0582   ( ( ( _val ) << GRIOMMU_GRPCTRL_BASE_31_4_SHIFT ) & \
0583     GRIOMMU_GRPCTRL_BASE_31_4_MASK )
0584
0585 #define GRIOMMU_GRPCTRL_P 0x2U
0586
0587 #define GRIOMMU_GRPCTRL_AG 0x1U
0588
0589 /** @} */
0590
0591 /**
0592  * @defgroup RTEMSDeviceGRIOMMUDIAGCTRL \
0593  *   Diagnostic cache access register (DIAGCTRL)
0594  *
0595  * @brief This group contains register bit definitions.
0596  *
0597  * @{
0598  */
0599
0600 #define GRIOMMU_DIAGCTRL_DA 0x80000000U
0601
0602 #define GRIOMMU_DIAGCTRL_RW 0x40000000U
0603
0604 #define GRIOMMU_DIAGCTRL_DP 0x200000U
0605
0606 #define GRIOMMU_DIAGCTRL_TP 0x100000U
0607
0608 #define GRIOMMU_DIAGCTRL_SETADDR_SHIFT 0
0609 #define GRIOMMU_DIAGCTRL_SETADDR_MASK 0x7ffffU
0610 #define GRIOMMU_DIAGCTRL_SETADDR_GET( _reg ) \
0611   ( ( ( _reg ) & GRIOMMU_DIAGCTRL_SETADDR_MASK ) >> \
0612     GRIOMMU_DIAGCTRL_SETADDR_SHIFT )
0613 #define GRIOMMU_DIAGCTRL_SETADDR_SET( _reg, _val ) \
0614   ( ( ( _reg ) & ~GRIOMMU_DIAGCTRL_SETADDR_MASK ) | \
0615     ( ( ( _val ) << GRIOMMU_DIAGCTRL_SETADDR_SHIFT ) & \
0616       GRIOMMU_DIAGCTRL_SETADDR_MASK ) )
0617 #define GRIOMMU_DIAGCTRL_SETADDR( _val ) \
0618   ( ( ( _val ) << GRIOMMU_DIAGCTRL_SETADDR_SHIFT ) & \
0619     GRIOMMU_DIAGCTRL_SETADDR_MASK )
0620
0621 /** @} */
0622
0623 /**
0624  * @defgroup RTEMSDeviceGRIOMMUDIAGD \
0625  *   Diagnostic cache access data register 0 - 7 (DIAGD)
0626  *
0627  * @brief This group contains register bit definitions.
0628  *
0629  * @{
0630  */
0631
0632 #define GRIOMMU_DIAGD_CDATAN_SHIFT 0
0633 #define GRIOMMU_DIAGD_CDATAN_MASK 0xffffffffU
0634 #define GRIOMMU_DIAGD_CDATAN_GET( _reg ) \
0635   ( ( ( _reg ) & GRIOMMU_DIAGD_CDATAN_MASK ) >> \
0636     GRIOMMU_DIAGD_CDATAN_SHIFT )
0637 #define GRIOMMU_DIAGD_CDATAN_SET( _reg, _val ) \
0638   ( ( ( _reg ) & ~GRIOMMU_DIAGD_CDATAN_MASK ) | \
0639     ( ( ( _val ) << GRIOMMU_DIAGD_CDATAN_SHIFT ) & \
0640       GRIOMMU_DIAGD_CDATAN_MASK ) )
0641 #define GRIOMMU_DIAGD_CDATAN( _val ) \
0642   ( ( ( _val ) << GRIOMMU_DIAGD_CDATAN_SHIFT ) & \
0643     GRIOMMU_DIAGD_CDATAN_MASK )
0644
0645 /** @} */
0646
0647 /**
0648  * @defgroup RTEMSDeviceGRIOMMUDIAGT \
0649  *   Diagnostic cache access tag register (DIAGT)
0650  *
0651  * @brief This group contains register bit definitions.
0652  *
0653  * @{
0654  */
0655
0656 #define GRIOMMU_DIAGT_TAG_SHIFT 1
0657 #define GRIOMMU_DIAGT_TAG_MASK 0xfffffffeU
0658 #define GRIOMMU_DIAGT_TAG_GET( _reg ) \
0659   ( ( ( _reg ) & GRIOMMU_DIAGT_TAG_MASK ) >> \
0660     GRIOMMU_DIAGT_TAG_SHIFT )
0661 #define GRIOMMU_DIAGT_TAG_SET( _reg, _val ) \
0662   ( ( ( _reg ) & ~GRIOMMU_DIAGT_TAG_MASK ) | \
0663     ( ( ( _val ) << GRIOMMU_DIAGT_TAG_SHIFT ) & \
0664       GRIOMMU_DIAGT_TAG_MASK ) )
0665 #define GRIOMMU_DIAGT_TAG( _val ) \
0666   ( ( ( _val ) << GRIOMMU_DIAGT_TAG_SHIFT ) & \
0667     GRIOMMU_DIAGT_TAG_MASK )
0668
0669 #define GRIOMMU_DIAGT_V 0x1U
0670
0671 /** @} */
0672
0673 /**
0674  * @defgroup RTEMSDeviceGRIOMMUDERRI Data RAM error injection register (DERRI)
0675  *
0676  * @brief This group contains register bit definitions.
0677  *
0678  * @{
0679  */
0680
0681 #define GRIOMMU_DERRI_DPERRINJ_SHIFT 0
0682 #define GRIOMMU_DERRI_DPERRINJ_MASK 0xffffffffU
0683 #define GRIOMMU_DERRI_DPERRINJ_GET( _reg ) \
0684   ( ( ( _reg ) & GRIOMMU_DERRI_DPERRINJ_MASK ) >> \
0685     GRIOMMU_DERRI_DPERRINJ_SHIFT )
0686 #define GRIOMMU_DERRI_DPERRINJ_SET( _reg, _val ) \
0687   ( ( ( _reg ) & ~GRIOMMU_DERRI_DPERRINJ_MASK ) | \
0688     ( ( ( _val ) << GRIOMMU_DERRI_DPERRINJ_SHIFT ) & \
0689       GRIOMMU_DERRI_DPERRINJ_MASK ) )
0690 #define GRIOMMU_DERRI_DPERRINJ( _val ) \
0691   ( ( ( _val ) << GRIOMMU_DERRI_DPERRINJ_SHIFT ) & \
0692     GRIOMMU_DERRI_DPERRINJ_MASK )
0693
0694 /** @} */
0695
0696 /**
0697  * @defgroup RTEMSDeviceGRIOMMUTERRI Tag RAM error injection register (TERRI)
0698  *
0699  * @brief This group contains register bit definitions.
0700  *
0701  * @{
0702  */
0703
0704 #define GRIOMMU_TERRI_TPERRINJ_SHIFT 0
0705 #define GRIOMMU_TERRI_TPERRINJ_MASK 0xffffffffU
0706 #define GRIOMMU_TERRI_TPERRINJ_GET( _reg ) \
0707   ( ( ( _reg ) & GRIOMMU_TERRI_TPERRINJ_MASK ) >> \
0708     GRIOMMU_TERRI_TPERRINJ_SHIFT )
0709 #define GRIOMMU_TERRI_TPERRINJ_SET( _reg, _val ) \
0710   ( ( ( _reg ) & ~GRIOMMU_TERRI_TPERRINJ_MASK ) | \
0711     ( ( ( _val ) << GRIOMMU_TERRI_TPERRINJ_SHIFT ) & \
0712       GRIOMMU_TERRI_TPERRINJ_MASK ) )
0713 #define GRIOMMU_TERRI_TPERRINJ( _val ) \
0714   ( ( ( _val ) << GRIOMMU_TERRI_TPERRINJ_SHIFT ) & \
0715     GRIOMMU_TERRI_TPERRINJ_MASK )
0716
0717 /** @} */
0718
0719 /**
0720  * @defgroup RTEMSDeviceGRIOMMUASMPCTRL \
0721  *   ASMP access control registers 0 - 3 (ASMPCTRL)
0722  *
0723  * @brief This group contains register bit definitions.
0724  *
0725  * @{
0726  */
0727
0728 #define GRIOMMU_ASMPCTRL_FC 0x40000U
0729
0730 #define GRIOMMU_ASMPCTRL_SC 0x20000U
0731
0732 #define GRIOMMU_ASMPCTRL_MC 0x10000U
0733
0734 #define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT 0
0735 #define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK 0xffffU
0736 #define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_GET( _reg ) \
0737   ( ( ( _reg ) & GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK ) >> \
0738     GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT )
0739 #define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SET( _reg, _val ) \
0740   ( ( ( _reg ) & ~GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK ) | \
0741     ( ( ( _val ) << GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT ) & \
0742       GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK ) )
0743 #define GRIOMMU_ASMPCTRL_GRPACCSZCTRL( _val ) \
0744   ( ( ( _val ) << GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT ) & \
0745     GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK )
0746
0747 /** @} */
0748
0749 /**
0750  * @brief This structure defines the GRIOMMU register block memory map.
0751  */
0752 typedef struct griommu {
0753   /**
0754    * @brief See @ref RTEMSDeviceGRIOMMUCAP0.
0755    */
0756   uint32_t cap0;
0757
0758   /**
0759    * @brief See @ref RTEMSDeviceGRIOMMUCAP1.
0760    */
0761   uint32_t cap1;
0762
0763   /**
0764    * @brief See @ref RTEMSDeviceGRIOMMUCAP2.
0765    */
0766   uint32_t cap2;
0767
0768   uint32_t reserved_c_10;
0769
0770   /**
0771    * @brief See @ref RTEMSDeviceGRIOMMUCTRL.
0772    */
0773   uint32_t ctrl;
0774
0775   /**
0776    * @brief See @ref RTEMSDeviceGRIOMMUFLUSH.
0777    */
0778   uint32_t flush;
0779
0780   /**
0781    * @brief See @ref RTEMSDeviceGRIOMMUSTATUS.
0782    */
0783   uint32_t status;
0784
0785   /**
0786    * @brief See @ref RTEMSDeviceGRIOMMUIMASK.
0787    */
0788   uint32_t imask;
0789
0790   /**
0791    * @brief See @ref RTEMSDeviceGRIOMMUAHBFAS.
0792    */
0793   uint32_t ahbfas;
0794
0795   uint32_t reserved_24_40[ 7 ];
0796
0797   /**
0798    * @brief See @ref RTEMSDeviceGRIOMMUMSTCFG.
0799    */
0800   uint32_t mstcfg_0;
0801
0802   uint32_t reserved_44_64[ 8 ];
0803
0804   /**
0805    * @brief See @ref RTEMSDeviceGRIOMMUMSTCFG.
0806    */
0807   uint32_t mstcfg_1;
0808
0809   uint32_t reserved_68_80[ 6 ];
0810
0811   /**
0812    * @brief See @ref RTEMSDeviceGRIOMMUGRPCTRL.
0813    */
0814   uint32_t grpctrl_0;
0815
0816   uint32_t reserved_84_9c[ 6 ];
0817
0818   /**
0819    * @brief See @ref RTEMSDeviceGRIOMMUGRPCTRL.
0820    */
0821   uint32_t grpctrl_1;
0822
0823   uint32_t reserved_a0_c0[ 8 ];
0824
0825   /**
0826    * @brief See @ref RTEMSDeviceGRIOMMUDIAGCTRL.
0827    */
0828   uint32_t diagctrl;
0829
0830   /**
0831    * @brief See @ref RTEMSDeviceGRIOMMUDIAGD.
0832    */
0833   uint32_t diagd_0;
0834
0835   uint32_t reserved_c8_e0[ 6 ];
0836
0837   /**
0838    * @brief See @ref RTEMSDeviceGRIOMMUDIAGD.
0839    */
0840   uint32_t diagd_1;
0841
0842   /**
0843    * @brief See @ref RTEMSDeviceGRIOMMUDIAGT.
0844    */
0845   uint32_t diagt;
0846
0847   /**
0848    * @brief See @ref RTEMSDeviceGRIOMMUDERRI.
0849    */
0850   uint32_t derri;
0851
0852   /**
0853    * @brief See @ref RTEMSDeviceGRIOMMUTERRI.
0854    */
0855   uint32_t terri;
0856
0857   uint32_t reserved_f0_100[ 4 ];
0858
0859   /**
0860    * @brief See @ref RTEMSDeviceGRIOMMUASMPCTRL.
0861    */
0862   uint32_t asmpctrl_0;
0863
0864   uint32_t reserved_104_10c[ 2 ];
0865
0866   /**
0867    * @brief See @ref RTEMSDeviceGRIOMMUASMPCTRL.
0868    */
0869   uint32_t asmpctrl_1;
0870 } griommu;
0871
0872 /** @} */
0873
0874 #ifdef __cplusplus
0875 }
0876 #endif
0877
0878 #endif /* _GRLIB_GRIOMMU_REGS_H */