include/grlib/grgpio-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRGPIO
0007  *
0008  * @brief This header file defines the GRGPIO register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/grgpio-header */
0054
0055 #ifndef _GRLIB_GRGPIO_REGS_H
0056 #define _GRLIB_GRGPIO_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/grgpio */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRGPIO GRGPIO
0068  *
0069  * @ingroup RTEMSDeviceGRLIB
0070  *
0071  * @brief This group contains the GRGPIO interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRGPIODATA I/O port data register (DATA)
0078  *
0079  * @brief This group contains register bit definitions.
0080  *
0081  * @{
0082  */
0083
0084 #define GRGPIO_DATA_DATA_SHIFT 0
0085 #define GRGPIO_DATA_DATA_MASK 0xffffffffU
0086 #define GRGPIO_DATA_DATA_GET( _reg ) \
0087   ( ( ( _reg ) & GRGPIO_DATA_DATA_MASK ) >> \
0088     GRGPIO_DATA_DATA_SHIFT )
0089 #define GRGPIO_DATA_DATA_SET( _reg, _val ) \
0090   ( ( ( _reg ) & ~GRGPIO_DATA_DATA_MASK ) | \
0091     ( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & \
0092       GRGPIO_DATA_DATA_MASK ) )
0093 #define GRGPIO_DATA_DATA( _val ) \
0094   ( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & \
0095     GRGPIO_DATA_DATA_MASK )
0096
0097 /** @} */
0098
0099 /**
0100  * @defgroup RTEMSDeviceGRGPIOOUTPUT I/O port output register (OUTPUT)
0101  *
0102  * @brief This group contains register bit definitions.
0103  *
0104  * @{
0105  */
0106
0107 #define GRGPIO_OUTPUT_DATA_SHIFT 0
0108 #define GRGPIO_OUTPUT_DATA_MASK 0xffffffffU
0109 #define GRGPIO_OUTPUT_DATA_GET( _reg ) \
0110   ( ( ( _reg ) & GRGPIO_OUTPUT_DATA_MASK ) >> \
0111     GRGPIO_OUTPUT_DATA_SHIFT )
0112 #define GRGPIO_OUTPUT_DATA_SET( _reg, _val ) \
0113   ( ( ( _reg ) & ~GRGPIO_OUTPUT_DATA_MASK ) | \
0114     ( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & \
0115       GRGPIO_OUTPUT_DATA_MASK ) )
0116 #define GRGPIO_OUTPUT_DATA( _val ) \
0117   ( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & \
0118     GRGPIO_OUTPUT_DATA_MASK )
0119
0120 /** @} */
0121
0122 /**
0123  * @defgroup RTEMSDeviceGRGPIODIRECTION I/O port direction register (DIRECTION)
0124  *
0125  * @brief This group contains register bit definitions.
0126  *
0127  * @{
0128  */
0129
0130 #define GRGPIO_DIRECTION_DIR_SHIFT 0
0131 #define GRGPIO_DIRECTION_DIR_MASK 0xffffffffU
0132 #define GRGPIO_DIRECTION_DIR_GET( _reg ) \
0133   ( ( ( _reg ) & GRGPIO_DIRECTION_DIR_MASK ) >> \
0134     GRGPIO_DIRECTION_DIR_SHIFT )
0135 #define GRGPIO_DIRECTION_DIR_SET( _reg, _val ) \
0136   ( ( ( _reg ) & ~GRGPIO_DIRECTION_DIR_MASK ) | \
0137     ( ( ( _val ) << GRGPIO_DIRECTION_DIR_SHIFT ) & \
0138       GRGPIO_DIRECTION_DIR_MASK ) )
0139 #define GRGPIO_DIRECTION_DIR( _val ) \
0140   ( ( ( _val ) << GRGPIO_DIRECTION_DIR_SHIFT ) & \
0141     GRGPIO_DIRECTION_DIR_MASK )
0142
0143 /** @} */
0144
0145 /**
0146  * @defgroup RTEMSDeviceGRGPIOIMASK Interrupt mask register (IMASK)
0147  *
0148  * @brief This group contains register bit definitions.
0149  *
0150  * @{
0151  */
0152
0153 #define GRGPIO_IMASK_MASK_SHIFT 0
0154 #define GRGPIO_IMASK_MASK_MASK 0xffffffffU
0155 #define GRGPIO_IMASK_MASK_GET( _reg ) \
0156   ( ( ( _reg ) & GRGPIO_IMASK_MASK_MASK ) >> \
0157     GRGPIO_IMASK_MASK_SHIFT )
0158 #define GRGPIO_IMASK_MASK_SET( _reg, _val ) \
0159   ( ( ( _reg ) & ~GRGPIO_IMASK_MASK_MASK ) | \
0160     ( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & \
0161       GRGPIO_IMASK_MASK_MASK ) )
0162 #define GRGPIO_IMASK_MASK( _val ) \
0163   ( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & \
0164     GRGPIO_IMASK_MASK_MASK )
0165
0166 /** @} */
0167
0168 /**
0169  * @defgroup RTEMSDeviceGRGPIOIPOL Interrupt polarity register (IPOL)
0170  *
0171  * @brief This group contains register bit definitions.
0172  *
0173  * @{
0174  */
0175
0176 #define GRGPIO_IPOL_POL_SHIFT 0
0177 #define GRGPIO_IPOL_POL_MASK 0xffffffffU
0178 #define GRGPIO_IPOL_POL_GET( _reg ) \
0179   ( ( ( _reg ) & GRGPIO_IPOL_POL_MASK ) >> \
0180     GRGPIO_IPOL_POL_SHIFT )
0181 #define GRGPIO_IPOL_POL_SET( _reg, _val ) \
0182   ( ( ( _reg ) & ~GRGPIO_IPOL_POL_MASK ) | \
0183     ( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & \
0184       GRGPIO_IPOL_POL_MASK ) )
0185 #define GRGPIO_IPOL_POL( _val ) \
0186   ( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & \
0187     GRGPIO_IPOL_POL_MASK )
0188
0189 /** @} */
0190
0191 /**
0192  * @defgroup RTEMSDeviceGRGPIOIEDGE Interrupt edge register (IEDGE)
0193  *
0194  * @brief This group contains register bit definitions.
0195  *
0196  * @{
0197  */
0198
0199 #define GRGPIO_IEDGE_EDGE_SHIFT 0
0200 #define GRGPIO_IEDGE_EDGE_MASK 0xffffffffU
0201 #define GRGPIO_IEDGE_EDGE_GET( _reg ) \
0202   ( ( ( _reg ) & GRGPIO_IEDGE_EDGE_MASK ) >> \
0203     GRGPIO_IEDGE_EDGE_SHIFT )
0204 #define GRGPIO_IEDGE_EDGE_SET( _reg, _val ) \
0205   ( ( ( _reg ) & ~GRGPIO_IEDGE_EDGE_MASK ) | \
0206     ( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & \
0207       GRGPIO_IEDGE_EDGE_MASK ) )
0208 #define GRGPIO_IEDGE_EDGE( _val ) \
0209   ( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & \
0210     GRGPIO_IEDGE_EDGE_MASK )
0211
0212 /** @} */
0213
0214 /**
0215  * @defgroup RTEMSDeviceGRGPIOBYPASS Bypass register (BYPASS)
0216  *
0217  * @brief This group contains register bit definitions.
0218  *
0219  * @{
0220  */
0221
0222 #define GRGPIO_BYPASS_BYPASS_SHIFT 0
0223 #define GRGPIO_BYPASS_BYPASS_MASK 0xffffffffU
0224 #define GRGPIO_BYPASS_BYPASS_GET( _reg ) \
0225   ( ( ( _reg ) & GRGPIO_BYPASS_BYPASS_MASK ) >> \
0226     GRGPIO_BYPASS_BYPASS_SHIFT )
0227 #define GRGPIO_BYPASS_BYPASS_SET( _reg, _val ) \
0228   ( ( ( _reg ) & ~GRGPIO_BYPASS_BYPASS_MASK ) | \
0229     ( ( ( _val ) << GRGPIO_BYPASS_BYPASS_SHIFT ) & \
0230       GRGPIO_BYPASS_BYPASS_MASK ) )
0231 #define GRGPIO_BYPASS_BYPASS( _val ) \
0232   ( ( ( _val ) << GRGPIO_BYPASS_BYPASS_SHIFT ) & \
0233     GRGPIO_BYPASS_BYPASS_MASK )
0234
0235 /** @} */
0236
0237 /**
0238  * @defgroup RTEMSDeviceGRGPIOCAP Capability register (CAP)
0239  *
0240  * @brief This group contains register bit definitions.
0241  *
0242  * @{
0243  */
0244
0245 #define GRGPIO_CAP_PU 0x40000U
0246
0247 #define GRGPIO_CAP_IER 0x20000U
0248
0249 #define GRGPIO_CAP_IFL 0x10000U
0250
0251 #define GRGPIO_CAP_IRQGEN_SHIFT 8
0252 #define GRGPIO_CAP_IRQGEN_MASK 0x1f00U
0253 #define GRGPIO_CAP_IRQGEN_GET( _reg ) \
0254   ( ( ( _reg ) & GRGPIO_CAP_IRQGEN_MASK ) >> \
0255     GRGPIO_CAP_IRQGEN_SHIFT )
0256 #define GRGPIO_CAP_IRQGEN_SET( _reg, _val ) \
0257   ( ( ( _reg ) & ~GRGPIO_CAP_IRQGEN_MASK ) | \
0258     ( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & \
0259       GRGPIO_CAP_IRQGEN_MASK ) )
0260 #define GRGPIO_CAP_IRQGEN( _val ) \
0261   ( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & \
0262     GRGPIO_CAP_IRQGEN_MASK )
0263
0264 #define GRGPIO_CAP_NLINES_SHIFT 0
0265 #define GRGPIO_CAP_NLINES_MASK 0x1fU
0266 #define GRGPIO_CAP_NLINES_GET( _reg ) \
0267   ( ( ( _reg ) & GRGPIO_CAP_NLINES_MASK ) >> \
0268     GRGPIO_CAP_NLINES_SHIFT )
0269 #define GRGPIO_CAP_NLINES_SET( _reg, _val ) \
0270   ( ( ( _reg ) & ~GRGPIO_CAP_NLINES_MASK ) | \
0271     ( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & \
0272       GRGPIO_CAP_NLINES_MASK ) )
0273 #define GRGPIO_CAP_NLINES( _val ) \
0274   ( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & \
0275     GRGPIO_CAP_NLINES_MASK )
0276
0277 /** @} */
0278
0279 /**
0280  * @defgroup RTEMSDeviceGRGPIOIRQMAPR \
0281  *   Interrupt map register n, where n = 0 .. 3 (IRQMAPR)
0282  *
0283  * @brief This group contains register bit definitions.
0284  *
0285  * @{
0286  */
0287
0288 #define GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT 24
0289 #define GRGPIO_IRQMAPR_IRQMAP_I_0_MASK 0x1f000000U
0290 #define GRGPIO_IRQMAPR_IRQMAP_I_0_GET( _reg ) \
0291   ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) >> \
0292     GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT )
0293 #define GRGPIO_IRQMAPR_IRQMAP_I_0_SET( _reg, _val ) \
0294   ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) | \
0295     ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) & \
0296       GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) )
0297 #define GRGPIO_IRQMAPR_IRQMAP_I_0( _val ) \
0298   ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) & \
0299     GRGPIO_IRQMAPR_IRQMAP_I_0_MASK )
0300
0301 #define GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT 16
0302 #define GRGPIO_IRQMAPR_IRQMAP_I_1_MASK 0x1f0000U
0303 #define GRGPIO_IRQMAPR_IRQMAP_I_1_GET( _reg ) \
0304   ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) >> \
0305     GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT )
0306 #define GRGPIO_IRQMAPR_IRQMAP_I_1_SET( _reg, _val ) \
0307   ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) | \
0308     ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT ) & \
0309       GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) )
0310 #define GRGPIO_IRQMAPR_IRQMAP_I_1( _val ) \
0311   ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT ) & \
0312     GRGPIO_IRQMAPR_IRQMAP_I_1_MASK )
0313
0314 #define GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT 8
0315 #define GRGPIO_IRQMAPR_IRQMAP_I_2_MASK 0x1f00U
0316 #define GRGPIO_IRQMAPR_IRQMAP_I_2_GET( _reg ) \
0317   ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) >> \
0318     GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT )
0319 #define GRGPIO_IRQMAPR_IRQMAP_I_2_SET( _reg, _val ) \
0320   ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) | \
0321     ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT ) & \
0322       GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) )
0323 #define GRGPIO_IRQMAPR_IRQMAP_I_2( _val ) \
0324   ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT ) & \
0325     GRGPIO_IRQMAPR_IRQMAP_I_2_MASK )
0326
0327 #define GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT 0
0328 #define GRGPIO_IRQMAPR_IRQMAP_I_3_MASK 0x1fU
0329 #define GRGPIO_IRQMAPR_IRQMAP_I_3_GET( _reg ) \
0330   ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) >> \
0331     GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT )
0332 #define GRGPIO_IRQMAPR_IRQMAP_I_3_SET( _reg, _val ) \
0333   ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) | \
0334     ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) & \
0335       GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) )
0336 #define GRGPIO_IRQMAPR_IRQMAP_I_3( _val ) \
0337   ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) & \
0338     GRGPIO_IRQMAPR_IRQMAP_I_3_MASK )
0339
0340 /** @} */
0341
0342 /**
0343  * @defgroup RTEMSDeviceGRGPIOIAVAIL Interrupt available register (IAVAIL)
0344  *
0345  * @brief This group contains register bit definitions.
0346  *
0347  * @{
0348  */
0349
0350 #define GRGPIO_IAVAIL_IMASK_SHIFT 0
0351 #define GRGPIO_IAVAIL_IMASK_MASK 0xffffffffU
0352 #define GRGPIO_IAVAIL_IMASK_GET( _reg ) \
0353   ( ( ( _reg ) & GRGPIO_IAVAIL_IMASK_MASK ) >> \
0354     GRGPIO_IAVAIL_IMASK_SHIFT )
0355 #define GRGPIO_IAVAIL_IMASK_SET( _reg, _val ) \
0356   ( ( ( _reg ) & ~GRGPIO_IAVAIL_IMASK_MASK ) | \
0357     ( ( ( _val ) << GRGPIO_IAVAIL_IMASK_SHIFT ) & \
0358       GRGPIO_IAVAIL_IMASK_MASK ) )
0359 #define GRGPIO_IAVAIL_IMASK( _val ) \
0360   ( ( ( _val ) << GRGPIO_IAVAIL_IMASK_SHIFT ) & \
0361     GRGPIO_IAVAIL_IMASK_MASK )
0362
0363 /** @} */
0364
0365 /**
0366  * @defgroup RTEMSDeviceGRGPIOIFLAG Interrupt flag register (IFLAG)
0367  *
0368  * @brief This group contains register bit definitions.
0369  *
0370  * @{
0371  */
0372
0373 #define GRGPIO_IFLAG_IFLAG_SHIFT 0
0374 #define GRGPIO_IFLAG_IFLAG_MASK 0xffffffffU
0375 #define GRGPIO_IFLAG_IFLAG_GET( _reg ) \
0376   ( ( ( _reg ) & GRGPIO_IFLAG_IFLAG_MASK ) >> \
0377     GRGPIO_IFLAG_IFLAG_SHIFT )
0378 #define GRGPIO_IFLAG_IFLAG_SET( _reg, _val ) \
0379   ( ( ( _reg ) & ~GRGPIO_IFLAG_IFLAG_MASK ) | \
0380     ( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & \
0381       GRGPIO_IFLAG_IFLAG_MASK ) )
0382 #define GRGPIO_IFLAG_IFLAG( _val ) \
0383   ( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & \
0384     GRGPIO_IFLAG_IFLAG_MASK )
0385
0386 /** @} */
0387
0388 /**
0389  * @defgroup RTEMSDeviceGRGPIOIPEN Interrupt enable register (IPEN)
0390  *
0391  * @brief This group contains register bit definitions.
0392  *
0393  * @{
0394  */
0395
0396 #define GRGPIO_IPEN_IPEN_SHIFT 0
0397 #define GRGPIO_IPEN_IPEN_MASK 0xffffffffU
0398 #define GRGPIO_IPEN_IPEN_GET( _reg ) \
0399   ( ( ( _reg ) & GRGPIO_IPEN_IPEN_MASK ) >> \
0400     GRGPIO_IPEN_IPEN_SHIFT )
0401 #define GRGPIO_IPEN_IPEN_SET( _reg, _val ) \
0402   ( ( ( _reg ) & ~GRGPIO_IPEN_IPEN_MASK ) | \
0403     ( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & \
0404       GRGPIO_IPEN_IPEN_MASK ) )
0405 #define GRGPIO_IPEN_IPEN( _val ) \
0406   ( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & \
0407     GRGPIO_IPEN_IPEN_MASK )
0408
0409 /** @} */
0410
0411 /**
0412  * @defgroup RTEMSDeviceGRGPIOPULSE Pulse register (PULSE)
0413  *
0414  * @brief This group contains register bit definitions.
0415  *
0416  * @{
0417  */
0418
0419 #define GRGPIO_PULSE_PULSE_SHIFT 0
0420 #define GRGPIO_PULSE_PULSE_MASK 0xffffffffU
0421 #define GRGPIO_PULSE_PULSE_GET( _reg ) \
0422   ( ( ( _reg ) & GRGPIO_PULSE_PULSE_MASK ) >> \
0423     GRGPIO_PULSE_PULSE_SHIFT )
0424 #define GRGPIO_PULSE_PULSE_SET( _reg, _val ) \
0425   ( ( ( _reg ) & ~GRGPIO_PULSE_PULSE_MASK ) | \
0426     ( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & \
0427       GRGPIO_PULSE_PULSE_MASK ) )
0428 #define GRGPIO_PULSE_PULSE( _val ) \
0429   ( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & \
0430     GRGPIO_PULSE_PULSE_MASK )
0431
0432 /** @} */
0433
0434 /**
0435  * @defgroup RTEMSDeviceGRGPIOLOR Logical-OR registers (LOR)
0436  *
0437  * @brief This group contains register bit definitions.
0438  *
0439  * @{
0440  */
0441
0442 #define GRGPIO_LOR_DATA_SHIFT 0
0443 #define GRGPIO_LOR_DATA_MASK 0xffffffffU
0444 #define GRGPIO_LOR_DATA_GET( _reg ) \
0445   ( ( ( _reg ) & GRGPIO_LOR_DATA_MASK ) >> \
0446     GRGPIO_LOR_DATA_SHIFT )
0447 #define GRGPIO_LOR_DATA_SET( _reg, _val ) \
0448   ( ( ( _reg ) & ~GRGPIO_LOR_DATA_MASK ) | \
0449     ( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & \
0450       GRGPIO_LOR_DATA_MASK ) )
0451 #define GRGPIO_LOR_DATA( _val ) \
0452   ( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & \
0453     GRGPIO_LOR_DATA_MASK )
0454
0455 /** @} */
0456
0457 /**
0458  * @defgroup RTEMSDeviceGRGPIOLAND Logical-AND registers (LAND)
0459  *
0460  * @brief This group contains register bit definitions.
0461  *
0462  * @{
0463  */
0464
0465 #define GRGPIO_LAND_DATA_SHIFT 0
0466 #define GRGPIO_LAND_DATA_MASK 0xffffffffU
0467 #define GRGPIO_LAND_DATA_GET( _reg ) \
0468   ( ( ( _reg ) & GRGPIO_LAND_DATA_MASK ) >> \
0469     GRGPIO_LAND_DATA_SHIFT )
0470 #define GRGPIO_LAND_DATA_SET( _reg, _val ) \
0471   ( ( ( _reg ) & ~GRGPIO_LAND_DATA_MASK ) | \
0472     ( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & \
0473       GRGPIO_LAND_DATA_MASK ) )
0474 #define GRGPIO_LAND_DATA( _val ) \
0475   ( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & \
0476     GRGPIO_LAND_DATA_MASK )
0477
0478 /** @} */
0479
0480 /**
0481  * @defgroup RTEMSDeviceGRGPIOLXOR Logical-XOR registers (LXOR)
0482  *
0483  * @brief This group contains register bit definitions.
0484  *
0485  * @{
0486  */
0487
0488 #define GRGPIO_LXOR_DATA_SHIFT 0
0489 #define GRGPIO_LXOR_DATA_MASK 0xffffffffU
0490 #define GRGPIO_LXOR_DATA_GET( _reg ) \
0491   ( ( ( _reg ) & GRGPIO_LXOR_DATA_MASK ) >> \
0492     GRGPIO_LXOR_DATA_SHIFT )
0493 #define GRGPIO_LXOR_DATA_SET( _reg, _val ) \
0494   ( ( ( _reg ) & ~GRGPIO_LXOR_DATA_MASK ) | \
0495     ( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & \
0496       GRGPIO_LXOR_DATA_MASK ) )
0497 #define GRGPIO_LXOR_DATA( _val ) \
0498   ( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & \
0499     GRGPIO_LXOR_DATA_MASK )
0500
0501 /** @} */
0502
0503 /**
0504  * @brief This structure defines the GRGPIO register block memory map.
0505  */
0506 typedef struct grgpio {
0507   /**
0508    * @brief See @ref RTEMSDeviceGRGPIODATA.
0509    */
0510   uint32_t data;
0511
0512   /**
0513    * @brief See @ref RTEMSDeviceGRGPIOOUTPUT.
0514    */
0515   uint32_t output;
0516
0517   /**
0518    * @brief See @ref RTEMSDeviceGRGPIODIRECTION.
0519    */
0520   uint32_t direction;
0521
0522   /**
0523    * @brief See @ref RTEMSDeviceGRGPIOIMASK.
0524    */
0525   uint32_t imask;
0526
0527   /**
0528    * @brief See @ref RTEMSDeviceGRGPIOIPOL.
0529    */
0530   uint32_t ipol;
0531
0532   /**
0533    * @brief See @ref RTEMSDeviceGRGPIOIEDGE.
0534    */
0535   uint32_t iedge;
0536
0537   /**
0538    * @brief See @ref RTEMSDeviceGRGPIOBYPASS.
0539    */
0540   uint32_t bypass;
0541
0542   /**
0543    * @brief See @ref RTEMSDeviceGRGPIOCAP.
0544    */
0545   uint32_t cap;
0546
0547   /**
0548    * @brief See @ref RTEMSDeviceGRGPIOIRQMAPR.
0549    */
0550   uint32_t irqmapr[ 8 ];
0551
0552   /**
0553    * @brief See @ref RTEMSDeviceGRGPIOIAVAIL.
0554    */
0555   uint32_t iavail;
0556
0557   /**
0558    * @brief See @ref RTEMSDeviceGRGPIOIFLAG.
0559    */
0560   uint32_t iflag;
0561
0562   /**
0563    * @brief See @ref RTEMSDeviceGRGPIOIPEN.
0564    */
0565   uint32_t ipen;
0566
0567   /**
0568    * @brief See @ref RTEMSDeviceGRGPIOPULSE.
0569    */
0570   uint32_t pulse;
0571
0572   uint32_t reserved_50_54;
0573
0574   /**
0575    * @brief See @ref RTEMSDeviceGRGPIOLOR.
0576    */
0577   uint32_t lor_output;
0578
0579   /**
0580    * @brief See @ref RTEMSDeviceGRGPIOLOR.
0581    */
0582   uint32_t lor_direction;
0583
0584   /**
0585    * @brief See @ref RTEMSDeviceGRGPIOLOR.
0586    */
0587   uint32_t lor_imask;
0588
0589   uint32_t reserved_60_64;
0590
0591   /**
0592    * @brief See @ref RTEMSDeviceGRGPIOLAND.
0593    */
0594   uint32_t land_output;
0595
0596   /**
0597    * @brief See @ref RTEMSDeviceGRGPIOLAND.
0598    */
0599   uint32_t land_direction;
0600
0601   /**
0602    * @brief See @ref RTEMSDeviceGRGPIOLAND.
0603    */
0604   uint32_t land_imask;
0605
0606   uint32_t reserved_70_74;
0607
0608   /**
0609    * @brief See @ref RTEMSDeviceGRGPIOLXOR.
0610    */
0611   uint32_t lxor_output;
0612
0613   /**
0614    * @brief See @ref RTEMSDeviceGRGPIOLXOR.
0615    */
0616   uint32_t lxor_direction;
0617
0618   /**
0619    * @brief See @ref RTEMSDeviceGRGPIOLXOR.
0620    */
0621   uint32_t lxor_imask;
0622 } grgpio;
0623
0624 /** @} */
0625
0626 #ifdef __cplusplus
0627 }
0628 #endif
0629
0630 #endif /* _GRLIB_GRGPIO_REGS_H */