include/grlib/grethgbit-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRETHGBIT
0007  *
0008  * @brief This header file defines the GRETH_GBIT register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/grethgbit-header */
0054
0055 #ifndef _GRLIB_GRETHGBIT_REGS_H
0056 #define _GRLIB_GRETHGBIT_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/grethgbit */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRETHGBIT GRETH_GBIT
0068  *
0069  * @ingroup RTEMSDeviceGRLIB
0070  *
0071  * @brief This group contains the GRETH_GBIT interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRETHGBITCR control register (CR)
0078  *
0079  * @brief This group contains register bit definitions.
0080  *
0081  * @{
0082  */
0083
0084 #define GRETHGBIT_CR_EA 0x80000000U
0085
0086 #define GRETHGBIT_CR_BS_SHIFT 28
0087 #define GRETHGBIT_CR_BS_MASK 0x70000000U
0088 #define GRETHGBIT_CR_BS_GET( _reg ) \
0089   ( ( ( _reg ) & GRETHGBIT_CR_BS_MASK ) >> \
0090     GRETHGBIT_CR_BS_SHIFT )
0091 #define GRETHGBIT_CR_BS_SET( _reg, _val ) \
0092   ( ( ( _reg ) & ~GRETHGBIT_CR_BS_MASK ) | \
0093     ( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & \
0094       GRETHGBIT_CR_BS_MASK ) )
0095 #define GRETHGBIT_CR_BS( _val ) \
0096   ( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & \
0097     GRETHGBIT_CR_BS_MASK )
0098
0099 #define GRETHGBIT_CR_GA 0x8000000U
0100
0101 #define GRETHGBIT_CR_MA 0x4000000U
0102
0103 #define GRETHGBIT_CR_MC 0x2000000U
0104
0105 #define GRETHGBIT_CR_ED 0x4000U
0106
0107 #define GRETHGBIT_CR_RD 0x2000U
0108
0109 #define GRETHGBIT_CR_DD 0x1000U
0110
0111 #define GRETHGBIT_CR_ME 0x800U
0112
0113 #define GRETHGBIT_CR_PI 0x400U
0114
0115 #define GRETHGBIT_CR_BM 0x200U
0116
0117 #define GRETHGBIT_CR_GB 0x100U
0118
0119 #define GRETHGBIT_CR_SP 0x80U
0120
0121 #define GRETHGBIT_CR_RS 0x40U
0122
0123 #define GRETHGBIT_CR_PM 0x20U
0124
0125 #define GRETHGBIT_CR_FD 0x10U
0126
0127 #define GRETHGBIT_CR_RI 0x8U
0128
0129 #define GRETHGBIT_CR_TI 0x4U
0130
0131 #define GRETHGBIT_CR_RE 0x2U
0132
0133 #define GRETHGBIT_CR_TE 0x1U
0134
0135 /** @} */
0136
0137 /**
0138  * @defgroup RTEMSDeviceGRETHGBITSR status register. (SR)
0139  *
0140  * @brief This group contains register bit definitions.
0141  *
0142  * @{
0143  */
0144
0145 #define GRETHGBIT_SR_PS 0x100U
0146
0147 #define GRETHGBIT_SR_IA 0x80U
0148
0149 #define GRETHGBIT_SR_TS 0x40U
0150
0151 #define GRETHGBIT_SR_TA 0x20U
0152
0153 #define GRETHGBIT_SR_RA 0x10U
0154
0155 #define GRETHGBIT_SR_TI 0x8U
0156
0157 #define GRETHGBIT_SR_RI 0x4U
0158
0159 #define GRETHGBIT_SR_TE 0x2U
0160
0161 #define GRETHGBIT_SR_RE 0x1U
0162
0163 /** @} */
0164
0165 /**
0166  * @defgroup RTEMSDeviceGRETHGBITMACMSB MAC address MSB. (MACMSB)
0167  *
0168  * @brief This group contains register bit definitions.
0169  *
0170  * @{
0171  */
0172
0173 #define GRETHGBIT_MACMSB_MSB_SHIFT 0
0174 #define GRETHGBIT_MACMSB_MSB_MASK 0xffffU
0175 #define GRETHGBIT_MACMSB_MSB_GET( _reg ) \
0176   ( ( ( _reg ) & GRETHGBIT_MACMSB_MSB_MASK ) >> \
0177     GRETHGBIT_MACMSB_MSB_SHIFT )
0178 #define GRETHGBIT_MACMSB_MSB_SET( _reg, _val ) \
0179   ( ( ( _reg ) & ~GRETHGBIT_MACMSB_MSB_MASK ) | \
0180     ( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & \
0181       GRETHGBIT_MACMSB_MSB_MASK ) )
0182 #define GRETHGBIT_MACMSB_MSB( _val ) \
0183   ( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & \
0184     GRETHGBIT_MACMSB_MSB_MASK )
0185
0186 /** @} */
0187
0188 /**
0189  * @defgroup RTEMSDeviceGRETHGBITMACLSB MAC address LSB. (MACLSB)
0190  *
0191  * @brief This group contains register bit definitions.
0192  *
0193  * @{
0194  */
0195
0196 #define GRETHGBIT_MACLSB_LSB_SHIFT 0
0197 #define GRETHGBIT_MACLSB_LSB_MASK 0xffffffffU
0198 #define GRETHGBIT_MACLSB_LSB_GET( _reg ) \
0199   ( ( ( _reg ) & GRETHGBIT_MACLSB_LSB_MASK ) >> \
0200     GRETHGBIT_MACLSB_LSB_SHIFT )
0201 #define GRETHGBIT_MACLSB_LSB_SET( _reg, _val ) \
0202   ( ( ( _reg ) & ~GRETHGBIT_MACLSB_LSB_MASK ) | \
0203     ( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & \
0204       GRETHGBIT_MACLSB_LSB_MASK ) )
0205 #define GRETHGBIT_MACLSB_LSB( _val ) \
0206   ( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & \
0207     GRETHGBIT_MACLSB_LSB_MASK )
0208
0209 /** @} */
0210
0211 /**
0212  * @defgroup RTEMSDeviceGRETHGBITMDIO MDIO control/status register. (MDIO)
0213  *
0214  * @brief This group contains register bit definitions.
0215  *
0216  * @{
0217  */
0218
0219 #define GRETHGBIT_MDIO_DATA_SHIFT 16
0220 #define GRETHGBIT_MDIO_DATA_MASK 0xffff0000U
0221 #define GRETHGBIT_MDIO_DATA_GET( _reg ) \
0222   ( ( ( _reg ) & GRETHGBIT_MDIO_DATA_MASK ) >> \
0223     GRETHGBIT_MDIO_DATA_SHIFT )
0224 #define GRETHGBIT_MDIO_DATA_SET( _reg, _val ) \
0225   ( ( ( _reg ) & ~GRETHGBIT_MDIO_DATA_MASK ) | \
0226     ( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & \
0227       GRETHGBIT_MDIO_DATA_MASK ) )
0228 #define GRETHGBIT_MDIO_DATA( _val ) \
0229   ( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & \
0230     GRETHGBIT_MDIO_DATA_MASK )
0231
0232 #define GRETHGBIT_MDIO_PHYADDR_SHIFT 11
0233 #define GRETHGBIT_MDIO_PHYADDR_MASK 0xf800U
0234 #define GRETHGBIT_MDIO_PHYADDR_GET( _reg ) \
0235   ( ( ( _reg ) & GRETHGBIT_MDIO_PHYADDR_MASK ) >> \
0236     GRETHGBIT_MDIO_PHYADDR_SHIFT )
0237 #define GRETHGBIT_MDIO_PHYADDR_SET( _reg, _val ) \
0238   ( ( ( _reg ) & ~GRETHGBIT_MDIO_PHYADDR_MASK ) | \
0239     ( ( ( _val ) << GRETHGBIT_MDIO_PHYADDR_SHIFT ) & \
0240       GRETHGBIT_MDIO_PHYADDR_MASK ) )
0241 #define GRETHGBIT_MDIO_PHYADDR( _val ) \
0242   ( ( ( _val ) << GRETHGBIT_MDIO_PHYADDR_SHIFT ) & \
0243     GRETHGBIT_MDIO_PHYADDR_MASK )
0244
0245 #define GRETHGBIT_MDIO_REGADDR_SHIFT 6
0246 #define GRETHGBIT_MDIO_REGADDR_MASK 0x7c0U
0247 #define GRETHGBIT_MDIO_REGADDR_GET( _reg ) \
0248   ( ( ( _reg ) & GRETHGBIT_MDIO_REGADDR_MASK ) >> \
0249     GRETHGBIT_MDIO_REGADDR_SHIFT )
0250 #define GRETHGBIT_MDIO_REGADDR_SET( _reg, _val ) \
0251   ( ( ( _reg ) & ~GRETHGBIT_MDIO_REGADDR_MASK ) | \
0252     ( ( ( _val ) << GRETHGBIT_MDIO_REGADDR_SHIFT ) & \
0253       GRETHGBIT_MDIO_REGADDR_MASK ) )
0254 #define GRETHGBIT_MDIO_REGADDR( _val ) \
0255   ( ( ( _val ) << GRETHGBIT_MDIO_REGADDR_SHIFT ) & \
0256     GRETHGBIT_MDIO_REGADDR_MASK )
0257
0258 #define GRETHGBIT_MDIO_BU 0x8U
0259
0260 #define GRETHGBIT_MDIO_LF 0x4U
0261
0262 #define GRETHGBIT_MDIO_RD 0x2U
0263
0264 #define GRETHGBIT_MDIO_WR 0x1U
0265
0266 /** @} */
0267
0268 /**
0269  * @defgroup RTEMSDeviceGRETHGBITTDTBA \
0270  *   transmitter descriptor table base address register. (TDTBA)
0271  *
0272  * @brief This group contains register bit definitions.
0273  *
0274  * @{
0275  */
0276
0277 #define GRETHGBIT_TDTBA_BASEADDR_SHIFT 10
0278 #define GRETHGBIT_TDTBA_BASEADDR_MASK 0xfffffc00U
0279 #define GRETHGBIT_TDTBA_BASEADDR_GET( _reg ) \
0280   ( ( ( _reg ) & GRETHGBIT_TDTBA_BASEADDR_MASK ) >> \
0281     GRETHGBIT_TDTBA_BASEADDR_SHIFT )
0282 #define GRETHGBIT_TDTBA_BASEADDR_SET( _reg, _val ) \
0283   ( ( ( _reg ) & ~GRETHGBIT_TDTBA_BASEADDR_MASK ) | \
0284     ( ( ( _val ) << GRETHGBIT_TDTBA_BASEADDR_SHIFT ) & \
0285       GRETHGBIT_TDTBA_BASEADDR_MASK ) )
0286 #define GRETHGBIT_TDTBA_BASEADDR( _val ) \
0287   ( ( ( _val ) << GRETHGBIT_TDTBA_BASEADDR_SHIFT ) & \
0288     GRETHGBIT_TDTBA_BASEADDR_MASK )
0289
0290 #define GRETHGBIT_TDTBA_DESCPNT_SHIFT 3
0291 #define GRETHGBIT_TDTBA_DESCPNT_MASK 0x3f8U
0292 #define GRETHGBIT_TDTBA_DESCPNT_GET( _reg ) \
0293   ( ( ( _reg ) & GRETHGBIT_TDTBA_DESCPNT_MASK ) >> \
0294     GRETHGBIT_TDTBA_DESCPNT_SHIFT )
0295 #define GRETHGBIT_TDTBA_DESCPNT_SET( _reg, _val ) \
0296   ( ( ( _reg ) & ~GRETHGBIT_TDTBA_DESCPNT_MASK ) | \
0297     ( ( ( _val ) << GRETHGBIT_TDTBA_DESCPNT_SHIFT ) & \
0298       GRETHGBIT_TDTBA_DESCPNT_MASK ) )
0299 #define GRETHGBIT_TDTBA_DESCPNT( _val ) \
0300   ( ( ( _val ) << GRETHGBIT_TDTBA_DESCPNT_SHIFT ) & \
0301     GRETHGBIT_TDTBA_DESCPNT_MASK )
0302
0303 /** @} */
0304
0305 /**
0306  * @defgroup RTEMSDeviceGRETHGBITRDTBA \
0307  *   receiver descriptor table base address register. (RDTBA)
0308  *
0309  * @brief This group contains register bit definitions.
0310  *
0311  * @{
0312  */
0313
0314 #define GRETHGBIT_RDTBA_BASEADDR_SHIFT 10
0315 #define GRETHGBIT_RDTBA_BASEADDR_MASK 0xfffffc00U
0316 #define GRETHGBIT_RDTBA_BASEADDR_GET( _reg ) \
0317   ( ( ( _reg ) & GRETHGBIT_RDTBA_BASEADDR_MASK ) >> \
0318     GRETHGBIT_RDTBA_BASEADDR_SHIFT )
0319 #define GRETHGBIT_RDTBA_BASEADDR_SET( _reg, _val ) \
0320   ( ( ( _reg ) & ~GRETHGBIT_RDTBA_BASEADDR_MASK ) | \
0321     ( ( ( _val ) << GRETHGBIT_RDTBA_BASEADDR_SHIFT ) & \
0322       GRETHGBIT_RDTBA_BASEADDR_MASK ) )
0323 #define GRETHGBIT_RDTBA_BASEADDR( _val ) \
0324   ( ( ( _val ) << GRETHGBIT_RDTBA_BASEADDR_SHIFT ) & \
0325     GRETHGBIT_RDTBA_BASEADDR_MASK )
0326
0327 #define GRETHGBIT_RDTBA_DESCPNT_SHIFT 3
0328 #define GRETHGBIT_RDTBA_DESCPNT_MASK 0x3f8U
0329 #define GRETHGBIT_RDTBA_DESCPNT_GET( _reg ) \
0330   ( ( ( _reg ) & GRETHGBIT_RDTBA_DESCPNT_MASK ) >> \
0331     GRETHGBIT_RDTBA_DESCPNT_SHIFT )
0332 #define GRETHGBIT_RDTBA_DESCPNT_SET( _reg, _val ) \
0333   ( ( ( _reg ) & ~GRETHGBIT_RDTBA_DESCPNT_MASK ) | \
0334     ( ( ( _val ) << GRETHGBIT_RDTBA_DESCPNT_SHIFT ) & \
0335       GRETHGBIT_RDTBA_DESCPNT_MASK ) )
0336 #define GRETHGBIT_RDTBA_DESCPNT( _val ) \
0337   ( ( ( _val ) << GRETHGBIT_RDTBA_DESCPNT_SHIFT ) & \
0338     GRETHGBIT_RDTBA_DESCPNT_MASK )
0339
0340 /** @} */
0341
0342 /**
0343  * @defgroup RTEMSDeviceGRETHGBITEDCLMACMSB EDCL MAC address MSB. (EDCLMACMSB)
0344  *
0345  * @brief This group contains register bit definitions.
0346  *
0347  * @{
0348  */
0349
0350 #define GRETHGBIT_EDCLMACMSB_MSB_SHIFT 0
0351 #define GRETHGBIT_EDCLMACMSB_MSB_MASK 0xffffU
0352 #define GRETHGBIT_EDCLMACMSB_MSB_GET( _reg ) \
0353   ( ( ( _reg ) & GRETHGBIT_EDCLMACMSB_MSB_MASK ) >> \
0354     GRETHGBIT_EDCLMACMSB_MSB_SHIFT )
0355 #define GRETHGBIT_EDCLMACMSB_MSB_SET( _reg, _val ) \
0356   ( ( ( _reg ) & ~GRETHGBIT_EDCLMACMSB_MSB_MASK ) | \
0357     ( ( ( _val ) << GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) & \
0358       GRETHGBIT_EDCLMACMSB_MSB_MASK ) )
0359 #define GRETHGBIT_EDCLMACMSB_MSB( _val ) \
0360   ( ( ( _val ) << GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) & \
0361     GRETHGBIT_EDCLMACMSB_MSB_MASK )
0362
0363 /** @} */
0364
0365 /**
0366  * @defgroup RTEMSDeviceGRETHGBITEDCLMACLSB EDCL MAC address LSB. (EDCLMACLSB)
0367  *
0368  * @brief This group contains register bit definitions.
0369  *
0370  * @{
0371  */
0372
0373 #define GRETHGBIT_EDCLMACLSB_LSB_SHIFT 0
0374 #define GRETHGBIT_EDCLMACLSB_LSB_MASK 0xffffffffU
0375 #define GRETHGBIT_EDCLMACLSB_LSB_GET( _reg ) \
0376   ( ( ( _reg ) & GRETHGBIT_EDCLMACLSB_LSB_MASK ) >> \
0377     GRETHGBIT_EDCLMACLSB_LSB_SHIFT )
0378 #define GRETHGBIT_EDCLMACLSB_LSB_SET( _reg, _val ) \
0379   ( ( ( _reg ) & ~GRETHGBIT_EDCLMACLSB_LSB_MASK ) | \
0380     ( ( ( _val ) << GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) & \
0381       GRETHGBIT_EDCLMACLSB_LSB_MASK ) )
0382 #define GRETHGBIT_EDCLMACLSB_LSB( _val ) \
0383   ( ( ( _val ) << GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) & \
0384     GRETHGBIT_EDCLMACLSB_LSB_MASK )
0385
0386 /** @} */
0387
0388 /**
0389  * @brief This structure defines the GRETH_GBIT register block memory map.
0390  */
0391 typedef struct grethgbit {
0392   /**
0393    * @brief See @ref RTEMSDeviceGRETHGBITCR.
0394    */
0395   uint32_t cr;
0396
0397   /**
0398    * @brief See @ref RTEMSDeviceGRETHGBITSR.
0399    */
0400   uint32_t sr;
0401
0402   /**
0403    * @brief See @ref RTEMSDeviceGRETHGBITMACMSB.
0404    */
0405   uint32_t macmsb;
0406
0407   /**
0408    * @brief See @ref RTEMSDeviceGRETHGBITMACLSB.
0409    */
0410   uint32_t maclsb;
0411
0412   /**
0413    * @brief See @ref RTEMSDeviceGRETHGBITMDIO.
0414    */
0415   uint32_t mdio;
0416
0417   /**
0418    * @brief See @ref RTEMSDeviceGRETHGBITTDTBA.
0419    */
0420   uint32_t tdtba;
0421
0422   /**
0423    * @brief See @ref RTEMSDeviceGRETHGBITRDTBA.
0424    */
0425   uint32_t rdtba;
0426
0427   uint32_t reserved_1c_28[ 3 ];
0428
0429   /**
0430    * @brief See @ref RTEMSDeviceGRETHGBITEDCLMACMSB.
0431    */
0432   uint32_t edclmacmsb;
0433
0434   /**
0435    * @brief See @ref RTEMSDeviceGRETHGBITEDCLMACLSB.
0436    */
0437   uint32_t edclmaclsb;
0438 } grethgbit;
0439
0440 /** @} */
0441
0442 #ifdef __cplusplus
0443 }
0444 #endif
0445
0446 #endif /* _GRLIB_GRETHGBIT_REGS_H */