include/grlib/grclkgate-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRCLKGATE
0007  *
0008  * @brief This header file defines the GRCLKGATE register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/grclkgate-header */
0054
0055 #ifndef _GRLIB_GRCLKGATE_REGS_H
0056 #define _GRLIB_GRCLKGATE_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/grclkgate */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRCLKGATE GRCLKGATE
0068  *
0069  * @ingroup RTEMSDeviceGRLIB
0070  *
0071  * @brief This group contains the GRCLKGATE interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRCLKGATEUNLOCK Unlock register (UNLOCK)
0078  *
0079  * @brief This group contains register bit definitions.
0080  *
0081  * @{
0082  */
0083
0084 #define GRCLKGATE_UNLOCK_UNLOCK_SHIFT 0
0085 #define GRCLKGATE_UNLOCK_UNLOCK_MASK 0xffffffffU
0086 #define GRCLKGATE_UNLOCK_UNLOCK_GET( _reg ) \
0087   ( ( ( _reg ) & GRCLKGATE_UNLOCK_UNLOCK_MASK ) >> \
0088     GRCLKGATE_UNLOCK_UNLOCK_SHIFT )
0089 #define GRCLKGATE_UNLOCK_UNLOCK_SET( _reg, _val ) \
0090   ( ( ( _reg ) & ~GRCLKGATE_UNLOCK_UNLOCK_MASK ) | \
0091     ( ( ( _val ) << GRCLKGATE_UNLOCK_UNLOCK_SHIFT ) & \
0092       GRCLKGATE_UNLOCK_UNLOCK_MASK ) )
0093 #define GRCLKGATE_UNLOCK_UNLOCK( _val ) \
0094   ( ( ( _val ) << GRCLKGATE_UNLOCK_UNLOCK_SHIFT ) & \
0095     GRCLKGATE_UNLOCK_UNLOCK_MASK )
0096
0097 /** @} */
0098
0099 /**
0100  * @defgroup RTEMSDeviceGRCLKGATECLKEN Clock enable register (CLKEN)
0101  *
0102  * @brief This group contains register bit definitions.
0103  *
0104  * @{
0105  */
0106
0107 #define GRCLKGATE_CLKEN_ENABLE_SHIFT 0
0108 #define GRCLKGATE_CLKEN_ENABLE_MASK 0xffffffffU
0109 #define GRCLKGATE_CLKEN_ENABLE_GET( _reg ) \
0110   ( ( ( _reg ) & GRCLKGATE_CLKEN_ENABLE_MASK ) >> \
0111     GRCLKGATE_CLKEN_ENABLE_SHIFT )
0112 #define GRCLKGATE_CLKEN_ENABLE_SET( _reg, _val ) \
0113   ( ( ( _reg ) & ~GRCLKGATE_CLKEN_ENABLE_MASK ) | \
0114     ( ( ( _val ) << GRCLKGATE_CLKEN_ENABLE_SHIFT ) & \
0115       GRCLKGATE_CLKEN_ENABLE_MASK ) )
0116 #define GRCLKGATE_CLKEN_ENABLE( _val ) \
0117   ( ( ( _val ) << GRCLKGATE_CLKEN_ENABLE_SHIFT ) & \
0118     GRCLKGATE_CLKEN_ENABLE_MASK )
0119
0120 /** @} */
0121
0122 /**
0123  * @defgroup RTEMSDeviceGRCLKGATERESET Reset register (RESET)
0124  *
0125  * @brief This group contains register bit definitions.
0126  *
0127  * @{
0128  */
0129
0130 #define GRCLKGATE_RESET_RESET_SHIFT 0
0131 #define GRCLKGATE_RESET_RESET_MASK 0xffffffffU
0132 #define GRCLKGATE_RESET_RESET_GET( _reg ) \
0133   ( ( ( _reg ) & GRCLKGATE_RESET_RESET_MASK ) >> \
0134     GRCLKGATE_RESET_RESET_SHIFT )
0135 #define GRCLKGATE_RESET_RESET_SET( _reg, _val ) \
0136   ( ( ( _reg ) & ~GRCLKGATE_RESET_RESET_MASK ) | \
0137     ( ( ( _val ) << GRCLKGATE_RESET_RESET_SHIFT ) & \
0138       GRCLKGATE_RESET_RESET_MASK ) )
0139 #define GRCLKGATE_RESET_RESET( _val ) \
0140   ( ( ( _val ) << GRCLKGATE_RESET_RESET_SHIFT ) & \
0141     GRCLKGATE_RESET_RESET_MASK )
0142
0143 /** @} */
0144
0145 /**
0146  * @defgroup RTEMSDeviceGRCLKGATEOVERRIDE CPU/FPU override register (OVERRIDE)
0147  *
0148  * @brief This group contains register bit definitions.
0149  *
0150  * @{
0151  */
0152
0153 #define GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT 16
0154 #define GRCLKGATE_OVERRIDE_FOVERRIDE_MASK 0xf0000U
0155 #define GRCLKGATE_OVERRIDE_FOVERRIDE_GET( _reg ) \
0156   ( ( ( _reg ) & GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) >> \
0157     GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT )
0158 #define GRCLKGATE_OVERRIDE_FOVERRIDE_SET( _reg, _val ) \
0159   ( ( ( _reg ) & ~GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) | \
0160     ( ( ( _val ) << GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT ) & \
0161       GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) )
0162 #define GRCLKGATE_OVERRIDE_FOVERRIDE( _val ) \
0163   ( ( ( _val ) << GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT ) & \
0164     GRCLKGATE_OVERRIDE_FOVERRIDE_MASK )
0165
0166 #define GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT 0
0167 #define GRCLKGATE_OVERRIDE_OVERRIDE_MASK 0xfU
0168 #define GRCLKGATE_OVERRIDE_OVERRIDE_GET( _reg ) \
0169   ( ( ( _reg ) & GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) >> \
0170     GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT )
0171 #define GRCLKGATE_OVERRIDE_OVERRIDE_SET( _reg, _val ) \
0172   ( ( ( _reg ) & ~GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) | \
0173     ( ( ( _val ) << GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT ) & \
0174       GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) )
0175 #define GRCLKGATE_OVERRIDE_OVERRIDE( _val ) \
0176   ( ( ( _val ) << GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT ) & \
0177     GRCLKGATE_OVERRIDE_OVERRIDE_MASK )
0178
0179 /** @} */
0180
0181 /**
0182  * @brief This structure defines the GRCLKGATE register block memory map.
0183  */
0184 typedef struct grclkgate {
0185   /**
0186    * @brief See @ref RTEMSDeviceGRCLKGATEUNLOCK.
0187    */
0188   uint32_t unlock;
0189
0190   /**
0191    * @brief See @ref RTEMSDeviceGRCLKGATECLKEN.
0192    */
0193   uint32_t clken;
0194
0195   /**
0196    * @brief See @ref RTEMSDeviceGRCLKGATERESET.
0197    */
0198   uint32_t reset;
0199
0200   /**
0201    * @brief See @ref RTEMSDeviceGRCLKGATEOVERRIDE.
0202    */
0203   uint32_t override;
0204 } grclkgate;
0205
0206 /** @} */
0207
0208 #ifdef __cplusplus
0209 }
0210 #endif
0211
0212 #endif /* _GRLIB_GRCLKGATE_REGS_H */