include/grlib/grcan-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRCAN
0007  *
0008  * @brief This header file defines the GRCAN register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/grcan-header */
0054
0055 #ifndef _GRLIB_GRCAN_REGS_H
0056 #define _GRLIB_GRCAN_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/grcan */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRCAN GRCAN
0068  *
0069  * @ingroup RTEMSDeviceGRLIB
0070  *
0071  * @brief This group contains the GRCAN interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRCANCanCONF Configuration Register (CanCONF)
0078  *
0079  * @brief This group contains register bit definitions.
0080  *
0081  * @{
0082  */
0083
0084 #define GRCAN_CANCONF_SCALER_SHIFT 24
0085 #define GRCAN_CANCONF_SCALER_MASK 0xff000000U
0086 #define GRCAN_CANCONF_SCALER_GET( _reg ) \
0087   ( ( ( _reg ) & GRCAN_CANCONF_SCALER_MASK ) >> \
0088     GRCAN_CANCONF_SCALER_SHIFT )
0089 #define GRCAN_CANCONF_SCALER_SET( _reg, _val ) \
0090   ( ( ( _reg ) & ~GRCAN_CANCONF_SCALER_MASK ) | \
0091     ( ( ( _val ) << GRCAN_CANCONF_SCALER_SHIFT ) & \
0092       GRCAN_CANCONF_SCALER_MASK ) )
0093 #define GRCAN_CANCONF_SCALER( _val ) \
0094   ( ( ( _val ) << GRCAN_CANCONF_SCALER_SHIFT ) & \
0095     GRCAN_CANCONF_SCALER_MASK )
0096
0097 #define GRCAN_CANCONF_PS1_SHIFT 20
0098 #define GRCAN_CANCONF_PS1_MASK 0xf00000U
0099 #define GRCAN_CANCONF_PS1_GET( _reg ) \
0100   ( ( ( _reg ) & GRCAN_CANCONF_PS1_MASK ) >> \
0101     GRCAN_CANCONF_PS1_SHIFT )
0102 #define GRCAN_CANCONF_PS1_SET( _reg, _val ) \
0103   ( ( ( _reg ) & ~GRCAN_CANCONF_PS1_MASK ) | \
0104     ( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & \
0105       GRCAN_CANCONF_PS1_MASK ) )
0106 #define GRCAN_CANCONF_PS1( _val ) \
0107   ( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & \
0108     GRCAN_CANCONF_PS1_MASK )
0109
0110 #define GRCAN_CANCONF_PS2_SHIFT 16
0111 #define GRCAN_CANCONF_PS2_MASK 0xf0000U
0112 #define GRCAN_CANCONF_PS2_GET( _reg ) \
0113   ( ( ( _reg ) & GRCAN_CANCONF_PS2_MASK ) >> \
0114     GRCAN_CANCONF_PS2_SHIFT )
0115 #define GRCAN_CANCONF_PS2_SET( _reg, _val ) \
0116   ( ( ( _reg ) & ~GRCAN_CANCONF_PS2_MASK ) | \
0117     ( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & \
0118       GRCAN_CANCONF_PS2_MASK ) )
0119 #define GRCAN_CANCONF_PS2( _val ) \
0120   ( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & \
0121     GRCAN_CANCONF_PS2_MASK )
0122
0123 #define GRCAN_CANCONF_RSJ_SHIFT 12
0124 #define GRCAN_CANCONF_RSJ_MASK 0x7000U
0125 #define GRCAN_CANCONF_RSJ_GET( _reg ) \
0126   ( ( ( _reg ) & GRCAN_CANCONF_RSJ_MASK ) >> \
0127     GRCAN_CANCONF_RSJ_SHIFT )
0128 #define GRCAN_CANCONF_RSJ_SET( _reg, _val ) \
0129   ( ( ( _reg ) & ~GRCAN_CANCONF_RSJ_MASK ) | \
0130     ( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & \
0131       GRCAN_CANCONF_RSJ_MASK ) )
0132 #define GRCAN_CANCONF_RSJ( _val ) \
0133   ( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & \
0134     GRCAN_CANCONF_RSJ_MASK )
0135
0136 #define GRCAN_CANCONF_BPR_SHIFT 8
0137 #define GRCAN_CANCONF_BPR_MASK 0x300U
0138 #define GRCAN_CANCONF_BPR_GET( _reg ) \
0139   ( ( ( _reg ) & GRCAN_CANCONF_BPR_MASK ) >> \
0140     GRCAN_CANCONF_BPR_SHIFT )
0141 #define GRCAN_CANCONF_BPR_SET( _reg, _val ) \
0142   ( ( ( _reg ) & ~GRCAN_CANCONF_BPR_MASK ) | \
0143     ( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & \
0144       GRCAN_CANCONF_BPR_MASK ) )
0145 #define GRCAN_CANCONF_BPR( _val ) \
0146   ( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & \
0147     GRCAN_CANCONF_BPR_MASK )
0148
0149 #define GRCAN_CANCONF_SAM 0x20U
0150
0151 #define GRCAN_CANCONF_SILNT 0x10U
0152
0153 #define GRCAN_CANCONF_SELECT 0x8U
0154
0155 #define GRCAN_CANCONF_ENABLE1 0x4U
0156
0157 #define GRCAN_CANCONF_ENABLE0 0x2U
0158
0159 #define GRCAN_CANCONF_ABORT 0x1U
0160
0161 /** @} */
0162
0163 /**
0164  * @defgroup RTEMSDeviceGRCANCanSTAT Status Register (CanSTAT)
0165  *
0166  * @brief This group contains register bit definitions.
0167  *
0168  * @{
0169  */
0170
0171 #define GRCAN_CANSTAT_TXCHANNELS_SHIFT 28
0172 #define GRCAN_CANSTAT_TXCHANNELS_MASK 0xf0000000U
0173 #define GRCAN_CANSTAT_TXCHANNELS_GET( _reg ) \
0174   ( ( ( _reg ) & GRCAN_CANSTAT_TXCHANNELS_MASK ) >> \
0175     GRCAN_CANSTAT_TXCHANNELS_SHIFT )
0176 #define GRCAN_CANSTAT_TXCHANNELS_SET( _reg, _val ) \
0177   ( ( ( _reg ) & ~GRCAN_CANSTAT_TXCHANNELS_MASK ) | \
0178     ( ( ( _val ) << GRCAN_CANSTAT_TXCHANNELS_SHIFT ) & \
0179       GRCAN_CANSTAT_TXCHANNELS_MASK ) )
0180 #define GRCAN_CANSTAT_TXCHANNELS( _val ) \
0181   ( ( ( _val ) << GRCAN_CANSTAT_TXCHANNELS_SHIFT ) & \
0182     GRCAN_CANSTAT_TXCHANNELS_MASK )
0183
0184 #define GRCAN_CANSTAT_RXCHANNELS_SHIFT 24
0185 #define GRCAN_CANSTAT_RXCHANNELS_MASK 0xf000000U
0186 #define GRCAN_CANSTAT_RXCHANNELS_GET( _reg ) \
0187   ( ( ( _reg ) & GRCAN_CANSTAT_RXCHANNELS_MASK ) >> \
0188     GRCAN_CANSTAT_RXCHANNELS_SHIFT )
0189 #define GRCAN_CANSTAT_RXCHANNELS_SET( _reg, _val ) \
0190   ( ( ( _reg ) & ~GRCAN_CANSTAT_RXCHANNELS_MASK ) | \
0191     ( ( ( _val ) << GRCAN_CANSTAT_RXCHANNELS_SHIFT ) & \
0192       GRCAN_CANSTAT_RXCHANNELS_MASK ) )
0193 #define GRCAN_CANSTAT_RXCHANNELS( _val ) \
0194   ( ( ( _val ) << GRCAN_CANSTAT_RXCHANNELS_SHIFT ) & \
0195     GRCAN_CANSTAT_RXCHANNELS_MASK )
0196
0197 #define GRCAN_CANSTAT_TXERRCNT_SHIFT 16
0198 #define GRCAN_CANSTAT_TXERRCNT_MASK 0xff0000U
0199 #define GRCAN_CANSTAT_TXERRCNT_GET( _reg ) \
0200   ( ( ( _reg ) & GRCAN_CANSTAT_TXERRCNT_MASK ) >> \
0201     GRCAN_CANSTAT_TXERRCNT_SHIFT )
0202 #define GRCAN_CANSTAT_TXERRCNT_SET( _reg, _val ) \
0203   ( ( ( _reg ) & ~GRCAN_CANSTAT_TXERRCNT_MASK ) | \
0204     ( ( ( _val ) << GRCAN_CANSTAT_TXERRCNT_SHIFT ) & \
0205       GRCAN_CANSTAT_TXERRCNT_MASK ) )
0206 #define GRCAN_CANSTAT_TXERRCNT( _val ) \
0207   ( ( ( _val ) << GRCAN_CANSTAT_TXERRCNT_SHIFT ) & \
0208     GRCAN_CANSTAT_TXERRCNT_MASK )
0209
0210 #define GRCAN_CANSTAT_RXERRCNT_SHIFT 8
0211 #define GRCAN_CANSTAT_RXERRCNT_MASK 0xff00U
0212 #define GRCAN_CANSTAT_RXERRCNT_GET( _reg ) \
0213   ( ( ( _reg ) & GRCAN_CANSTAT_RXERRCNT_MASK ) >> \
0214     GRCAN_CANSTAT_RXERRCNT_SHIFT )
0215 #define GRCAN_CANSTAT_RXERRCNT_SET( _reg, _val ) \
0216   ( ( ( _reg ) & ~GRCAN_CANSTAT_RXERRCNT_MASK ) | \
0217     ( ( ( _val ) << GRCAN_CANSTAT_RXERRCNT_SHIFT ) & \
0218       GRCAN_CANSTAT_RXERRCNT_MASK ) )
0219 #define GRCAN_CANSTAT_RXERRCNT( _val ) \
0220   ( ( ( _val ) << GRCAN_CANSTAT_RXERRCNT_SHIFT ) & \
0221     GRCAN_CANSTAT_RXERRCNT_MASK )
0222
0223 #define GRCAN_CANSTAT_ACTIVE 0x10U
0224
0225 #define GRCAN_CANSTAT_AHBERR 0x8U
0226
0227 #define GRCAN_CANSTAT_OR 0x4U
0228
0229 #define GRCAN_CANSTAT_OFF 0x2U
0230
0231 #define GRCAN_CANSTAT_PASS 0x1U
0232
0233 /** @} */
0234
0235 /**
0236  * @defgroup RTEMSDeviceGRCANCanCTRL Control Register (CanCTRL)
0237  *
0238  * @brief This group contains register bit definitions.
0239  *
0240  * @{
0241  */
0242
0243 #define GRCAN_CANCTRL_RESET 0x2U
0244
0245 #define GRCAN_CANCTRL_ENABLE 0x1U
0246
0247 /** @} */
0248
0249 /**
0250  * @defgroup RTEMSDeviceGRCANCanMASK SYNC Mask Filter Register (CanMASK)
0251  *
0252  * @brief This group contains register bit definitions.
0253  *
0254  * @{
0255  */
0256
0257 #define GRCAN_CANMASK_MASK_SHIFT 0
0258 #define GRCAN_CANMASK_MASK_MASK 0x1fffffffU
0259 #define GRCAN_CANMASK_MASK_GET( _reg ) \
0260   ( ( ( _reg ) & GRCAN_CANMASK_MASK_MASK ) >> \
0261     GRCAN_CANMASK_MASK_SHIFT )
0262 #define GRCAN_CANMASK_MASK_SET( _reg, _val ) \
0263   ( ( ( _reg ) & ~GRCAN_CANMASK_MASK_MASK ) | \
0264     ( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & \
0265       GRCAN_CANMASK_MASK_MASK ) )
0266 #define GRCAN_CANMASK_MASK( _val ) \
0267   ( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & \
0268     GRCAN_CANMASK_MASK_MASK )
0269
0270 /** @} */
0271
0272 /**
0273  * @defgroup RTEMSDeviceGRCANCanCODE SYNC Code Filter Register (CanCODE)
0274  *
0275  * @brief This group contains register bit definitions.
0276  *
0277  * @{
0278  */
0279
0280 #define GRCAN_CANCODE_SYNC_SHIFT 0
0281 #define GRCAN_CANCODE_SYNC_MASK 0x1fffffffU
0282 #define GRCAN_CANCODE_SYNC_GET( _reg ) \
0283   ( ( ( _reg ) & GRCAN_CANCODE_SYNC_MASK ) >> \
0284     GRCAN_CANCODE_SYNC_SHIFT )
0285 #define GRCAN_CANCODE_SYNC_SET( _reg, _val ) \
0286   ( ( ( _reg ) & ~GRCAN_CANCODE_SYNC_MASK ) | \
0287     ( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & \
0288       GRCAN_CANCODE_SYNC_MASK ) )
0289 #define GRCAN_CANCODE_SYNC( _val ) \
0290   ( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & \
0291     GRCAN_CANCODE_SYNC_MASK )
0292
0293 /** @} */
0294
0295 /**
0296  * @defgroup RTEMSDeviceGRCANCanTxCTRL \
0297  *   Transmit Channel Control Register (CanTxCTRL)
0298  *
0299  * @brief This group contains register bit definitions.
0300  *
0301  * @{
0302  */
0303
0304 #define GRCAN_CANTXCTRL_SINGLE 0x4U
0305
0306 #define GRCAN_CANTXCTRL_ONGOING 0x2U
0307
0308 #define GRCAN_CANTXCTRL_ENABLE 0x1U
0309
0310 /** @} */
0311
0312 /**
0313  * @defgroup RTEMSDeviceGRCANCanTxADDR \
0314  *   Transmit Channel Address Register (CanTxADDR)
0315  *
0316  * @brief This group contains register bit definitions.
0317  *
0318  * @{
0319  */
0320
0321 #define GRCAN_CANTXADDR_ADDR_SHIFT 10
0322 #define GRCAN_CANTXADDR_ADDR_MASK 0xfffffc00U
0323 #define GRCAN_CANTXADDR_ADDR_GET( _reg ) \
0324   ( ( ( _reg ) & GRCAN_CANTXADDR_ADDR_MASK ) >> \
0325     GRCAN_CANTXADDR_ADDR_SHIFT )
0326 #define GRCAN_CANTXADDR_ADDR_SET( _reg, _val ) \
0327   ( ( ( _reg ) & ~GRCAN_CANTXADDR_ADDR_MASK ) | \
0328     ( ( ( _val ) << GRCAN_CANTXADDR_ADDR_SHIFT ) & \
0329       GRCAN_CANTXADDR_ADDR_MASK ) )
0330 #define GRCAN_CANTXADDR_ADDR( _val ) \
0331   ( ( ( _val ) << GRCAN_CANTXADDR_ADDR_SHIFT ) & \
0332     GRCAN_CANTXADDR_ADDR_MASK )
0333
0334 /** @} */
0335
0336 /**
0337  * @defgroup RTEMSDeviceGRCANCanTxSIZE \
0338  *   Transmit Channel Size Register (CanTxSIZE)
0339  *
0340  * @brief This group contains register bit definitions.
0341  *
0342  * @{
0343  */
0344
0345 #define GRCAN_CANTXSIZE_SIZE_SHIFT 6
0346 #define GRCAN_CANTXSIZE_SIZE_MASK 0x1fffc0U
0347 #define GRCAN_CANTXSIZE_SIZE_GET( _reg ) \
0348   ( ( ( _reg ) & GRCAN_CANTXSIZE_SIZE_MASK ) >> \
0349     GRCAN_CANTXSIZE_SIZE_SHIFT )
0350 #define GRCAN_CANTXSIZE_SIZE_SET( _reg, _val ) \
0351   ( ( ( _reg ) & ~GRCAN_CANTXSIZE_SIZE_MASK ) | \
0352     ( ( ( _val ) << GRCAN_CANTXSIZE_SIZE_SHIFT ) & \
0353       GRCAN_CANTXSIZE_SIZE_MASK ) )
0354 #define GRCAN_CANTXSIZE_SIZE( _val ) \
0355   ( ( ( _val ) << GRCAN_CANTXSIZE_SIZE_SHIFT ) & \
0356     GRCAN_CANTXSIZE_SIZE_MASK )
0357
0358 /** @} */
0359
0360 /**
0361  * @defgroup RTEMSDeviceGRCANCanTxWR Transmit Channel Write Register (CanTxWR)
0362  *
0363  * @brief This group contains register bit definitions.
0364  *
0365  * @{
0366  */
0367
0368 #define GRCAN_CANTXWR_WRITE_SHIFT 4
0369 #define GRCAN_CANTXWR_WRITE_MASK 0xffff0U
0370 #define GRCAN_CANTXWR_WRITE_GET( _reg ) \
0371   ( ( ( _reg ) & GRCAN_CANTXWR_WRITE_MASK ) >> \
0372     GRCAN_CANTXWR_WRITE_SHIFT )
0373 #define GRCAN_CANTXWR_WRITE_SET( _reg, _val ) \
0374   ( ( ( _reg ) & ~GRCAN_CANTXWR_WRITE_MASK ) | \
0375     ( ( ( _val ) << GRCAN_CANTXWR_WRITE_SHIFT ) & \
0376       GRCAN_CANTXWR_WRITE_MASK ) )
0377 #define GRCAN_CANTXWR_WRITE( _val ) \
0378   ( ( ( _val ) << GRCAN_CANTXWR_WRITE_SHIFT ) & \
0379     GRCAN_CANTXWR_WRITE_MASK )
0380
0381 /** @} */
0382
0383 /**
0384  * @defgroup RTEMSDeviceGRCANCanTxRD Transmit Channel Read Register (CanTxRD)
0385  *
0386  * @brief This group contains register bit definitions.
0387  *
0388  * @{
0389  */
0390
0391 #define GRCAN_CANTXRD_READ_SHIFT 4
0392 #define GRCAN_CANTXRD_READ_MASK 0xffff0U
0393 #define GRCAN_CANTXRD_READ_GET( _reg ) \
0394   ( ( ( _reg ) & GRCAN_CANTXRD_READ_MASK ) >> \
0395     GRCAN_CANTXRD_READ_SHIFT )
0396 #define GRCAN_CANTXRD_READ_SET( _reg, _val ) \
0397   ( ( ( _reg ) & ~GRCAN_CANTXRD_READ_MASK ) | \
0398     ( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & \
0399       GRCAN_CANTXRD_READ_MASK ) )
0400 #define GRCAN_CANTXRD_READ( _val ) \
0401   ( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & \
0402     GRCAN_CANTXRD_READ_MASK )
0403
0404 /** @} */
0405
0406 /**
0407  * @defgroup RTEMSDeviceGRCANCanTxIRQ \
0408  *   Transmit Channel Interrupt Register (CanTxIRQ)
0409  *
0410  * @brief This group contains register bit definitions.
0411  *
0412  * @{
0413  */
0414
0415 #define GRCAN_CANTXIRQ_IRQ_SHIFT 4
0416 #define GRCAN_CANTXIRQ_IRQ_MASK 0xffff0U
0417 #define GRCAN_CANTXIRQ_IRQ_GET( _reg ) \
0418   ( ( ( _reg ) & GRCAN_CANTXIRQ_IRQ_MASK ) >> \
0419     GRCAN_CANTXIRQ_IRQ_SHIFT )
0420 #define GRCAN_CANTXIRQ_IRQ_SET( _reg, _val ) \
0421   ( ( ( _reg ) & ~GRCAN_CANTXIRQ_IRQ_MASK ) | \
0422     ( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & \
0423       GRCAN_CANTXIRQ_IRQ_MASK ) )
0424 #define GRCAN_CANTXIRQ_IRQ( _val ) \
0425   ( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & \
0426     GRCAN_CANTXIRQ_IRQ_MASK )
0427
0428 /** @} */
0429
0430 /**
0431  * @defgroup RTEMSDeviceGRCANCanRxCTRL \
0432  *   Receive Channel Control Register (CanRxCTRL)
0433  *
0434  * @brief This group contains register bit definitions.
0435  *
0436  * @{
0437  */
0438
0439 #define GRCAN_CANRXCTRL_ONGOING 0x2U
0440
0441 #define GRCAN_CANRXCTRL_ENABLE 0x1U
0442
0443 /** @} */
0444
0445 /**
0446  * @defgroup RTEMSDeviceGRCANCanRxADDR \
0447  *   Receive Channel Address Register (CanRxADDR)
0448  *
0449  * @brief This group contains register bit definitions.
0450  *
0451  * @{
0452  */
0453
0454 #define GRCAN_CANRXADDR_ADDR_SHIFT 10
0455 #define GRCAN_CANRXADDR_ADDR_MASK 0xfffffc00U
0456 #define GRCAN_CANRXADDR_ADDR_GET( _reg ) \
0457   ( ( ( _reg ) & GRCAN_CANRXADDR_ADDR_MASK ) >> \
0458     GRCAN_CANRXADDR_ADDR_SHIFT )
0459 #define GRCAN_CANRXADDR_ADDR_SET( _reg, _val ) \
0460   ( ( ( _reg ) & ~GRCAN_CANRXADDR_ADDR_MASK ) | \
0461     ( ( ( _val ) << GRCAN_CANRXADDR_ADDR_SHIFT ) & \
0462       GRCAN_CANRXADDR_ADDR_MASK ) )
0463 #define GRCAN_CANRXADDR_ADDR( _val ) \
0464   ( ( ( _val ) << GRCAN_CANRXADDR_ADDR_SHIFT ) & \
0465     GRCAN_CANRXADDR_ADDR_MASK )
0466
0467 /** @} */
0468
0469 /**
0470  * @defgroup RTEMSDeviceGRCANCanRxSIZE \
0471  *   Receive Channel Size Register (CanRxSIZE)
0472  *
0473  * @brief This group contains register bit definitions.
0474  *
0475  * @{
0476  */
0477
0478 #define GRCAN_CANRXSIZE_SIZE_SHIFT 6
0479 #define GRCAN_CANRXSIZE_SIZE_MASK 0x1fffc0U
0480 #define GRCAN_CANRXSIZE_SIZE_GET( _reg ) \
0481   ( ( ( _reg ) & GRCAN_CANRXSIZE_SIZE_MASK ) >> \
0482     GRCAN_CANRXSIZE_SIZE_SHIFT )
0483 #define GRCAN_CANRXSIZE_SIZE_SET( _reg, _val ) \
0484   ( ( ( _reg ) & ~GRCAN_CANRXSIZE_SIZE_MASK ) | \
0485     ( ( ( _val ) << GRCAN_CANRXSIZE_SIZE_SHIFT ) & \
0486       GRCAN_CANRXSIZE_SIZE_MASK ) )
0487 #define GRCAN_CANRXSIZE_SIZE( _val ) \
0488   ( ( ( _val ) << GRCAN_CANRXSIZE_SIZE_SHIFT ) & \
0489     GRCAN_CANRXSIZE_SIZE_MASK )
0490
0491 /** @} */
0492
0493 /**
0494  * @defgroup RTEMSDeviceGRCANCanRxWR Receive Channel Write Register (CanRxWR)
0495  *
0496  * @brief This group contains register bit definitions.
0497  *
0498  * @{
0499  */
0500
0501 #define GRCAN_CANRXWR_WRITE_SHIFT 4
0502 #define GRCAN_CANRXWR_WRITE_MASK 0xffff0U
0503 #define GRCAN_CANRXWR_WRITE_GET( _reg ) \
0504   ( ( ( _reg ) & GRCAN_CANRXWR_WRITE_MASK ) >> \
0505     GRCAN_CANRXWR_WRITE_SHIFT )
0506 #define GRCAN_CANRXWR_WRITE_SET( _reg, _val ) \
0507   ( ( ( _reg ) & ~GRCAN_CANRXWR_WRITE_MASK ) | \
0508     ( ( ( _val ) << GRCAN_CANRXWR_WRITE_SHIFT ) & \
0509       GRCAN_CANRXWR_WRITE_MASK ) )
0510 #define GRCAN_CANRXWR_WRITE( _val ) \
0511   ( ( ( _val ) << GRCAN_CANRXWR_WRITE_SHIFT ) & \
0512     GRCAN_CANRXWR_WRITE_MASK )
0513
0514 /** @} */
0515
0516 /**
0517  * @defgroup RTEMSDeviceGRCANCanRxRD Receive Channel Read Register (CanRxRD)
0518  *
0519  * @brief This group contains register bit definitions.
0520  *
0521  * @{
0522  */
0523
0524 #define GRCAN_CANRXRD_READ_SHIFT 4
0525 #define GRCAN_CANRXRD_READ_MASK 0xffff0U
0526 #define GRCAN_CANRXRD_READ_GET( _reg ) \
0527   ( ( ( _reg ) & GRCAN_CANRXRD_READ_MASK ) >> \
0528     GRCAN_CANRXRD_READ_SHIFT )
0529 #define GRCAN_CANRXRD_READ_SET( _reg, _val ) \
0530   ( ( ( _reg ) & ~GRCAN_CANRXRD_READ_MASK ) | \
0531     ( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & \
0532       GRCAN_CANRXRD_READ_MASK ) )
0533 #define GRCAN_CANRXRD_READ( _val ) \
0534   ( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & \
0535     GRCAN_CANRXRD_READ_MASK )
0536
0537 /** @} */
0538
0539 /**
0540  * @defgroup RTEMSDeviceGRCANCanRxIRQ \
0541  *   Receive Channel Interrupt Register (CanRxIRQ)
0542  *
0543  * @brief This group contains register bit definitions.
0544  *
0545  * @{
0546  */
0547
0548 #define GRCAN_CANRXIRQ_IRQ_SHIFT 4
0549 #define GRCAN_CANRXIRQ_IRQ_MASK 0xffff0U
0550 #define GRCAN_CANRXIRQ_IRQ_GET( _reg ) \
0551   ( ( ( _reg ) & GRCAN_CANRXIRQ_IRQ_MASK ) >> \
0552     GRCAN_CANRXIRQ_IRQ_SHIFT )
0553 #define GRCAN_CANRXIRQ_IRQ_SET( _reg, _val ) \
0554   ( ( ( _reg ) & ~GRCAN_CANRXIRQ_IRQ_MASK ) | \
0555     ( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & \
0556       GRCAN_CANRXIRQ_IRQ_MASK ) )
0557 #define GRCAN_CANRXIRQ_IRQ( _val ) \
0558   ( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & \
0559     GRCAN_CANRXIRQ_IRQ_MASK )
0560
0561 /** @} */
0562
0563 /**
0564  * @defgroup RTEMSDeviceGRCANCanRxMASK \
0565  *   Receive Channel Mask Register (CanRxMASK)
0566  *
0567  * @brief This group contains register bit definitions.
0568  *
0569  * @{
0570  */
0571
0572 #define GRCAN_CANRXMASK_AM_SHIFT 0
0573 #define GRCAN_CANRXMASK_AM_MASK 0x1fffffffU
0574 #define GRCAN_CANRXMASK_AM_GET( _reg ) \
0575   ( ( ( _reg ) & GRCAN_CANRXMASK_AM_MASK ) >> \
0576     GRCAN_CANRXMASK_AM_SHIFT )
0577 #define GRCAN_CANRXMASK_AM_SET( _reg, _val ) \
0578   ( ( ( _reg ) & ~GRCAN_CANRXMASK_AM_MASK ) | \
0579     ( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & \
0580       GRCAN_CANRXMASK_AM_MASK ) )
0581 #define GRCAN_CANRXMASK_AM( _val ) \
0582   ( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & \
0583     GRCAN_CANRXMASK_AM_MASK )
0584
0585 /** @} */
0586
0587 /**
0588  * @defgroup RTEMSDeviceGRCANCanRxCODE \
0589  *   Receive Channel Code Register (CanRxCODE)
0590  *
0591  * @brief This group contains register bit definitions.
0592  *
0593  * @{
0594  */
0595
0596 #define GRCAN_CANRXCODE_AC_SHIFT 0
0597 #define GRCAN_CANRXCODE_AC_MASK 0x1fffffffU
0598 #define GRCAN_CANRXCODE_AC_GET( _reg ) \
0599   ( ( ( _reg ) & GRCAN_CANRXCODE_AC_MASK ) >> \
0600     GRCAN_CANRXCODE_AC_SHIFT )
0601 #define GRCAN_CANRXCODE_AC_SET( _reg, _val ) \
0602   ( ( ( _reg ) & ~GRCAN_CANRXCODE_AC_MASK ) | \
0603     ( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & \
0604       GRCAN_CANRXCODE_AC_MASK ) )
0605 #define GRCAN_CANRXCODE_AC( _val ) \
0606   ( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & \
0607     GRCAN_CANRXCODE_AC_MASK )
0608
0609 /** @} */
0610
0611 /**
0612  * @brief This structure defines the GRCAN register block memory map.
0613  */
0614 typedef struct grcan {
0615   /**
0616    * @brief See @ref RTEMSDeviceGRCANCanCONF.
0617    */
0618   uint32_t canconf;
0619
0620   /**
0621    * @brief See @ref RTEMSDeviceGRCANCanSTAT.
0622    */
0623   uint32_t canstat;
0624
0625   /**
0626    * @brief See @ref RTEMSDeviceGRCANCanCTRL.
0627    */
0628   uint32_t canctrl;
0629
0630   uint32_t reserved_c_18[ 3 ];
0631
0632   /**
0633    * @brief See @ref RTEMSDeviceGRCANCanMASK.
0634    */
0635   uint32_t canmask;
0636
0637   /**
0638    * @brief See @ref RTEMSDeviceGRCANCanCODE.
0639    */
0640   uint32_t cancode;
0641
0642   uint32_t reserved_20_200[ 120 ];
0643
0644   /**
0645    * @brief See @ref RTEMSDeviceGRCANCanTxCTRL.
0646    */
0647   uint32_t cantxctrl;
0648
0649   /**
0650    * @brief See @ref RTEMSDeviceGRCANCanTxADDR.
0651    */
0652   uint32_t cantxaddr;
0653
0654   /**
0655    * @brief See @ref RTEMSDeviceGRCANCanTxSIZE.
0656    */
0657   uint32_t cantxsize;
0658
0659   /**
0660    * @brief See @ref RTEMSDeviceGRCANCanTxWR.
0661    */
0662   uint32_t cantxwr;
0663
0664   /**
0665    * @brief See @ref RTEMSDeviceGRCANCanTxRD.
0666    */
0667   uint32_t cantxrd;
0668
0669   /**
0670    * @brief See @ref RTEMSDeviceGRCANCanTxIRQ.
0671    */
0672   uint32_t cantxirq;
0673
0674   uint32_t reserved_218_300[ 58 ];
0675
0676   /**
0677    * @brief See @ref RTEMSDeviceGRCANCanRxCTRL.
0678    */
0679   uint32_t canrxctrl;
0680
0681   /**
0682    * @brief See @ref RTEMSDeviceGRCANCanRxADDR.
0683    */
0684   uint32_t canrxaddr;
0685
0686   /**
0687    * @brief See @ref RTEMSDeviceGRCANCanRxSIZE.
0688    */
0689   uint32_t canrxsize;
0690
0691   /**
0692    * @brief See @ref RTEMSDeviceGRCANCanRxWR.
0693    */
0694   uint32_t canrxwr;
0695
0696   /**
0697    * @brief See @ref RTEMSDeviceGRCANCanRxRD.
0698    */
0699   uint32_t canrxrd;
0700
0701   /**
0702    * @brief See @ref RTEMSDeviceGRCANCanRxIRQ.
0703    */
0704   uint32_t canrxirq;
0705
0706   /**
0707    * @brief See @ref RTEMSDeviceGRCANCanRxMASK.
0708    */
0709   uint32_t canrxmask;
0710
0711   /**
0712    * @brief See @ref RTEMSDeviceGRCANCanRxCODE.
0713    */
0714   uint32_t canrxcode;
0715 } grcan;
0716
0717 /** @} */
0718
0719 #ifdef __cplusplus
0720 }
0721 #endif
0722
0723 #endif /* _GRLIB_GRCAN_REGS_H */