include/grlib/gr_rasta_tmtc.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*  GR-RASTA-TMTC PCI Target driver.
0004  *
0005  *  COPYRIGHT (c) 2008.
0006  *  Cobham Gaisler AB.
0007  *
0008  *  Configures the GR-RASTA-TMTC interface PCI board.
0009  *  This driver provides a AMBA PnP bus by using the general part
0010  *  of the AMBA PnP bus driver (ambapp_bus.c).
0011  *
0012  *  Driver resources for the AMBA PnP bus provided can be set using
0013  *  gr_rasta_tmtc_set_resources().
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifndef __GR_RASTA_TMTC_H__
0038 #define __GR_RASTA_TMTC_H__
0039
0040 #include <drvmgr/drvmgr.h>
0041
0042 #ifdef __cplusplus
0043 extern "C" {
0044 #endif
0045
0046 /* GPIO TM/TC configuration pin definitions
0047  * --31         PWRX                (1=PW2APB,     0=TM VC3/4)
0048  * --30         PWTC                (1=APB2PW,     0=TC MAP1/2)
0049  * --29         Redundant TM        (1=enable,     0=disable)
0050  * --28         Redundant TC        (1=enable,     0=disable)
0051  * --27         Select TM output    (1=GRTM,       0=PTME)
0052  * --26         Loop back PW        (1=enable,     0=disable)
0053  * --25         Transponder clock   (1=PLL,        0=PLL bypass)
0054  * --24         PWTX-SELECT         (0=TX0-0,      1=TX0-1)
0055  * --23         PDEC Map Switch     (1=on,         0=off)
0056  * --22         PDEC Ext CPDU       (1=on,         0=off)
0057  * --21         PDEC Super User     (1=on,         0=off)
0058  * --20         PDEC RM On          (1=on,         0=off)
0059  * --19         PDEC AU Enable      (1=on,         0=off)
0060  * --18         PDEC Dynamic Mode   (1=on,         0=off)
0061  * --17         PDEC Priority       (1=on,         0=off)
0062  * --16         TC PSS Support      (1=on,         0=off)
0063  * --15         TC Mark             (1=on,         0=off)
0064  * --14         TC Pseudo           (1=on,         0=off)
0065  * --13         TC Rising Clock     (1=rise,       0=fall)
0066  * --12         TC Active High      (1=high,       0=low)
0067  * --11         Bit Lock Positive   (1=high,       0=low)
0068  * --10         RF Avail Positive   (1=high,       0=low)
0069  * -- 9 : 0     SpaceCraft ID
0070  */
0071
0072 #define GR_TMTC_GPIO_PWRX       (1<<31)
0073 #define GR_TMTC_GPIO_PWTC       (1<<30)
0074 #define GR_TMTC_GPIO_RED_TM     (1<<29)
0075 #define GR_TMTC_GPIO_RED_TC     (1<<28)
0076 #define GR_TMTC_GPIO_GRTM_SEL       (1<<27)
0077 #define GR_TMTC_GPIO_LB_PW      (1<<26)
0078 #define GR_TMTC_GPIO_TRANSP_CLK     (1<<25)
0079 #define GR_TMTC_GPIO_PWTX_SEL       (1<<24)
0080 #define GR_TMTC_GPIO_PDEC_MAP       (1<<23)
0081 #define GR_TMTC_GPIO_PDEC_CPDU      (1<<22)
0082 #define GR_TMTC_GPIO_PDEC_SU        (1<<21)
0083 #define GR_TMTC_GPIO_PDEC_RM        (1<<20)
0084 #define GR_TMTC_GPIO_PDEC_AU        (1<<19)
0085 #define GR_TMTC_GPIO_PDEC_DYN_MODE  (1<<18)
0086 #define GR_TMTC_GPIO_PDEC_PRIO      (1<<17)
0087 #define GR_TMTC_GPIO_TC_PSS     (1<<16)
0088 #define GR_TMTC_GPIO_TC_MARK        (1<<15)
0089 #define GR_TMTC_GPIO_TC_PSEUDO      (1<<14)
0090 #define GR_TMTC_GPIO_TC_RISING_CLK  (1<<13)
0091 #define GR_TMTC_GPIO_TC_ACTIVE_HIGH (1<<12)
0092 #define GR_TMTC_GPIO_TC_BIT_LOCK    (1<<11)
0093 #define GR_TMTC_GPIO_TC_RF_AVAIL    (1<<10)
0094 #define GR_TMTC_GPIO_SCID       (0x000003ff)
0095
0096 /* An array of pointers to GR-RASTA-TMTC bus resources. The resources will be
0097  * used by the device drivers controlling the cores on the GR-RASTA-IO target
0098  * AMBA bus.
0099  *
0100  * The array is defined weak, and defaults to no resources. The array must be
0101  * terminated with a NULL resource.
0102  */
0103 extern struct drvmgr_bus_res *gr_rasta_tmtc_resources[];
0104
0105 /* Options to gr_rasta_io_print function */
0106 #define RASTA_TMTC_OPTIONS_AMBA   0x01 /* Print AMBA bus devices */
0107 #define RASTA_TMTC_OPTIONS_IRQ    0x02 /* Print current IRQ setup */
0108
0109 /* Print information about GR-RASTA-TMTC PCI boards */
0110 void gr_rasta_tmtc_print(int options);
0111
0112 /* Print information about a GR-RASTA-TMTC PCI boards */
0113 void gr_rasta_tmtc_print_dev(struct drvmgr_dev *dev, int options);
0114
0115 /* Register GR-RASTA-TMTC driver */
0116 void gr_rasta_tmtc_register_drv(void);
0117
0118 #ifdef __cplusplus
0119 }
0120 #endif
0121
0122 #endif