include/grlib/gr1553b.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /* GR1553B driver, used by BC, RT and/or BM driver
0004  *
0005  * COPYRIGHT (c) 2010.
0006  * Cobham Gaisler AB.
0007  *
0008  * Redistribution and use in source and binary forms, with or without
0009  * modification, are permitted provided that the following conditions
0010  * are met:
0011  * 1. Redistributions of source code must retain the above copyright
0012  *    notice, this list of conditions and the following disclaimer.
0013  * 2. Redistributions in binary form must reproduce the above copyright
0014  *    notice, this list of conditions and the following disclaimer in the
0015  *    documentation and/or other materials provided with the distribution.
0016  *
0017  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0018  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0019  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0020  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0021  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0022  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0023  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0024  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0025  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0026  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0027  * POSSIBILITY OF SUCH DAMAGE.
0028  *
0029  * OVERVIEW
0030  * ========
0031  * This driver controls the GR1553B device regardless of interfaces supported
0032  * (BC, RT and/or BM). The device can be located at an on-chip AMBA or an
0033  * AMBA-over-PCI bus. This driver provides an interface for the BC, RT and BM
0034  * drivers to use. Since the different interfaces are accessed over the same
0035  * register interface on the same core, the other drivers must share a GR1553B
0036  * device. Any combination of interface functionality is supported, but the RT
0037  * and BC functionality can nnot be used simultaneously due to hardware
0038  * limitation.
0039  *
0040  */
0041
0042 #ifndef __GR1553B_H__
0043 #define __GR1553B_H__
0044
0045 #include <stdint.h>
0046
0047 #ifdef __cplusplus
0048 extern "C" {
0049 #endif
0050
0051 /* The GR1553B registers */
0052 struct gr1553b_regs {
0053     /* Common Registers */
0054     volatile uint32_t irq;      /* 0x00 IRQ register */
0055     volatile uint32_t imask;    /* 0x04 IRQ enable mask */
0056     int unused0[(0x10-0x08)/4];
0057     volatile uint32_t hwcfg;    /* 0x10 HW config register */
0058
0059     int unused1[(0x40-0x14)/4]; /* Padding */
0060
0061     /* BC Registers */
0062     volatile uint32_t bc_stat;  /* 0x40 BC status */
0063     volatile uint32_t bc_ctrl;  /* 0x44 BC Action register */
0064     volatile uint32_t bc_bd;    /* 0x48 BC transfer list pointer */
0065     volatile uint32_t bc_abd;   /* 0x4c BC async list pointer */
0066     volatile uint32_t bc_timer; /* 0x50 BC timer register */
0067     volatile uint32_t bc_wake;  /* 0x54 BC wakeup control register */
0068     volatile uint32_t bc_irqptr;    /* 0x58 BC transfer IRQ pointer */
0069     volatile uint32_t bc_busmsk;    /* 0x5C BC per-RT bus mask register */
0070
0071     int unused2[(0x68-0x60)/4]; /* Padding */
0072
0073     volatile uint32_t bc_slot;  /* 0x68 BC Current BD pointer */
0074     volatile uint32_t bc_aslot; /* 0x6c BC Current async BD pointer */
0075
0076     int unused3[(0x80-0x70)/4]; /* Padding */
0077
0078     /* RT Registers */
0079     volatile uint32_t rt_stat;  /* 0x80 RT status */
0080     volatile uint32_t rt_cfg;   /* 0x84 RT config register */
0081     volatile uint32_t rt_stat2; /* 0x88 RT bus status bits */
0082     volatile uint32_t rt_statw; /* 0x8c RT status words */
0083     volatile uint32_t rt_sync;  /* 0x90 RT bus synchronize */
0084     volatile uint32_t rt_tab;   /* 0x94 RT subaddress table base */
0085     volatile uint32_t rt_mcctrl;    /* 0x98 RT valid mode code mask */
0086     int unused4[(0xa4-0x9c)/4];
0087     volatile uint32_t rt_ttag;  /* 0xa4 RT time tag register */
0088     int unused5;            /* 0xa8 RESERVED */
0089     volatile uint32_t rt_evsz;  /* 0xac RT event log end pointer */
0090     volatile uint32_t rt_evlog; /* 0xb0 RT event log position */
0091     volatile uint32_t rt_evirq; /* 0xb4 RT event log IRQ position */
0092
0093     int unused6[(0xc0-0xb8)/4]; /* Padding */
0094
0095     /* BM Registers */
0096     volatile uint32_t bm_stat;  /* 0xc0 BM status */
0097     volatile uint32_t bm_ctrl;  /* 0xc4 BM control register */
0098     volatile uint32_t bm_adr;   /* 0xc8 BM address filter */
0099     volatile uint32_t bm_subadr;    /* 0xcc BM subaddress filter */
0100     volatile uint32_t bm_mc;    /* 0xd0 BM mode code filter */
0101     volatile uint32_t bm_start; /* 0xd4 BM log start address */
0102     volatile uint32_t bm_end;   /* 0xd8 BM log size/alignment mask */
0103     volatile uint32_t bm_pos;   /* 0xdc BM log position */
0104     volatile uint32_t bm_ttag;  /* 0xe0 BM time tag register */
0105 };
0106
0107 #define GR1553BC_KEY 0x15520000
0108 #define GR1553RT_KEY 0x15530000
0109
0110 /* IRQ Definitions */
0111 #define GR1553BC_IRQLOG_SIZE 64
0112 #define GR1553BC_IRQLOG_CNT (GR1553BC_IRQLOG_SIZE/sizeof(uint32_t))
0113
0114 /*** IRQ Flag Register ***/
0115 #define GR1553B_IRQ_BCEV_BIT    0
0116 #define GR1553B_IRQ_BCD_BIT 1
0117 #define GR1553B_IRQ_BCWK_BIT    2
0118 #define GR1553B_IRQ_RTEV_BIT    8
0119 #define GR1553B_IRQ_RTD_BIT 9
0120 #define GR1553B_IRQ_RTTE_BIT    10
0121 #define GR1553B_IRQ_BMD_BIT 16
0122 #define GR1553B_IRQ_BMTOF_BIT   17
0123
0124 #define GR1553B_IRQ_BCEV    (1<<GR1553B_IRQ_BCEV_BIT)
0125 #define GR1553B_IRQ_BCD     (1<<GR1553B_IRQ_BCD_BIT)
0126 #define GR1553B_IRQ_BCWK    (1<<GR1553B_IRQ_BCWK_BIT)
0127 #define GR1553B_IRQ_RTEV    (1<<GR1553B_IRQ_RTEV_BIT)
0128 #define GR1553B_IRQ_RTD     (1<<GR1553B_IRQ_RTD_BIT)
0129 #define GR1553B_IRQ_RTTE    (1<<GR1553B_IRQ_RTTE_BIT)
0130 #define GR1553B_IRQ_BMD     (1<<GR1553B_IRQ_BMD_BIT)
0131 #define GR1553B_IRQ_BMTOF       (1<<GR1553B_IRQ_BMTOF_BIT)
0132
0133 /*** IRQ Enable Register ***/
0134 #define GR1553B_IRQEN_BCEVE_BIT 0
0135 #define GR1553B_IRQEN_BCDE_BIT  1
0136 #define GR1553B_IRQEN_BCWKE_BIT 2
0137 #define GR1553B_IRQEN_RTEVE_BIT 8
0138 #define GR1553B_IRQEN_RTDE_BIT  9
0139 #define GR1553B_IRQEN_RTTEE_BIT 10
0140 #define GR1553B_IRQEN_BMDE_BIT  16
0141 #define GR1553B_IRQEN_BMTOE_BIT 17
0142
0143 #define GR1553B_IRQEN_BCEVE (1<<GR1553B_IRQEN_BCEVE_BIT)
0144 #define GR1553B_IRQEN_BCDE  (1<<GR1553B_IRQEN_BCDE_BIT)
0145 #define GR1553B_IRQEN_BCWKE (1<<GR1553B_IRQEN_BCWKE_BIT)
0146 #define GR1553B_IRQEN_RTEVE (1<<GR1553B_IRQEN_RTEVE_BIT)
0147 #define GR1553B_IRQEN_RTDE  (1<<GR1553B_IRQEN_RTDE_BIT)
0148 #define GR1553B_IRQEN_RTTEE (1<<GR1553B_IRQEN_RTTEE_BIT)
0149 #define GR1553B_IRQEN_BMDE  (1<<GR1553B_IRQEN_BMDE_BIT)
0150 #define GR1553B_IRQEN_BMTOE (1<<GR1553B_IRQEN_BMTOE_BIT)
0151
0152 /*** BC Status Register ***/
0153 #define GR1553B_BC_STAT_SCST_BIT    0
0154 #define GR1553B_BC_STAT_SCADL_BIT   3
0155 #define GR1553B_BC_STAT_ASST_BIT    8
0156 #define GR1553B_BC_STAT_ASADL_BIT   11
0157 #define GR1553B_BC_STAT_BCSUP_BIT   31
0158
0159 #define GR1553B_BC_STAT_SCST        (0x3<<GR1553B_BC_STAT_SCST_BIT)
0160 #define GR1553B_BC_STAT_SCADL       (0x1f<<GR1553B_BC_STAT_SCADL_BIT)
0161 #define GR1553B_BC_STAT_ASST        (0x3<<GR1553B_BC_STAT_ASST_BIT)
0162 #define GR1553B_BC_STAT_ASADL       (0x1f<<GR1553B_BC_STAT_ASADL_BIT)
0163 #define GR1553B_BC_STAT_BCSUP       (1<<GR1553B_BC_STAT_BCSUP_BIT)
0164
0165 /*** BC Action Register ***/
0166 #define GR1553B_BC_ACT_SCSRT_BIT    0
0167 #define GR1553B_BC_ACT_SCSUS_BIT    1
0168 #define GR1553B_BC_ACT_SCSTP_BIT    2
0169 #define GR1553B_BC_ACT_SETT_BIT     3
0170 #define GR1553B_BC_ACT_CLRT_BIT     4
0171 #define GR1553B_BC_ACT_ASSRT_BIT    8
0172 #define GR1553B_BC_ACT_ASSTP_BIT    9
0173 #define GR1553B_BC_ACT_BCKEY_BIT    16
0174
0175 #define GR1553B_BC_ACT_SCSRT        (1<<GR1553B_BC_ACT_SCSRT_BIT)
0176 #define GR1553B_BC_ACT_SCSUS        (1<<GR1553B_BC_ACT_SCSUS_BIT)
0177 #define GR1553B_BC_ACT_SCSTP        (1<<GR1553B_BC_ACT_SCSTP_BIT)
0178 #define GR1553B_BC_ACT_SETT     (1<<GR1553B_BC_ACT_SETT_BIT)
0179 #define GR1553B_BC_ACT_CLRT     (1<<GR1553B_BC_ACT_CLRT_BIT)
0180 #define GR1553B_BC_ACT_ASSRT        (1<<GR1553B_BC_ACT_ASSRT_BIT)
0181 #define GR1553B_BC_ACT_ASSTP        (1<<GR1553B_BC_ACT_ASSTP_BIT)
0182 #define GR1553B_BC_ACT_BCKEY        (0xffff<<GR1553B_BC_ACT_BCKEY_BIT)
0183
0184 /*** BC Timer Register ***/
0185 #define GR1553B_BC_TIMER_SCTM_BIT   0
0186
0187 #define GR1553B_BC_TIMER_SCTM       (0xffffff<<GR1553B_BC_TIMER_SCTM_BIT)
0188
0189 /*** BC Wake-up control Register ***/
0190 #define GR1553B_BC_WAKE_TIME_BIT    0
0191 #define GR1553B_BC_WAKE_WKEN_BIT    31
0192
0193 #define GR1553B_BC_WAKE_TIME        (0xffffff<<GR1553B_BC_WAKE_TIME_BIT)
0194 #define GR1553B_BC_WAKE_WKEN        (1<GR1553B_BC_WAKE_WKEN_BIT)
0195
0196 /*** RT status Register ***/
0197 #define GR1553B_RT_STAT_RUN_BIT     0
0198 #define GR1553B_RT_STAT_SHDB_BIT    1
0199 #define GR1553B_RT_STAT_SHDA_BIT    2
0200 #define GR1553B_RT_STAT_ACT_BIT     3
0201 #define GR1553B_RT_STAT_RTSUP_BIT   31
0202
0203 #define GR1553B_RT_STAT_RUN     (1<<GR1553B_RT_STAT_RUN_BIT)
0204 #define GR1553B_RT_STAT_SHDB        (1<<GR1553B_RT_STAT_SHDB_BIT)
0205 #define GR1553B_RT_STAT_SHDA        (1<<GR1553B_RT_STAT_SHDA_BIT)
0206 #define GR1553B_RT_STAT_ACT     (1<<GR1553B_RT_STAT_ACT_BIT)
0207 #define GR1553B_RT_STAT_RTSUP       (1<<GR1553B_RT_STAT_RTSUP_BIT)
0208
0209
0210 /*** RT Config Register ***/
0211 #define GR1553B_RT_CFG_RTEN_BIT     0
0212 #define GR1553B_RT_CFG_RTADDR_BIT   1
0213 #define GR1553B_RT_CFG_RTKEY_BIT    16
0214
0215 #define GR1553B_RT_CFG_RTEN     (1<<GR1553B_RT_CFG_RTEN_BIT)
0216 #define GR1553B_RT_CFG_RTADDR       (1<<GR1553B_RT_CFG_RTADDR_BIT)
0217 #define GR1553B_RT_CFG_RTKEY        (0xffff<<GR1553B_RT_CFG_RTKEY_BIT)
0218
0219 /*** RT Bus Status Register ***/
0220 #define GR1553B_RT_STAT2_TFLG_BIT   0
0221 #define GR1553B_RT_STAT2_DBCA_BIT   1
0222 #define GR1553B_RT_STAT2_SSF_BIT    2
0223 #define GR1553B_RT_STAT2_BUSY_BIT   3
0224 #define GR1553B_RT_STAT2_SREQ_BIT   4
0225 #define GR1553B_RT_STAT2_TFDE_BIT   8
0226
0227 #define GR1553B_RT_STAT2_TFLG       (1<<GR1553B_RT_STAT2_TFLG_BIT)
0228 #define GR1553B_RT_STAT2_DBCA       (1<<GR1553B_RT_STAT2_DBCA_BIT)
0229 #define GR1553B_RT_STAT2_SSF        (1<<GR1553B_RT_STAT2_SSF_BIT)
0230 #define GR1553B_RT_STAT2_BUSY       (1<<GR1553B_RT_STAT2_BUSY_BIT)
0231 #define GR1553B_RT_STAT2_SREQ       (1<<GR1553B_RT_STAT2_SREQ_BIT)
0232 #define GR1553B_RT_STAT2_TFDE       (1<<GR1553B_RT_STAT2_TFDE_BIT)
0233
0234 /*** RT Status Words Register ***/
0235 #define GR1553B_RT_STATW_VECW_BIT   0
0236 #define GR1553B_RT_STATW_BITW_BIT   16
0237
0238 #define GR1553B_RT_STATW_VECW       (0xffff<<GR1553B_RT_STATW_VECW_BIT)
0239 #define GR1553B_RT_STATW_BITW       (0xffff<<GR1553B_RT_STATW_BITW_BIT)
0240
0241 /*** RT Sync Register ***/
0242 #define GR1553B_RT_SYNC_SYD_BIT     0
0243 #define GR1553B_RT_SYNC_SYTM_BIT    16
0244
0245 #define GR1553B_RT_SYNC_SYD     (0xffff<<GR1553B_RT_SYNC_SYD_BIT)
0246 #define GR1553B_RT_SYNC_SYTM        (0xffff<<GR1553B_RT_SYNC_SYTM_BIT)
0247
0248 /*** RT Sub adress table Register ***/
0249 #define GR1553B_RT_TAB_SATB_BIT     0
0250
0251 #define GR1553B_RT_TAB_SATB     (0xffff<<GR1553B_RT_TAB_SATB_BIT)
0252
0253 /*** RT Mode code control Register ***/
0254 #define GR1553B_RT_MCCTRL_S_BIT     0
0255 #define GR1553B_RT_MCCTRL_SB_BIT    2
0256 #define GR1553B_RT_MCCTRL_SD_BIT    4
0257 #define GR1553B_RT_MCCTRL_SDB_BIT   6
0258 #define GR1553B_RT_MCCTRL_TS_BIT    8
0259 #define GR1553B_RT_MCCTRL_TSB_BIT   10
0260 #define GR1553B_RT_MCCTRL_TVW_BIT   12
0261 #define GR1553B_RT_MCCTRL_TBW_BIT   14
0262 #define GR1553B_RT_MCCTRL_DBC_BIT   16
0263 #define GR1553B_RT_MCCTRL_IST_BIT   18
0264 #define GR1553B_RT_MCCTRL_ISTB_BIT  20
0265 #define GR1553B_RT_MCCTRL_ITF_BIT   22
0266 #define GR1553B_RT_MCCTRL_ITFB_BIT  24
0267 #define GR1553B_RT_MCCTRL_RRT_BIT   26
0268 #define GR1553B_RT_MCCTRL_RRTB_BIT  28
0269
0270 #define GR1553B_RT_MCCTRL_S (1<<GR1553B_RT_MCCTRL_S_BIT)
0271 #define GR1553B_RT_MCCTRL_SB    (1<<GR1553B_RT_MCCTRL_SB_BIT)
0272 #define GR1553B_RT_MCCTRL_SD    (1<<GR1553B_RT_MCCTRL_SD_BIT)
0273 #define GR1553B_RT_MCCTRL_SDB   (1<<GR1553B_RT_MCCTRL_SDB_BIT)
0274 #define GR1553B_RT_MCCTRL_TS    (1<<GR1553B_RT_MCCTRL_TS_BIT)
0275 #define GR1553B_RT_MCCTRL_TSB   (1<<GR1553B_RT_MCCTRL_TSB_BIT)
0276 #define GR1553B_RT_MCCTRL_TVW   (1<<GR1553B_RT_MCCTRL_TVW_BIT)
0277 #define GR1553B_RT_MCCTRL_TBW   (1<<GR1553B_RT_MCCTRL_TBW_BIT)
0278 #define GR1553B_RT_MCCTRL_DBC   (1<<GR1553B_RT_MCCTRL_DBC_BIT)
0279 #define GR1553B_RT_MCCTRL_IST   (1<<GR1553B_RT_MCCTRL_IST_BIT)
0280 #define GR1553B_RT_MCCTRL_ISTB  (1<<GR1553B_RT_MCCTRL_ISTB_BIT)
0281 #define GR1553B_RT_MCCTRL_ITF   (1<<GR1553B_RT_MCCTRL_ITF_BIT)
0282 #define GR1553B_RT_MCCTRL_ITFB  (1<<GR1553B_RT_MCCTRL_ITFB_BIT)
0283 #define GR1553B_RT_MCCTRL_RRT   (1<<GR1553B_RT_MCCTRL_RRT_BIT)
0284 #define GR1553B_RT_MCCTRL_RRTB  (1<<GR1553B_RT_MCCTRL_RRTB_BIT)
0285
0286 /*** RT Time Tag control Register ***/
0287 #define GR1553B_RT_TTAG_TVAL_BIT    0
0288 #define GR1553B_RT_TTAG_TRES_BIT    16
0289
0290 #define GR1553B_RT_TTAG_TVAL        (0xffff<<GR1553B_RT_TTAG_TVAL_BIT)
0291 #define GR1553B_RT_TTAG_TRES        (0xffff<<GR1553B_RT_TTAG_TRES_BIT)
0292
0293 /*** BM Control Register ***/
0294 #define GR1553B_BM_STAT_BMSUP_BIT   31
0295
0296 #define GR1553B_BM_STAT_BMSUP       (1<<GR1553B_BM_STAT_BMSUP_BIT)
0297
0298 /*** BM Control Register ***/
0299 #define GR1553B_BM_CTRL_BMEN_BIT    0
0300 #define GR1553B_BM_CTRL_MANL_BIT    1
0301 #define GR1553B_BM_CTRL_UDWL_BIT    2
0302 #define GR1553B_BM_CTRL_IMCL_BIT    3
0303
0304 #define GR1553B_BM_CTRL_BMEN    (1<<GR1553B_BM_CTRL_BMEN_BIT)
0305 #define GR1553B_BM_CTRL_MANL    (1<<GR1553B_BM_CTRL_MANL_BIT)
0306 #define GR1553B_BM_CTRL_UDWL    (1<<GR1553B_BM_CTRL_UDWL_BIT)
0307 #define GR1553B_BM_CTRL_IMCL    (1<<GR1553B_BM_CTRL_IMCL_BIT)
0308
0309 /*** BM RT Mode code filter Register ***/
0310 #define GR1553B_BM_MC_S_BIT 0
0311 #define GR1553B_BM_MC_SB_BIT    1
0312 #define GR1553B_BM_MC_SD_BIT    2
0313 #define GR1553B_BM_MC_SDB_BIT   3
0314 #define GR1553B_BM_MC_TS_BIT    4
0315 #define GR1553B_BM_MC_TSB_BIT   5
0316 #define GR1553B_BM_MC_TVW_BIT   6
0317 #define GR1553B_BM_MC_TBW_BIT   7
0318 #define GR1553B_BM_MC_DBC_BIT   8
0319 #define GR1553B_BM_MC_IST_BIT   9
0320 #define GR1553B_BM_MC_ISTB_BIT  10
0321 #define GR1553B_BM_MC_ITF_BIT   11
0322 #define GR1553B_BM_MC_ITFB_BIT  12
0323 #define GR1553B_BM_MC_RRT_BIT   13
0324 #define GR1553B_BM_MC_RRTB_BIT  14
0325 #define GR1553B_BM_MC_TSW_BIT   15
0326 #define GR1553B_BM_MC_TLC_BIT   16
0327 #define GR1553B_BM_MC_STS_BIT   17
0328 #define GR1553B_BM_MC_STSB_BIT  18
0329
0330 #define GR1553B_BM_MC_S     (1<<GR1553B_BM_MC_S_BIT)
0331 #define GR1553B_BM_MC_SB    (1<<GR1553B_BM_MC_SB_BIT)
0332 #define GR1553B_BM_MC_SD    (1<<GR1553B_BM_MC_SD_BIT)
0333 #define GR1553B_BM_MC_SDB   (1<<GR1553B_BM_MC_SDB_BIT)
0334 #define GR1553B_BM_MC_TS    (1<<GR1553B_BM_MC_TS_BIT)
0335 #define GR1553B_BM_MC_TSB   (1<<GR1553B_BM_MC_TSB_BIT)
0336 #define GR1553B_BM_MC_TVW   (1<<GR1553B_BM_MC_TVW_BIT)
0337 #define GR1553B_BM_MC_TBW   (1<<GR1553B_BM_MC_TBW_BIT)
0338 #define GR1553B_BM_MC_DBC   (1<<GR1553B_BM_MC_DBC_BIT)
0339 #define GR1553B_BM_MC_IST   (1<<GR1553B_BM_MC_IST_BIT)
0340 #define GR1553B_BM_MC_ISTB  (1<<GR1553B_BM_MC_ISTB_BIT)
0341 #define GR1553B_BM_MC_ITF   (1<<GR1553B_BM_MC_ITF_BIT)
0342 #define GR1553B_BM_MC_ITFB  (1<<GR1553B_BM_MC_ITFB_BIT)
0343 #define GR1553B_BM_MC_RRT   (1<<GR1553B_BM_MC_RRT_BIT)
0344 #define GR1553B_BM_MC_RRTB  (1<<GR1553B_BM_MC_RRTB_BIT)
0345 #define GR1553B_BM_MC_TSW   (1<<GR1553B_BM_MC_TSW_BIT)
0346 #define GR1553B_BM_MC_TLC   (1<<GR1553B_BM_MC_TLC_BIT)
0347 #define GR1553B_BM_MC_STS   (1<<GR1553B_BM_MC_STS_BIT)
0348 #define GR1553B_BM_MC_STSB  (1<<GR1553B_BM_MC_STSB_BIT)
0349
0350 /*** BM RT Mode code filter Register ***/
0351 #define GR1553B_BM_TTAG_VAL_BIT 0
0352 #define GR1553B_BM_TTAG_RES_BIT 24
0353
0354 #define GR1553B_BM_TTAG_VAL     (0xffffff<<GR1553B_BM_TTAG_VAL_BIT)
0355 #define GR1553B_BM_TTAG_RES     (0xff<<GR1553B_BM_TTAG_RES_BIT)
0356
0357 /* Register GR1553B driver */
0358 extern void gr1553_register(void);
0359
0360 /*** BC Device allocation ***/
0361 /* Allocate a BC device. Minor is assigned to a device in the order
0362  * they are registered to the driver.
0363  */
0364 extern struct drvmgr_dev **gr1553_bc_open(int minor);
0365 /* Free a BC device previously allocated */
0366 extern void gr1553_bc_close(struct drvmgr_dev **dev);
0367
0368 /*** RT Device allocation ***/
0369 /* Allocate a BC device. Minor is assigned to a device in the order
0370  * they are registered to the driver.
0371  */
0372 extern struct drvmgr_dev **gr1553_rt_open(int minor);
0373 /* Free a BC device previously allocated */
0374 extern void gr1553_rt_close(struct drvmgr_dev **dev);
0375
0376 /*** BM Device allocation ***/
0377 /* Allocate a BC device. Minor is assigned to a device in the order
0378  * they are registered to the driver.
0379  */
0380 extern struct drvmgr_dev **gr1553_bm_open(int minor);
0381 /* Free a BC device previously allocated */
0382 extern void gr1553_bm_close(struct drvmgr_dev **dev);
0383
0384 #ifdef __cplusplus
0385 }
0386 #endif
0387
0388 #endif /* __GR1553B_H__ */