include/grlib/gr1553b-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGR1553B
0007  *
0008  * @brief This header file defines the GR1553B register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/gr1553b-header */
0054
0055 #ifndef _GRLIB_GR1553B_REGS_H
0056 #define _GRLIB_GR1553B_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/gr1553b */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGR1553B GR1553B
0068  *
0069  * @ingroup RTEMSDeviceGRLIB
0070  *
0071  * @brief This group contains the GR1553B interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGR1553BIRQ GR1553B IRQ Register (IRQ)
0078  *
0079  * @brief This group contains register bit definitions.
0080  *
0081  * @{
0082  */
0083
0084 #define GR1553B_IRQ_BMTOF 0x20000U
0085
0086 #define GR1553B_IRQ_BMD 0x10000U
0087
0088 #define GR1553B_IRQ_RTTE 0x400U
0089
0090 #define GR1553B_IRQ_RTD 0x200U
0091
0092 #define GR1553B_IRQ_RTEV 0x100U
0093
0094 #define GR1553B_IRQ_BCWK 0x4U
0095
0096 #define GR1553B_IRQ_BCD 0x2U
0097
0098 #define GR1553B_IRQ_BCEV 0x1U
0099
0100 /** @} */
0101
0102 /**
0103  * @defgroup RTEMSDeviceGR1553BIRQE GR1553B IRQ Enable Register (IRQE)
0104  *
0105  * @brief This group contains register bit definitions.
0106  *
0107  * @{
0108  */
0109
0110 #define GR1553B_IRQE_BMTOE 0x20000U
0111
0112 #define GR1553B_IRQE_BMDE 0x10000U
0113
0114 #define GR1553B_IRQE_RTTEE 0x400U
0115
0116 #define GR1553B_IRQE_RTDE 0x200U
0117
0118 #define GR1553B_IRQE_RTEVE 0x100U
0119
0120 #define GR1553B_IRQE_BCWKE 0x4U
0121
0122 #define GR1553B_IRQE_BCDE 0x2U
0123
0124 #define GR1553B_IRQE_BCEVE 0x1U
0125
0126 /** @} */
0127
0128 /**
0129  * @defgroup RTEMSDeviceGR1553BHC GR1553B Hardware Configuration Register (HC)
0130  *
0131  * @brief This group contains register bit definitions.
0132  *
0133  * @{
0134  */
0135
0136 #define GR1553B_HC_MOD 0x80000000U
0137
0138 #define GR1553B_HC_CVER 0x1000U
0139
0140 #define GR1553B_HC_XKEYS 0x800U
0141
0142 #define GR1553B_HC_ENDIAN_SHIFT 9
0143 #define GR1553B_HC_ENDIAN_MASK 0x600U
0144 #define GR1553B_HC_ENDIAN_GET( _reg ) \
0145   ( ( ( _reg ) & GR1553B_HC_ENDIAN_MASK ) >> \
0146     GR1553B_HC_ENDIAN_SHIFT )
0147 #define GR1553B_HC_ENDIAN_SET( _reg, _val ) \
0148   ( ( ( _reg ) & ~GR1553B_HC_ENDIAN_MASK ) | \
0149     ( ( ( _val ) << GR1553B_HC_ENDIAN_SHIFT ) & \
0150       GR1553B_HC_ENDIAN_MASK ) )
0151 #define GR1553B_HC_ENDIAN( _val ) \
0152   ( ( ( _val ) << GR1553B_HC_ENDIAN_SHIFT ) & \
0153     GR1553B_HC_ENDIAN_MASK )
0154
0155 #define GR1553B_HC_SCLK 0x100U
0156
0157 #define GR1553B_HC_CCFREQ_SHIFT 0
0158 #define GR1553B_HC_CCFREQ_MASK 0xffU
0159 #define GR1553B_HC_CCFREQ_GET( _reg ) \
0160   ( ( ( _reg ) & GR1553B_HC_CCFREQ_MASK ) >> \
0161     GR1553B_HC_CCFREQ_SHIFT )
0162 #define GR1553B_HC_CCFREQ_SET( _reg, _val ) \
0163   ( ( ( _reg ) & ~GR1553B_HC_CCFREQ_MASK ) | \
0164     ( ( ( _val ) << GR1553B_HC_CCFREQ_SHIFT ) & \
0165       GR1553B_HC_CCFREQ_MASK ) )
0166 #define GR1553B_HC_CCFREQ( _val ) \
0167   ( ( ( _val ) << GR1553B_HC_CCFREQ_SHIFT ) & \
0168     GR1553B_HC_CCFREQ_MASK )
0169
0170 /** @} */
0171
0172 /**
0173  * @defgroup RTEMSDeviceGR1553BBCSC \
0174  *   GR1553B BC Status and Config Register (BCSC)
0175  *
0176  * @brief This group contains register bit definitions.
0177  *
0178  * @{
0179  */
0180
0181 #define GR1553B_BCSC_BCSUP 0x80000000U
0182
0183 #define GR1553B_BCSC_BCFEAT_SHIFT 28
0184 #define GR1553B_BCSC_BCFEAT_MASK 0x70000000U
0185 #define GR1553B_BCSC_BCFEAT_GET( _reg ) \
0186   ( ( ( _reg ) & GR1553B_BCSC_BCFEAT_MASK ) >> \
0187     GR1553B_BCSC_BCFEAT_SHIFT )
0188 #define GR1553B_BCSC_BCFEAT_SET( _reg, _val ) \
0189   ( ( ( _reg ) & ~GR1553B_BCSC_BCFEAT_MASK ) | \
0190     ( ( ( _val ) << GR1553B_BCSC_BCFEAT_SHIFT ) & \
0191       GR1553B_BCSC_BCFEAT_MASK ) )
0192 #define GR1553B_BCSC_BCFEAT( _val ) \
0193   ( ( ( _val ) << GR1553B_BCSC_BCFEAT_SHIFT ) & \
0194     GR1553B_BCSC_BCFEAT_MASK )
0195
0196 #define GR1553B_BCSC_BCCHK 0x10000U
0197
0198 #define GR1553B_BCSC_ASADL_SHIFT 11
0199 #define GR1553B_BCSC_ASADL_MASK 0xf800U
0200 #define GR1553B_BCSC_ASADL_GET( _reg ) \
0201   ( ( ( _reg ) & GR1553B_BCSC_ASADL_MASK ) >> \
0202     GR1553B_BCSC_ASADL_SHIFT )
0203 #define GR1553B_BCSC_ASADL_SET( _reg, _val ) \
0204   ( ( ( _reg ) & ~GR1553B_BCSC_ASADL_MASK ) | \
0205     ( ( ( _val ) << GR1553B_BCSC_ASADL_SHIFT ) & \
0206       GR1553B_BCSC_ASADL_MASK ) )
0207 #define GR1553B_BCSC_ASADL( _val ) \
0208   ( ( ( _val ) << GR1553B_BCSC_ASADL_SHIFT ) & \
0209     GR1553B_BCSC_ASADL_MASK )
0210
0211 #define GR1553B_BCSC_ASST_SHIFT 8
0212 #define GR1553B_BCSC_ASST_MASK 0x300U
0213 #define GR1553B_BCSC_ASST_GET( _reg ) \
0214   ( ( ( _reg ) & GR1553B_BCSC_ASST_MASK ) >> \
0215     GR1553B_BCSC_ASST_SHIFT )
0216 #define GR1553B_BCSC_ASST_SET( _reg, _val ) \
0217   ( ( ( _reg ) & ~GR1553B_BCSC_ASST_MASK ) | \
0218     ( ( ( _val ) << GR1553B_BCSC_ASST_SHIFT ) & \
0219       GR1553B_BCSC_ASST_MASK ) )
0220 #define GR1553B_BCSC_ASST( _val ) \
0221   ( ( ( _val ) << GR1553B_BCSC_ASST_SHIFT ) & \
0222     GR1553B_BCSC_ASST_MASK )
0223
0224 #define GR1553B_BCSC_SCADL_SHIFT 3
0225 #define GR1553B_BCSC_SCADL_MASK 0xf8U
0226 #define GR1553B_BCSC_SCADL_GET( _reg ) \
0227   ( ( ( _reg ) & GR1553B_BCSC_SCADL_MASK ) >> \
0228     GR1553B_BCSC_SCADL_SHIFT )
0229 #define GR1553B_BCSC_SCADL_SET( _reg, _val ) \
0230   ( ( ( _reg ) & ~GR1553B_BCSC_SCADL_MASK ) | \
0231     ( ( ( _val ) << GR1553B_BCSC_SCADL_SHIFT ) & \
0232       GR1553B_BCSC_SCADL_MASK ) )
0233 #define GR1553B_BCSC_SCADL( _val ) \
0234   ( ( ( _val ) << GR1553B_BCSC_SCADL_SHIFT ) & \
0235     GR1553B_BCSC_SCADL_MASK )
0236
0237 #define GR1553B_BCSC_SCST_SHIFT 0
0238 #define GR1553B_BCSC_SCST_MASK 0x7U
0239 #define GR1553B_BCSC_SCST_GET( _reg ) \
0240   ( ( ( _reg ) & GR1553B_BCSC_SCST_MASK ) >> \
0241     GR1553B_BCSC_SCST_SHIFT )
0242 #define GR1553B_BCSC_SCST_SET( _reg, _val ) \
0243   ( ( ( _reg ) & ~GR1553B_BCSC_SCST_MASK ) | \
0244     ( ( ( _val ) << GR1553B_BCSC_SCST_SHIFT ) & \
0245       GR1553B_BCSC_SCST_MASK ) )
0246 #define GR1553B_BCSC_SCST( _val ) \
0247   ( ( ( _val ) << GR1553B_BCSC_SCST_SHIFT ) & \
0248     GR1553B_BCSC_SCST_MASK )
0249
0250 /** @} */
0251
0252 /**
0253  * @defgroup RTEMSDeviceGR1553BBCA GR1553B BC Action Register (BCA)
0254  *
0255  * @brief This group contains register bit definitions.
0256  *
0257  * @{
0258  */
0259
0260 #define GR1553B_BCA_BCKEY_SHIFT 16
0261 #define GR1553B_BCA_BCKEY_MASK 0xffff0000U
0262 #define GR1553B_BCA_BCKEY_GET( _reg ) \
0263   ( ( ( _reg ) & GR1553B_BCA_BCKEY_MASK ) >> \
0264     GR1553B_BCA_BCKEY_SHIFT )
0265 #define GR1553B_BCA_BCKEY_SET( _reg, _val ) \
0266   ( ( ( _reg ) & ~GR1553B_BCA_BCKEY_MASK ) | \
0267     ( ( ( _val ) << GR1553B_BCA_BCKEY_SHIFT ) & \
0268       GR1553B_BCA_BCKEY_MASK ) )
0269 #define GR1553B_BCA_BCKEY( _val ) \
0270   ( ( ( _val ) << GR1553B_BCA_BCKEY_SHIFT ) & \
0271     GR1553B_BCA_BCKEY_MASK )
0272
0273 #define GR1553B_BCA_ASSTP 0x200U
0274
0275 #define GR1553B_BCA_ASSRT 0x100U
0276
0277 #define GR1553B_BCA_CLRT 0x10U
0278
0279 #define GR1553B_BCA_SETT 0x8U
0280
0281 #define GR1553B_BCA_SCSTP 0x4U
0282
0283 #define GR1553B_BCA_SCSUS 0x2U
0284
0285 #define GR1553B_BCA_SCSRT 0x1U
0286
0287 /** @} */
0288
0289 /**
0290  * @defgroup RTEMSDeviceGR1553BBCTNP \
0291  *   GR1553B BC Transfer list next pointer register (BCTNP)
0292  *
0293  * @brief This group contains register bit definitions.
0294  *
0295  * @{
0296  */
0297
0298 #define GR1553B_BCTNP_POINTER_SHIFT 0
0299 #define GR1553B_BCTNP_POINTER_MASK 0xffffffffU
0300 #define GR1553B_BCTNP_POINTER_GET( _reg ) \
0301   ( ( ( _reg ) & GR1553B_BCTNP_POINTER_MASK ) >> \
0302     GR1553B_BCTNP_POINTER_SHIFT )
0303 #define GR1553B_BCTNP_POINTER_SET( _reg, _val ) \
0304   ( ( ( _reg ) & ~GR1553B_BCTNP_POINTER_MASK ) | \
0305     ( ( ( _val ) << GR1553B_BCTNP_POINTER_SHIFT ) & \
0306       GR1553B_BCTNP_POINTER_MASK ) )
0307 #define GR1553B_BCTNP_POINTER( _val ) \
0308   ( ( ( _val ) << GR1553B_BCTNP_POINTER_SHIFT ) & \
0309     GR1553B_BCTNP_POINTER_MASK )
0310
0311 /** @} */
0312
0313 /**
0314  * @defgroup RTEMSDeviceGR1553BBCANP \
0315  *   GR1553B BC Asynchronous list next pointer register (BCANP)
0316  *
0317  * @brief This group contains register bit definitions.
0318  *
0319  * @{
0320  */
0321
0322 #define GR1553B_BCANP_POINTER_SHIFT 0
0323 #define GR1553B_BCANP_POINTER_MASK 0xffffffffU
0324 #define GR1553B_BCANP_POINTER_GET( _reg ) \
0325   ( ( ( _reg ) & GR1553B_BCANP_POINTER_MASK ) >> \
0326     GR1553B_BCANP_POINTER_SHIFT )
0327 #define GR1553B_BCANP_POINTER_SET( _reg, _val ) \
0328   ( ( ( _reg ) & ~GR1553B_BCANP_POINTER_MASK ) | \
0329     ( ( ( _val ) << GR1553B_BCANP_POINTER_SHIFT ) & \
0330       GR1553B_BCANP_POINTER_MASK ) )
0331 #define GR1553B_BCANP_POINTER( _val ) \
0332   ( ( ( _val ) << GR1553B_BCANP_POINTER_SHIFT ) & \
0333     GR1553B_BCANP_POINTER_MASK )
0334
0335 /** @} */
0336
0337 /**
0338  * @defgroup RTEMSDeviceGR1553BBCT GR1553B BC Timer register (BCT)
0339  *
0340  * @brief This group contains register bit definitions.
0341  *
0342  * @{
0343  */
0344
0345 #define GR1553B_BCT_SCTM_SHIFT 0
0346 #define GR1553B_BCT_SCTM_MASK 0xffffffU
0347 #define GR1553B_BCT_SCTM_GET( _reg ) \
0348   ( ( ( _reg ) & GR1553B_BCT_SCTM_MASK ) >> \
0349     GR1553B_BCT_SCTM_SHIFT )
0350 #define GR1553B_BCT_SCTM_SET( _reg, _val ) \
0351   ( ( ( _reg ) & ~GR1553B_BCT_SCTM_MASK ) | \
0352     ( ( ( _val ) << GR1553B_BCT_SCTM_SHIFT ) & \
0353       GR1553B_BCT_SCTM_MASK ) )
0354 #define GR1553B_BCT_SCTM( _val ) \
0355   ( ( ( _val ) << GR1553B_BCT_SCTM_SHIFT ) & \
0356     GR1553B_BCT_SCTM_MASK )
0357
0358 /** @} */
0359
0360 /**
0361  * @defgroup RTEMSDeviceGR1553BBCRP \
0362  *   GR1553B BC Transfer-triggered IRQ ring position register (BCRP)
0363  *
0364  * @brief This group contains register bit definitions.
0365  *
0366  * @{
0367  */
0368
0369 #define GR1553B_BCRP_POSITION_SHIFT 0
0370 #define GR1553B_BCRP_POSITION_MASK 0xffffffffU
0371 #define GR1553B_BCRP_POSITION_GET( _reg ) \
0372   ( ( ( _reg ) & GR1553B_BCRP_POSITION_MASK ) >> \
0373     GR1553B_BCRP_POSITION_SHIFT )
0374 #define GR1553B_BCRP_POSITION_SET( _reg, _val ) \
0375   ( ( ( _reg ) & ~GR1553B_BCRP_POSITION_MASK ) | \
0376     ( ( ( _val ) << GR1553B_BCRP_POSITION_SHIFT ) & \
0377       GR1553B_BCRP_POSITION_MASK ) )
0378 #define GR1553B_BCRP_POSITION( _val ) \
0379   ( ( ( _val ) << GR1553B_BCRP_POSITION_SHIFT ) & \
0380     GR1553B_BCRP_POSITION_MASK )
0381
0382 /** @} */
0383
0384 /**
0385  * @defgroup RTEMSDeviceGR1553BBCBS GR1553B BC per-RT Bus swap register (BCBS)
0386  *
0387  * @brief This group contains register bit definitions.
0388  *
0389  * @{
0390  */
0391
0392 #define GR1553B_BCBS_SWAP_SHIFT 0
0393 #define GR1553B_BCBS_SWAP_MASK 0xffffffffU
0394 #define GR1553B_BCBS_SWAP_GET( _reg ) \
0395   ( ( ( _reg ) & GR1553B_BCBS_SWAP_MASK ) >> \
0396     GR1553B_BCBS_SWAP_SHIFT )
0397 #define GR1553B_BCBS_SWAP_SET( _reg, _val ) \
0398   ( ( ( _reg ) & ~GR1553B_BCBS_SWAP_MASK ) | \
0399     ( ( ( _val ) << GR1553B_BCBS_SWAP_SHIFT ) & \
0400       GR1553B_BCBS_SWAP_MASK ) )
0401 #define GR1553B_BCBS_SWAP( _val ) \
0402   ( ( ( _val ) << GR1553B_BCBS_SWAP_SHIFT ) & \
0403     GR1553B_BCBS_SWAP_MASK )
0404
0405 /** @} */
0406
0407 /**
0408  * @defgroup RTEMSDeviceGR1553BBCTCP \
0409  *   GR1553B BC Transfer list current slot pointer (BCTCP)
0410  *
0411  * @brief This group contains register bit definitions.
0412  *
0413  * @{
0414  */
0415
0416 #define GR1553B_BCTCP_POINTER_SHIFT 0
0417 #define GR1553B_BCTCP_POINTER_MASK 0xffffffffU
0418 #define GR1553B_BCTCP_POINTER_GET( _reg ) \
0419   ( ( ( _reg ) & GR1553B_BCTCP_POINTER_MASK ) >> \
0420     GR1553B_BCTCP_POINTER_SHIFT )
0421 #define GR1553B_BCTCP_POINTER_SET( _reg, _val ) \
0422   ( ( ( _reg ) & ~GR1553B_BCTCP_POINTER_MASK ) | \
0423     ( ( ( _val ) << GR1553B_BCTCP_POINTER_SHIFT ) & \
0424       GR1553B_BCTCP_POINTER_MASK ) )
0425 #define GR1553B_BCTCP_POINTER( _val ) \
0426   ( ( ( _val ) << GR1553B_BCTCP_POINTER_SHIFT ) & \
0427     GR1553B_BCTCP_POINTER_MASK )
0428
0429 /** @} */
0430
0431 /**
0432  * @defgroup RTEMSDeviceGR1553BBCACP \
0433  *   GR1553B BC Asynchronous list current slot pointer (BCACP)
0434  *
0435  * @brief This group contains register bit definitions.
0436  *
0437  * @{
0438  */
0439
0440 #define GR1553B_BCACP_POINTER_SHIFT 0
0441 #define GR1553B_BCACP_POINTER_MASK 0xffffffffU
0442 #define GR1553B_BCACP_POINTER_GET( _reg ) \
0443   ( ( ( _reg ) & GR1553B_BCACP_POINTER_MASK ) >> \
0444     GR1553B_BCACP_POINTER_SHIFT )
0445 #define GR1553B_BCACP_POINTER_SET( _reg, _val ) \
0446   ( ( ( _reg ) & ~GR1553B_BCACP_POINTER_MASK ) | \
0447     ( ( ( _val ) << GR1553B_BCACP_POINTER_SHIFT ) & \
0448       GR1553B_BCACP_POINTER_MASK ) )
0449 #define GR1553B_BCACP_POINTER( _val ) \
0450   ( ( ( _val ) << GR1553B_BCACP_POINTER_SHIFT ) & \
0451     GR1553B_BCACP_POINTER_MASK )
0452
0453 /** @} */
0454
0455 /**
0456  * @defgroup RTEMSDeviceGR1553BRTS GR1553B RT Status register (RTS)
0457  *
0458  * @brief This group contains register bit definitions.
0459  *
0460  * @{
0461  */
0462
0463 #define GR1553B_RTS_RTSUP 0x80000000U
0464
0465 #define GR1553B_RTS_ACT 0x8U
0466
0467 #define GR1553B_RTS_SHDA 0x4U
0468
0469 #define GR1553B_RTS_SHDB 0x2U
0470
0471 #define GR1553B_RTS_RUN 0x1U
0472
0473 /** @} */
0474
0475 /**
0476  * @defgroup RTEMSDeviceGR1553BRTC GR1553B RT Config register (RTC)
0477  *
0478  * @brief This group contains register bit definitions.
0479  *
0480  * @{
0481  */
0482
0483 #define GR1553B_RTC_RTKEY_SHIFT 16
0484 #define GR1553B_RTC_RTKEY_MASK 0xffff0000U
0485 #define GR1553B_RTC_RTKEY_GET( _reg ) \
0486   ( ( ( _reg ) & GR1553B_RTC_RTKEY_MASK ) >> \
0487     GR1553B_RTC_RTKEY_SHIFT )
0488 #define GR1553B_RTC_RTKEY_SET( _reg, _val ) \
0489   ( ( ( _reg ) & ~GR1553B_RTC_RTKEY_MASK ) | \
0490     ( ( ( _val ) << GR1553B_RTC_RTKEY_SHIFT ) & \
0491       GR1553B_RTC_RTKEY_MASK ) )
0492 #define GR1553B_RTC_RTKEY( _val ) \
0493   ( ( ( _val ) << GR1553B_RTC_RTKEY_SHIFT ) & \
0494     GR1553B_RTC_RTKEY_MASK )
0495
0496 #define GR1553B_RTC_SYS 0x8000U
0497
0498 #define GR1553B_RTC_SYDS 0x4000U
0499
0500 #define GR1553B_RTC_BRS 0x2000U
0501
0502 #define GR1553B_RTC_RTEIS 0x40U
0503
0504 #define GR1553B_RTC_RTADDR_SHIFT 1
0505 #define GR1553B_RTC_RTADDR_MASK 0x3eU
0506 #define GR1553B_RTC_RTADDR_GET( _reg ) \
0507   ( ( ( _reg ) & GR1553B_RTC_RTADDR_MASK ) >> \
0508     GR1553B_RTC_RTADDR_SHIFT )
0509 #define GR1553B_RTC_RTADDR_SET( _reg, _val ) \
0510   ( ( ( _reg ) & ~GR1553B_RTC_RTADDR_MASK ) | \
0511     ( ( ( _val ) << GR1553B_RTC_RTADDR_SHIFT ) & \
0512       GR1553B_RTC_RTADDR_MASK ) )
0513 #define GR1553B_RTC_RTADDR( _val ) \
0514   ( ( ( _val ) << GR1553B_RTC_RTADDR_SHIFT ) & \
0515     GR1553B_RTC_RTADDR_MASK )
0516
0517 #define GR1553B_RTC_RTEN 0x1U
0518
0519 /** @} */
0520
0521 /**
0522  * @defgroup RTEMSDeviceGR1553BRTBS GR1553B RT Bus status register (RTBS)
0523  *
0524  * @brief This group contains register bit definitions.
0525  *
0526  * @{
0527  */
0528
0529 #define GR1553B_RTBS_TFDE 0x100U
0530
0531 #define GR1553B_RTBS_SREQ 0x10U
0532
0533 #define GR1553B_RTBS_BUSY 0x8U
0534
0535 #define GR1553B_RTBS_SSF 0x4U
0536
0537 #define GR1553B_RTBS_DBCA 0x2U
0538
0539 #define GR1553B_RTBS_TFLG 0x1U
0540
0541 /** @} */
0542
0543 /**
0544  * @defgroup RTEMSDeviceGR1553BRTSW GR1553B RT Status words register (RTSW)
0545  *
0546  * @brief This group contains register bit definitions.
0547  *
0548  * @{
0549  */
0550
0551 #define GR1553B_RTSW_BITW_SHIFT 16
0552 #define GR1553B_RTSW_BITW_MASK 0xffff0000U
0553 #define GR1553B_RTSW_BITW_GET( _reg ) \
0554   ( ( ( _reg ) & GR1553B_RTSW_BITW_MASK ) >> \
0555     GR1553B_RTSW_BITW_SHIFT )
0556 #define GR1553B_RTSW_BITW_SET( _reg, _val ) \
0557   ( ( ( _reg ) & ~GR1553B_RTSW_BITW_MASK ) | \
0558     ( ( ( _val ) << GR1553B_RTSW_BITW_SHIFT ) & \
0559       GR1553B_RTSW_BITW_MASK ) )
0560 #define GR1553B_RTSW_BITW( _val ) \
0561   ( ( ( _val ) << GR1553B_RTSW_BITW_SHIFT ) & \
0562     GR1553B_RTSW_BITW_MASK )
0563
0564 #define GR1553B_RTSW_VECW_SHIFT 0
0565 #define GR1553B_RTSW_VECW_MASK 0xffffU
0566 #define GR1553B_RTSW_VECW_GET( _reg ) \
0567   ( ( ( _reg ) & GR1553B_RTSW_VECW_MASK ) >> \
0568     GR1553B_RTSW_VECW_SHIFT )
0569 #define GR1553B_RTSW_VECW_SET( _reg, _val ) \
0570   ( ( ( _reg ) & ~GR1553B_RTSW_VECW_MASK ) | \
0571     ( ( ( _val ) << GR1553B_RTSW_VECW_SHIFT ) & \
0572       GR1553B_RTSW_VECW_MASK ) )
0573 #define GR1553B_RTSW_VECW( _val ) \
0574   ( ( ( _val ) << GR1553B_RTSW_VECW_SHIFT ) & \
0575     GR1553B_RTSW_VECW_MASK )
0576
0577 /** @} */
0578
0579 /**
0580  * @defgroup RTEMSDeviceGR1553BRTSY GR1553B RT Sync register (RTSY)
0581  *
0582  * @brief This group contains register bit definitions.
0583  *
0584  * @{
0585  */
0586
0587 #define GR1553B_RTSY_SYTM_SHIFT 16
0588 #define GR1553B_RTSY_SYTM_MASK 0xffff0000U
0589 #define GR1553B_RTSY_SYTM_GET( _reg ) \
0590   ( ( ( _reg ) & GR1553B_RTSY_SYTM_MASK ) >> \
0591     GR1553B_RTSY_SYTM_SHIFT )
0592 #define GR1553B_RTSY_SYTM_SET( _reg, _val ) \
0593   ( ( ( _reg ) & ~GR1553B_RTSY_SYTM_MASK ) | \
0594     ( ( ( _val ) << GR1553B_RTSY_SYTM_SHIFT ) & \
0595       GR1553B_RTSY_SYTM_MASK ) )
0596 #define GR1553B_RTSY_SYTM( _val ) \
0597   ( ( ( _val ) << GR1553B_RTSY_SYTM_SHIFT ) & \
0598     GR1553B_RTSY_SYTM_MASK )
0599
0600 #define GR1553B_RTSY_SYD_SHIFT 0
0601 #define GR1553B_RTSY_SYD_MASK 0xffffU
0602 #define GR1553B_RTSY_SYD_GET( _reg ) \
0603   ( ( ( _reg ) & GR1553B_RTSY_SYD_MASK ) >> \
0604     GR1553B_RTSY_SYD_SHIFT )
0605 #define GR1553B_RTSY_SYD_SET( _reg, _val ) \
0606   ( ( ( _reg ) & ~GR1553B_RTSY_SYD_MASK ) | \
0607     ( ( ( _val ) << GR1553B_RTSY_SYD_SHIFT ) & \
0608       GR1553B_RTSY_SYD_MASK ) )
0609 #define GR1553B_RTSY_SYD( _val ) \
0610   ( ( ( _val ) << GR1553B_RTSY_SYD_SHIFT ) & \
0611     GR1553B_RTSY_SYD_MASK )
0612
0613 /** @} */
0614
0615 /**
0616  * @defgroup RTEMSDeviceGR1553BRTSTBA \
0617  *   GR1553B RT Subaddress table base address register (RTSTBA)
0618  *
0619  * @brief This group contains register bit definitions.
0620  *
0621  * @{
0622  */
0623
0624 #define GR1553B_RTSTBA_SATB_SHIFT 9
0625 #define GR1553B_RTSTBA_SATB_MASK 0xfffffe00U
0626 #define GR1553B_RTSTBA_SATB_GET( _reg ) \
0627   ( ( ( _reg ) & GR1553B_RTSTBA_SATB_MASK ) >> \
0628     GR1553B_RTSTBA_SATB_SHIFT )
0629 #define GR1553B_RTSTBA_SATB_SET( _reg, _val ) \
0630   ( ( ( _reg ) & ~GR1553B_RTSTBA_SATB_MASK ) | \
0631     ( ( ( _val ) << GR1553B_RTSTBA_SATB_SHIFT ) & \
0632       GR1553B_RTSTBA_SATB_MASK ) )
0633 #define GR1553B_RTSTBA_SATB( _val ) \
0634   ( ( ( _val ) << GR1553B_RTSTBA_SATB_SHIFT ) & \
0635     GR1553B_RTSTBA_SATB_MASK )
0636
0637 /** @} */
0638
0639 /**
0640  * @defgroup RTEMSDeviceGR1553BRTMCC \
0641  *   GR1553B RT Mode code control register (RTMCC)
0642  *
0643  * @brief This group contains register bit definitions.
0644  *
0645  * @{
0646  */
0647
0648 #define GR1553B_RTMCC_RRTB_SHIFT 28
0649 #define GR1553B_RTMCC_RRTB_MASK 0x30000000U
0650 #define GR1553B_RTMCC_RRTB_GET( _reg ) \
0651   ( ( ( _reg ) & GR1553B_RTMCC_RRTB_MASK ) >> \
0652     GR1553B_RTMCC_RRTB_SHIFT )
0653 #define GR1553B_RTMCC_RRTB_SET( _reg, _val ) \
0654   ( ( ( _reg ) & ~GR1553B_RTMCC_RRTB_MASK ) | \
0655     ( ( ( _val ) << GR1553B_RTMCC_RRTB_SHIFT ) & \
0656       GR1553B_RTMCC_RRTB_MASK ) )
0657 #define GR1553B_RTMCC_RRTB( _val ) \
0658   ( ( ( _val ) << GR1553B_RTMCC_RRTB_SHIFT ) & \
0659     GR1553B_RTMCC_RRTB_MASK )
0660
0661 #define GR1553B_RTMCC_RRT_SHIFT 26
0662 #define GR1553B_RTMCC_RRT_MASK 0xc000000U
0663 #define GR1553B_RTMCC_RRT_GET( _reg ) \
0664   ( ( ( _reg ) & GR1553B_RTMCC_RRT_MASK ) >> \
0665     GR1553B_RTMCC_RRT_SHIFT )
0666 #define GR1553B_RTMCC_RRT_SET( _reg, _val ) \
0667   ( ( ( _reg ) & ~GR1553B_RTMCC_RRT_MASK ) | \
0668     ( ( ( _val ) << GR1553B_RTMCC_RRT_SHIFT ) & \
0669       GR1553B_RTMCC_RRT_MASK ) )
0670 #define GR1553B_RTMCC_RRT( _val ) \
0671   ( ( ( _val ) << GR1553B_RTMCC_RRT_SHIFT ) & \
0672     GR1553B_RTMCC_RRT_MASK )
0673
0674 #define GR1553B_RTMCC_ITFB_SHIFT 24
0675 #define GR1553B_RTMCC_ITFB_MASK 0x3000000U
0676 #define GR1553B_RTMCC_ITFB_GET( _reg ) \
0677   ( ( ( _reg ) & GR1553B_RTMCC_ITFB_MASK ) >> \
0678     GR1553B_RTMCC_ITFB_SHIFT )
0679 #define GR1553B_RTMCC_ITFB_SET( _reg, _val ) \
0680   ( ( ( _reg ) & ~GR1553B_RTMCC_ITFB_MASK ) | \
0681     ( ( ( _val ) << GR1553B_RTMCC_ITFB_SHIFT ) & \
0682       GR1553B_RTMCC_ITFB_MASK ) )
0683 #define GR1553B_RTMCC_ITFB( _val ) \
0684   ( ( ( _val ) << GR1553B_RTMCC_ITFB_SHIFT ) & \
0685     GR1553B_RTMCC_ITFB_MASK )
0686
0687 #define GR1553B_RTMCC_ITF_SHIFT 22
0688 #define GR1553B_RTMCC_ITF_MASK 0xc00000U
0689 #define GR1553B_RTMCC_ITF_GET( _reg ) \
0690   ( ( ( _reg ) & GR1553B_RTMCC_ITF_MASK ) >> \
0691     GR1553B_RTMCC_ITF_SHIFT )
0692 #define GR1553B_RTMCC_ITF_SET( _reg, _val ) \
0693   ( ( ( _reg ) & ~GR1553B_RTMCC_ITF_MASK ) | \
0694     ( ( ( _val ) << GR1553B_RTMCC_ITF_SHIFT ) & \
0695       GR1553B_RTMCC_ITF_MASK ) )
0696 #define GR1553B_RTMCC_ITF( _val ) \
0697   ( ( ( _val ) << GR1553B_RTMCC_ITF_SHIFT ) & \
0698     GR1553B_RTMCC_ITF_MASK )
0699
0700 #define GR1553B_RTMCC_ISTB_SHIFT 20
0701 #define GR1553B_RTMCC_ISTB_MASK 0x300000U
0702 #define GR1553B_RTMCC_ISTB_GET( _reg ) \
0703   ( ( ( _reg ) & GR1553B_RTMCC_ISTB_MASK ) >> \
0704     GR1553B_RTMCC_ISTB_SHIFT )
0705 #define GR1553B_RTMCC_ISTB_SET( _reg, _val ) \
0706   ( ( ( _reg ) & ~GR1553B_RTMCC_ISTB_MASK ) | \
0707     ( ( ( _val ) << GR1553B_RTMCC_ISTB_SHIFT ) & \
0708       GR1553B_RTMCC_ISTB_MASK ) )
0709 #define GR1553B_RTMCC_ISTB( _val ) \
0710   ( ( ( _val ) << GR1553B_RTMCC_ISTB_SHIFT ) & \
0711     GR1553B_RTMCC_ISTB_MASK )
0712
0713 #define GR1553B_RTMCC_IST_SHIFT 18
0714 #define GR1553B_RTMCC_IST_MASK 0xc0000U
0715 #define GR1553B_RTMCC_IST_GET( _reg ) \
0716   ( ( ( _reg ) & GR1553B_RTMCC_IST_MASK ) >> \
0717     GR1553B_RTMCC_IST_SHIFT )
0718 #define GR1553B_RTMCC_IST_SET( _reg, _val ) \
0719   ( ( ( _reg ) & ~GR1553B_RTMCC_IST_MASK ) | \
0720     ( ( ( _val ) << GR1553B_RTMCC_IST_SHIFT ) & \
0721       GR1553B_RTMCC_IST_MASK ) )
0722 #define GR1553B_RTMCC_IST( _val ) \
0723   ( ( ( _val ) << GR1553B_RTMCC_IST_SHIFT ) & \
0724     GR1553B_RTMCC_IST_MASK )
0725
0726 #define GR1553B_RTMCC_DBC_SHIFT 16
0727 #define GR1553B_RTMCC_DBC_MASK 0x30000U
0728 #define GR1553B_RTMCC_DBC_GET( _reg ) \
0729   ( ( ( _reg ) & GR1553B_RTMCC_DBC_MASK ) >> \
0730     GR1553B_RTMCC_DBC_SHIFT )
0731 #define GR1553B_RTMCC_DBC_SET( _reg, _val ) \
0732   ( ( ( _reg ) & ~GR1553B_RTMCC_DBC_MASK ) | \
0733     ( ( ( _val ) << GR1553B_RTMCC_DBC_SHIFT ) & \
0734       GR1553B_RTMCC_DBC_MASK ) )
0735 #define GR1553B_RTMCC_DBC( _val ) \
0736   ( ( ( _val ) << GR1553B_RTMCC_DBC_SHIFT ) & \
0737     GR1553B_RTMCC_DBC_MASK )
0738
0739 #define GR1553B_RTMCC_TBW_SHIFT 14
0740 #define GR1553B_RTMCC_TBW_MASK 0xc000U
0741 #define GR1553B_RTMCC_TBW_GET( _reg ) \
0742   ( ( ( _reg ) & GR1553B_RTMCC_TBW_MASK ) >> \
0743     GR1553B_RTMCC_TBW_SHIFT )
0744 #define GR1553B_RTMCC_TBW_SET( _reg, _val ) \
0745   ( ( ( _reg ) & ~GR1553B_RTMCC_TBW_MASK ) | \
0746     ( ( ( _val ) << GR1553B_RTMCC_TBW_SHIFT ) & \
0747       GR1553B_RTMCC_TBW_MASK ) )
0748 #define GR1553B_RTMCC_TBW( _val ) \
0749   ( ( ( _val ) << GR1553B_RTMCC_TBW_SHIFT ) & \
0750     GR1553B_RTMCC_TBW_MASK )
0751
0752 #define GR1553B_RTMCC_TVW_SHIFT 12
0753 #define GR1553B_RTMCC_TVW_MASK 0x3000U
0754 #define GR1553B_RTMCC_TVW_GET( _reg ) \
0755   ( ( ( _reg ) & GR1553B_RTMCC_TVW_MASK ) >> \
0756     GR1553B_RTMCC_TVW_SHIFT )
0757 #define GR1553B_RTMCC_TVW_SET( _reg, _val ) \
0758   ( ( ( _reg ) & ~GR1553B_RTMCC_TVW_MASK ) | \
0759     ( ( ( _val ) << GR1553B_RTMCC_TVW_SHIFT ) & \
0760       GR1553B_RTMCC_TVW_MASK ) )
0761 #define GR1553B_RTMCC_TVW( _val ) \
0762   ( ( ( _val ) << GR1553B_RTMCC_TVW_SHIFT ) & \
0763     GR1553B_RTMCC_TVW_MASK )
0764
0765 #define GR1553B_RTMCC_TSB_SHIFT 10
0766 #define GR1553B_RTMCC_TSB_MASK 0xc00U
0767 #define GR1553B_RTMCC_TSB_GET( _reg ) \
0768   ( ( ( _reg ) & GR1553B_RTMCC_TSB_MASK ) >> \
0769     GR1553B_RTMCC_TSB_SHIFT )
0770 #define GR1553B_RTMCC_TSB_SET( _reg, _val ) \
0771   ( ( ( _reg ) & ~GR1553B_RTMCC_TSB_MASK ) | \
0772     ( ( ( _val ) << GR1553B_RTMCC_TSB_SHIFT ) & \
0773       GR1553B_RTMCC_TSB_MASK ) )
0774 #define GR1553B_RTMCC_TSB( _val ) \
0775   ( ( ( _val ) << GR1553B_RTMCC_TSB_SHIFT ) & \
0776     GR1553B_RTMCC_TSB_MASK )
0777
0778 #define GR1553B_RTMCC_TS_SHIFT 8
0779 #define GR1553B_RTMCC_TS_MASK 0x300U
0780 #define GR1553B_RTMCC_TS_GET( _reg ) \
0781   ( ( ( _reg ) & GR1553B_RTMCC_TS_MASK ) >> \
0782     GR1553B_RTMCC_TS_SHIFT )
0783 #define GR1553B_RTMCC_TS_SET( _reg, _val ) \
0784   ( ( ( _reg ) & ~GR1553B_RTMCC_TS_MASK ) | \
0785     ( ( ( _val ) << GR1553B_RTMCC_TS_SHIFT ) & \
0786       GR1553B_RTMCC_TS_MASK ) )
0787 #define GR1553B_RTMCC_TS( _val ) \
0788   ( ( ( _val ) << GR1553B_RTMCC_TS_SHIFT ) & \
0789     GR1553B_RTMCC_TS_MASK )
0790
0791 #define GR1553B_RTMCC_SDB_SHIFT 6
0792 #define GR1553B_RTMCC_SDB_MASK 0xc0U
0793 #define GR1553B_RTMCC_SDB_GET( _reg ) \
0794   ( ( ( _reg ) & GR1553B_RTMCC_SDB_MASK ) >> \
0795     GR1553B_RTMCC_SDB_SHIFT )
0796 #define GR1553B_RTMCC_SDB_SET( _reg, _val ) \
0797   ( ( ( _reg ) & ~GR1553B_RTMCC_SDB_MASK ) | \
0798     ( ( ( _val ) << GR1553B_RTMCC_SDB_SHIFT ) & \
0799       GR1553B_RTMCC_SDB_MASK ) )
0800 #define GR1553B_RTMCC_SDB( _val ) \
0801   ( ( ( _val ) << GR1553B_RTMCC_SDB_SHIFT ) & \
0802     GR1553B_RTMCC_SDB_MASK )
0803
0804 #define GR1553B_RTMCC_SD_SHIFT 4
0805 #define GR1553B_RTMCC_SD_MASK 0x30U
0806 #define GR1553B_RTMCC_SD_GET( _reg ) \
0807   ( ( ( _reg ) & GR1553B_RTMCC_SD_MASK ) >> \
0808     GR1553B_RTMCC_SD_SHIFT )
0809 #define GR1553B_RTMCC_SD_SET( _reg, _val ) \
0810   ( ( ( _reg ) & ~GR1553B_RTMCC_SD_MASK ) | \
0811     ( ( ( _val ) << GR1553B_RTMCC_SD_SHIFT ) & \
0812       GR1553B_RTMCC_SD_MASK ) )
0813 #define GR1553B_RTMCC_SD( _val ) \
0814   ( ( ( _val ) << GR1553B_RTMCC_SD_SHIFT ) & \
0815     GR1553B_RTMCC_SD_MASK )
0816
0817 #define GR1553B_RTMCC_SB_SHIFT 2
0818 #define GR1553B_RTMCC_SB_MASK 0xcU
0819 #define GR1553B_RTMCC_SB_GET( _reg ) \
0820   ( ( ( _reg ) & GR1553B_RTMCC_SB_MASK ) >> \
0821     GR1553B_RTMCC_SB_SHIFT )
0822 #define GR1553B_RTMCC_SB_SET( _reg, _val ) \
0823   ( ( ( _reg ) & ~GR1553B_RTMCC_SB_MASK ) | \
0824     ( ( ( _val ) << GR1553B_RTMCC_SB_SHIFT ) & \
0825       GR1553B_RTMCC_SB_MASK ) )
0826 #define GR1553B_RTMCC_SB( _val ) \
0827   ( ( ( _val ) << GR1553B_RTMCC_SB_SHIFT ) & \
0828     GR1553B_RTMCC_SB_MASK )
0829
0830 #define GR1553B_RTMCC_S_SHIFT 0
0831 #define GR1553B_RTMCC_S_MASK 0x3U
0832 #define GR1553B_RTMCC_S_GET( _reg ) \
0833   ( ( ( _reg ) & GR1553B_RTMCC_S_MASK ) >> \
0834     GR1553B_RTMCC_S_SHIFT )
0835 #define GR1553B_RTMCC_S_SET( _reg, _val ) \
0836   ( ( ( _reg ) & ~GR1553B_RTMCC_S_MASK ) | \
0837     ( ( ( _val ) << GR1553B_RTMCC_S_SHIFT ) & \
0838       GR1553B_RTMCC_S_MASK ) )
0839 #define GR1553B_RTMCC_S( _val ) \
0840   ( ( ( _val ) << GR1553B_RTMCC_S_SHIFT ) & \
0841     GR1553B_RTMCC_S_MASK )
0842
0843 /** @} */
0844
0845 /**
0846  * @defgroup RTEMSDeviceGR1553BRTTTC \
0847  *   GR1553B RT Time tag control register (RTTTC)
0848  *
0849  * @brief This group contains register bit definitions.
0850  *
0851  * @{
0852  */
0853
0854 #define GR1553B_RTTTC_TRES_SHIFT 16
0855 #define GR1553B_RTTTC_TRES_MASK 0xffff0000U
0856 #define GR1553B_RTTTC_TRES_GET( _reg ) \
0857   ( ( ( _reg ) & GR1553B_RTTTC_TRES_MASK ) >> \
0858     GR1553B_RTTTC_TRES_SHIFT )
0859 #define GR1553B_RTTTC_TRES_SET( _reg, _val ) \
0860   ( ( ( _reg ) & ~GR1553B_RTTTC_TRES_MASK ) | \
0861     ( ( ( _val ) << GR1553B_RTTTC_TRES_SHIFT ) & \
0862       GR1553B_RTTTC_TRES_MASK ) )
0863 #define GR1553B_RTTTC_TRES( _val ) \
0864   ( ( ( _val ) << GR1553B_RTTTC_TRES_SHIFT ) & \
0865     GR1553B_RTTTC_TRES_MASK )
0866
0867 #define GR1553B_RTTTC_TVAL_SHIFT 0
0868 #define GR1553B_RTTTC_TVAL_MASK 0xffffU
0869 #define GR1553B_RTTTC_TVAL_GET( _reg ) \
0870   ( ( ( _reg ) & GR1553B_RTTTC_TVAL_MASK ) >> \
0871     GR1553B_RTTTC_TVAL_SHIFT )
0872 #define GR1553B_RTTTC_TVAL_SET( _reg, _val ) \
0873   ( ( ( _reg ) & ~GR1553B_RTTTC_TVAL_MASK ) | \
0874     ( ( ( _val ) << GR1553B_RTTTC_TVAL_SHIFT ) & \
0875       GR1553B_RTTTC_TVAL_MASK ) )
0876 #define GR1553B_RTTTC_TVAL( _val ) \
0877   ( ( ( _val ) << GR1553B_RTTTC_TVAL_SHIFT ) & \
0878     GR1553B_RTTTC_TVAL_MASK )
0879
0880 /** @} */
0881
0882 /**
0883  * @defgroup RTEMSDeviceGR1553BRTELM \
0884  *   GR1553B RT Event log size mask register (RTELM)
0885  *
0886  * @brief This group contains register bit definitions.
0887  *
0888  * @{
0889  */
0890
0891 #define GR1553B_RTELM_MASK_SHIFT 0
0892 #define GR1553B_RTELM_MASK_MASK 0xffffffffU
0893 #define GR1553B_RTELM_MASK_GET( _reg ) \
0894   ( ( ( _reg ) & GR1553B_RTELM_MASK_MASK ) >> \
0895     GR1553B_RTELM_MASK_SHIFT )
0896 #define GR1553B_RTELM_MASK_SET( _reg, _val ) \
0897   ( ( ( _reg ) & ~GR1553B_RTELM_MASK_MASK ) | \
0898     ( ( ( _val ) << GR1553B_RTELM_MASK_SHIFT ) & \
0899       GR1553B_RTELM_MASK_MASK ) )
0900 #define GR1553B_RTELM_MASK( _val ) \
0901   ( ( ( _val ) << GR1553B_RTELM_MASK_SHIFT ) & \
0902     GR1553B_RTELM_MASK_MASK )
0903
0904 /** @} */
0905
0906 /**
0907  * @defgroup RTEMSDeviceGR1553BRTELP \
0908  *   GR1553B RT Event log position register (RTELP)
0909  *
0910  * @brief This group contains register bit definitions.
0911  *
0912  * @{
0913  */
0914
0915 #define GR1553B_RTELP_POINTER_SHIFT 0
0916 #define GR1553B_RTELP_POINTER_MASK 0xffffffffU
0917 #define GR1553B_RTELP_POINTER_GET( _reg ) \
0918   ( ( ( _reg ) & GR1553B_RTELP_POINTER_MASK ) >> \
0919     GR1553B_RTELP_POINTER_SHIFT )
0920 #define GR1553B_RTELP_POINTER_SET( _reg, _val ) \
0921   ( ( ( _reg ) & ~GR1553B_RTELP_POINTER_MASK ) | \
0922     ( ( ( _val ) << GR1553B_RTELP_POINTER_SHIFT ) & \
0923       GR1553B_RTELP_POINTER_MASK ) )
0924 #define GR1553B_RTELP_POINTER( _val ) \
0925   ( ( ( _val ) << GR1553B_RTELP_POINTER_SHIFT ) & \
0926     GR1553B_RTELP_POINTER_MASK )
0927
0928 /** @} */
0929
0930 /**
0931  * @defgroup RTEMSDeviceGR1553BRTELIP \
0932  *   GR1553B RT Event Log interrupt position register (RTELIP)
0933  *
0934  * @brief This group contains register bit definitions.
0935  *
0936  * @{
0937  */
0938
0939 #define GR1553B_RTELIP_POINTER_SHIFT 0
0940 #define GR1553B_RTELIP_POINTER_MASK 0xffffffffU
0941 #define GR1553B_RTELIP_POINTER_GET( _reg ) \
0942   ( ( ( _reg ) & GR1553B_RTELIP_POINTER_MASK ) >> \
0943     GR1553B_RTELIP_POINTER_SHIFT )
0944 #define GR1553B_RTELIP_POINTER_SET( _reg, _val ) \
0945   ( ( ( _reg ) & ~GR1553B_RTELIP_POINTER_MASK ) | \
0946     ( ( ( _val ) << GR1553B_RTELIP_POINTER_SHIFT ) & \
0947       GR1553B_RTELIP_POINTER_MASK ) )
0948 #define GR1553B_RTELIP_POINTER( _val ) \
0949   ( ( ( _val ) << GR1553B_RTELIP_POINTER_SHIFT ) & \
0950     GR1553B_RTELIP_POINTER_MASK )
0951
0952 /** @} */
0953
0954 /**
0955  * @defgroup RTEMSDeviceGR1553BBMS GR1553B BM Status register (BMS)
0956  *
0957  * @brief This group contains register bit definitions.
0958  *
0959  * @{
0960  */
0961
0962 #define GR1553B_BMS_BMSUP 0x80000000U
0963
0964 #define GR1553B_BMS_KEYEN 0x40000000U
0965
0966 /** @} */
0967
0968 /**
0969  * @defgroup RTEMSDeviceGR1553BBMC GR1553B BM Control register (BMC)
0970  *
0971  * @brief This group contains register bit definitions.
0972  *
0973  * @{
0974  */
0975
0976 #define GR1553B_BMC_BMKEY_SHIFT 16
0977 #define GR1553B_BMC_BMKEY_MASK 0xffff0000U
0978 #define GR1553B_BMC_BMKEY_GET( _reg ) \
0979   ( ( ( _reg ) & GR1553B_BMC_BMKEY_MASK ) >> \
0980     GR1553B_BMC_BMKEY_SHIFT )
0981 #define GR1553B_BMC_BMKEY_SET( _reg, _val ) \
0982   ( ( ( _reg ) & ~GR1553B_BMC_BMKEY_MASK ) | \
0983     ( ( ( _val ) << GR1553B_BMC_BMKEY_SHIFT ) & \
0984       GR1553B_BMC_BMKEY_MASK ) )
0985 #define GR1553B_BMC_BMKEY( _val ) \
0986   ( ( ( _val ) << GR1553B_BMC_BMKEY_SHIFT ) & \
0987     GR1553B_BMC_BMKEY_MASK )
0988
0989 #define GR1553B_BMC_WRSTP 0x20U
0990
0991 #define GR1553B_BMC_EXST 0x10U
0992
0993 #define GR1553B_BMC_IMCL 0x8U
0994
0995 #define GR1553B_BMC_UDWL 0x4U
0996
0997 #define GR1553B_BMC_MANL 0x2U
0998
0999 #define GR1553B_BMC_BMEN 0x1U
1000
1001 /** @} */
1002
1003 /**
1004  * @defgroup RTEMSDeviceGR1553BBMRTAF \
1005  *   GR1553B BM RT Address filter register (BMRTAF)
1006  *
1007  * @brief This group contains register bit definitions.
1008  *
1009  * @{
1010  */
1011
1012 #define GR1553B_BMRTAF_MASK_SHIFT 0
1013 #define GR1553B_BMRTAF_MASK_MASK 0xffffffffU
1014 #define GR1553B_BMRTAF_MASK_GET( _reg ) \
1015   ( ( ( _reg ) & GR1553B_BMRTAF_MASK_MASK ) >> \
1016     GR1553B_BMRTAF_MASK_SHIFT )
1017 #define GR1553B_BMRTAF_MASK_SET( _reg, _val ) \
1018   ( ( ( _reg ) & ~GR1553B_BMRTAF_MASK_MASK ) | \
1019     ( ( ( _val ) << GR1553B_BMRTAF_MASK_SHIFT ) & \
1020       GR1553B_BMRTAF_MASK_MASK ) )
1021 #define GR1553B_BMRTAF_MASK( _val ) \
1022   ( ( ( _val ) << GR1553B_BMRTAF_MASK_SHIFT ) & \
1023     GR1553B_BMRTAF_MASK_MASK )
1024
1025 /** @} */
1026
1027 /**
1028  * @defgroup RTEMSDeviceGR1553BBMRTSF \
1029  *   GR1553B BM RT Subaddress filter register (BMRTSF)
1030  *
1031  * @brief This group contains register bit definitions.
1032  *
1033  * @{
1034  */
1035
1036 #define GR1553B_BMRTSF_MASK_SHIFT 0
1037 #define GR1553B_BMRTSF_MASK_MASK 0xffffffffU
1038 #define GR1553B_BMRTSF_MASK_GET( _reg ) \
1039   ( ( ( _reg ) & GR1553B_BMRTSF_MASK_MASK ) >> \
1040     GR1553B_BMRTSF_MASK_SHIFT )
1041 #define GR1553B_BMRTSF_MASK_SET( _reg, _val ) \
1042   ( ( ( _reg ) & ~GR1553B_BMRTSF_MASK_MASK ) | \
1043     ( ( ( _val ) << GR1553B_BMRTSF_MASK_SHIFT ) & \
1044       GR1553B_BMRTSF_MASK_MASK ) )
1045 #define GR1553B_BMRTSF_MASK( _val ) \
1046   ( ( ( _val ) << GR1553B_BMRTSF_MASK_SHIFT ) & \
1047     GR1553B_BMRTSF_MASK_MASK )
1048
1049 /** @} */
1050
1051 /**
1052  * @defgroup RTEMSDeviceGR1553BBMRTMC \
1053  *   GR1553B BM RT Mode code filter register (BMRTMC)
1054  *
1055  * @brief This group contains register bit definitions.
1056  *
1057  * @{
1058  */
1059
1060 #define GR1553B_BMRTMC_STSB 0x40000U
1061
1062 #define GR1553B_BMRTMC_STS 0x20000U
1063
1064 #define GR1553B_BMRTMC_TLC 0x10000U
1065
1066 #define GR1553B_BMRTMC_TSW 0x8000U
1067
1068 #define GR1553B_BMRTMC_RRTB 0x4000U
1069
1070 #define GR1553B_BMRTMC_RRT 0x2000U
1071
1072 #define GR1553B_BMRTMC_ITFB 0x1000U
1073
1074 #define GR1553B_BMRTMC_ITF 0x800U
1075
1076 #define GR1553B_BMRTMC_ISTB 0x400U
1077
1078 #define GR1553B_BMRTMC_IST 0x200U
1079
1080 #define GR1553B_BMRTMC_DBC 0x100U
1081
1082 #define GR1553B_BMRTMC_TBW 0x80U
1083
1084 #define GR1553B_BMRTMC_TVW 0x40U
1085
1086 #define GR1553B_BMRTMC_TSB 0x20U
1087
1088 #define GR1553B_BMRTMC_TS 0x10U
1089
1090 #define GR1553B_BMRTMC_SDB 0x8U
1091
1092 #define GR1553B_BMRTMC_SD 0x4U
1093
1094 #define GR1553B_BMRTMC_SB 0x2U
1095
1096 #define GR1553B_BMRTMC_S 0x1U
1097
1098 /** @} */
1099
1100 /**
1101  * @defgroup RTEMSDeviceGR1553BBMLBS GR1553B BM Log buffer start (BMLBS)
1102  *
1103  * @brief This group contains register bit definitions.
1104  *
1105  * @{
1106  */
1107
1108 #define GR1553B_BMLBS_START_SHIFT 0
1109 #define GR1553B_BMLBS_START_MASK 0xffffffffU
1110 #define GR1553B_BMLBS_START_GET( _reg ) \
1111   ( ( ( _reg ) & GR1553B_BMLBS_START_MASK ) >> \
1112     GR1553B_BMLBS_START_SHIFT )
1113 #define GR1553B_BMLBS_START_SET( _reg, _val ) \
1114   ( ( ( _reg ) & ~GR1553B_BMLBS_START_MASK ) | \
1115     ( ( ( _val ) << GR1553B_BMLBS_START_SHIFT ) & \
1116       GR1553B_BMLBS_START_MASK ) )
1117 #define GR1553B_BMLBS_START( _val ) \
1118   ( ( ( _val ) << GR1553B_BMLBS_START_SHIFT ) & \
1119     GR1553B_BMLBS_START_MASK )
1120
1121 /** @} */
1122
1123 /**
1124  * @defgroup RTEMSDeviceGR1553BBMLBE GR1553B BM Log buffer end (BMLBE)
1125  *
1126  * @brief This group contains register bit definitions.
1127  *
1128  * @{
1129  */
1130
1131 #define GR1553B_BMLBE_END_SHIFT 0
1132 #define GR1553B_BMLBE_END_MASK 0xffffffffU
1133 #define GR1553B_BMLBE_END_GET( _reg ) \
1134   ( ( ( _reg ) & GR1553B_BMLBE_END_MASK ) >> \
1135     GR1553B_BMLBE_END_SHIFT )
1136 #define GR1553B_BMLBE_END_SET( _reg, _val ) \
1137   ( ( ( _reg ) & ~GR1553B_BMLBE_END_MASK ) | \
1138     ( ( ( _val ) << GR1553B_BMLBE_END_SHIFT ) & \
1139       GR1553B_BMLBE_END_MASK ) )
1140 #define GR1553B_BMLBE_END( _val ) \
1141   ( ( ( _val ) << GR1553B_BMLBE_END_SHIFT ) & \
1142     GR1553B_BMLBE_END_MASK )
1143
1144 /** @} */
1145
1146 /**
1147  * @defgroup RTEMSDeviceGR1553BBMLBP GR1553B BM Log buffer position (BMLBP)
1148  *
1149  * @brief This group contains register bit definitions.
1150  *
1151  * @{
1152  */
1153
1154 #define GR1553B_BMLBP_POSITION_SHIFT 0
1155 #define GR1553B_BMLBP_POSITION_MASK 0xffffffffU
1156 #define GR1553B_BMLBP_POSITION_GET( _reg ) \
1157   ( ( ( _reg ) & GR1553B_BMLBP_POSITION_MASK ) >> \
1158     GR1553B_BMLBP_POSITION_SHIFT )
1159 #define GR1553B_BMLBP_POSITION_SET( _reg, _val ) \
1160   ( ( ( _reg ) & ~GR1553B_BMLBP_POSITION_MASK ) | \
1161     ( ( ( _val ) << GR1553B_BMLBP_POSITION_SHIFT ) & \
1162       GR1553B_BMLBP_POSITION_MASK ) )
1163 #define GR1553B_BMLBP_POSITION( _val ) \
1164   ( ( ( _val ) << GR1553B_BMLBP_POSITION_SHIFT ) & \
1165     GR1553B_BMLBP_POSITION_MASK )
1166
1167 /** @} */
1168
1169 /**
1170  * @defgroup RTEMSDeviceGR1553BBMTTC \
1171  *   GR1553B BM Time tag control register (BMTTC)
1172  *
1173  * @brief This group contains register bit definitions.
1174  *
1175  * @{
1176  */
1177
1178 #define GR1553B_BMTTC_TRES_SHIFT 24
1179 #define GR1553B_BMTTC_TRES_MASK 0xff000000U
1180 #define GR1553B_BMTTC_TRES_GET( _reg ) \
1181   ( ( ( _reg ) & GR1553B_BMTTC_TRES_MASK ) >> \
1182     GR1553B_BMTTC_TRES_SHIFT )
1183 #define GR1553B_BMTTC_TRES_SET( _reg, _val ) \
1184   ( ( ( _reg ) & ~GR1553B_BMTTC_TRES_MASK ) | \
1185     ( ( ( _val ) << GR1553B_BMTTC_TRES_SHIFT ) & \
1186       GR1553B_BMTTC_TRES_MASK ) )
1187 #define GR1553B_BMTTC_TRES( _val ) \
1188   ( ( ( _val ) << GR1553B_BMTTC_TRES_SHIFT ) & \
1189     GR1553B_BMTTC_TRES_MASK )
1190
1191 #define GR1553B_BMTTC_TVAL_SHIFT 0
1192 #define GR1553B_BMTTC_TVAL_MASK 0xffffffU
1193 #define GR1553B_BMTTC_TVAL_GET( _reg ) \
1194   ( ( ( _reg ) & GR1553B_BMTTC_TVAL_MASK ) >> \
1195     GR1553B_BMTTC_TVAL_SHIFT )
1196 #define GR1553B_BMTTC_TVAL_SET( _reg, _val ) \
1197   ( ( ( _reg ) & ~GR1553B_BMTTC_TVAL_MASK ) | \
1198     ( ( ( _val ) << GR1553B_BMTTC_TVAL_SHIFT ) & \
1199       GR1553B_BMTTC_TVAL_MASK ) )
1200 #define GR1553B_BMTTC_TVAL( _val ) \
1201   ( ( ( _val ) << GR1553B_BMTTC_TVAL_SHIFT ) & \
1202     GR1553B_BMTTC_TVAL_MASK )
1203
1204 /** @} */
1205
1206 /**
1207  * @brief This structure defines the GR1553B register block memory map.
1208  */
1209 typedef struct gr1553b {
1210   /**
1211    * @brief See @ref RTEMSDeviceGR1553BIRQ.
1212    */
1213   uint32_t irq;
1214
1215   /**
1216    * @brief See @ref RTEMSDeviceGR1553BIRQE.
1217    */
1218   uint32_t irqe;
1219
1220   uint32_t reserved_8_10[ 2 ];
1221
1222   /**
1223    * @brief See @ref RTEMSDeviceGR1553BHC.
1224    */
1225   uint32_t hc;
1226
1227   uint32_t reserved_14_40[ 11 ];
1228
1229   /**
1230    * @brief See @ref RTEMSDeviceGR1553BBCSC.
1231    */
1232   uint32_t bcsc;
1233
1234   /**
1235    * @brief See @ref RTEMSDeviceGR1553BBCA.
1236    */
1237   uint32_t bca;
1238
1239   /**
1240    * @brief See @ref RTEMSDeviceGR1553BBCTNP.
1241    */
1242   uint32_t bctnp;
1243
1244   /**
1245    * @brief See @ref RTEMSDeviceGR1553BBCANP.
1246    */
1247   uint32_t bcanp;
1248
1249   /**
1250    * @brief See @ref RTEMSDeviceGR1553BBCT.
1251    */
1252   uint32_t bct;
1253
1254   uint32_t reserved_54_58;
1255
1256   /**
1257    * @brief See @ref RTEMSDeviceGR1553BBCRP.
1258    */
1259   uint32_t bcrp;
1260
1261   /**
1262    * @brief See @ref RTEMSDeviceGR1553BBCBS.
1263    */
1264   uint32_t bcbs;
1265
1266   uint32_t reserved_60_68[ 2 ];
1267
1268   /**
1269    * @brief See @ref RTEMSDeviceGR1553BBCTCP.
1270    */
1271   uint32_t bctcp;
1272
1273   /**
1274    * @brief See @ref RTEMSDeviceGR1553BBCACP.
1275    */
1276   uint32_t bcacp;
1277
1278   uint32_t reserved_70_80[ 4 ];
1279
1280   /**
1281    * @brief See @ref RTEMSDeviceGR1553BRTS.
1282    */
1283   uint32_t rts;
1284
1285   /**
1286    * @brief See @ref RTEMSDeviceGR1553BRTC.
1287    */
1288   uint32_t rtc;
1289
1290   /**
1291    * @brief See @ref RTEMSDeviceGR1553BRTBS.
1292    */
1293   uint32_t rtbs;
1294
1295   /**
1296    * @brief See @ref RTEMSDeviceGR1553BRTSW.
1297    */
1298   uint32_t rtsw;
1299
1300   /**
1301    * @brief See @ref RTEMSDeviceGR1553BRTSY.
1302    */
1303   uint32_t rtsy;
1304
1305   /**
1306    * @brief See @ref RTEMSDeviceGR1553BRTSTBA.
1307    */
1308   uint32_t rtstba;
1309
1310   /**
1311    * @brief See @ref RTEMSDeviceGR1553BRTMCC.
1312    */
1313   uint32_t rtmcc;
1314
1315   uint32_t reserved_9c_a4[ 2 ];
1316
1317   /**
1318    * @brief See @ref RTEMSDeviceGR1553BRTTTC.
1319    */
1320   uint32_t rtttc;
1321
1322   uint32_t reserved_a8_ac;
1323
1324   /**
1325    * @brief See @ref RTEMSDeviceGR1553BRTELM.
1326    */
1327   uint32_t rtelm;
1328
1329   /**
1330    * @brief See @ref RTEMSDeviceGR1553BRTELP.
1331    */
1332   uint32_t rtelp;
1333
1334   /**
1335    * @brief See @ref RTEMSDeviceGR1553BRTELIP.
1336    */
1337   uint32_t rtelip;
1338
1339   uint32_t reserved_b8_c0[ 2 ];
1340
1341   /**
1342    * @brief See @ref RTEMSDeviceGR1553BBMS.
1343    */
1344   uint32_t bms;
1345
1346   /**
1347    * @brief See @ref RTEMSDeviceGR1553BBMC.
1348    */
1349   uint32_t bmc;
1350
1351   /**
1352    * @brief See @ref RTEMSDeviceGR1553BBMRTAF.
1353    */
1354   uint32_t bmrtaf;
1355
1356   /**
1357    * @brief See @ref RTEMSDeviceGR1553BBMRTSF.
1358    */
1359   uint32_t bmrtsf;
1360
1361   /**
1362    * @brief See @ref RTEMSDeviceGR1553BBMRTMC.
1363    */
1364   uint32_t bmrtmc;
1365
1366   /**
1367    * @brief See @ref RTEMSDeviceGR1553BBMLBS.
1368    */
1369   uint32_t bmlbs;
1370
1371   /**
1372    * @brief See @ref RTEMSDeviceGR1553BBMLBE.
1373    */
1374   uint32_t bmlbe;
1375
1376   /**
1377    * @brief See @ref RTEMSDeviceGR1553BBMLBP.
1378    */
1379   uint32_t bmlbp;
1380
1381   /**
1382    * @brief See @ref RTEMSDeviceGR1553BBMTTC.
1383    */
1384   uint32_t bmttc;
1385 } gr1553b;
1386
1387 /** @} */
1388
1389 #ifdef __cplusplus
1390 }
1391 #endif
1392
1393 #endif /* _GRLIB_GR1553B_REGS_H */