include/grlib/gptimer-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRLIBGPTIMER
0007  *
0008  * @brief This header file defines the GPTIMER register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/gptimer-header */
0054
0055 #ifndef _GRLIB_GPTIMER_REGS_H
0056 #define _GRLIB_GPTIMER_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/group */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRLIB GRLIB
0068  *
0069  * @ingroup RTEMSDeviceDrivers
0070  *
0071  * @brief This group contains the GRLIB interfaces.
0072  */
0073
0074 /* Generated from spec:/dev/grlib/if/gptimer-timer */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRLIBGPTIMERTimer GPTIMER TIMER
0078  *
0079  * @ingroup RTEMSDeviceGRLIBGPTIMER
0080  *
0081  * @brief This group contains the GPTIMER TIMER interfaces.
0082  *
0083  * @{
0084  */
0085
0086 /**
0087  * @defgroup RTEMSDeviceGRLIBGPTIMERTimerTCNTVAL \
0088  *   Timer n counter value register (TCNTVAL)
0089  *
0090  * @brief This group contains register bit definitions.
0091  *
0092  * @{
0093  */
0094
0095 #define GPTIMER_TCNTVAL_TCVAL_SHIFT 0
0096 #define GPTIMER_TCNTVAL_TCVAL_MASK 0xffffffffU
0097 #define GPTIMER_TCNTVAL_TCVAL_GET( _reg ) \
0098   ( ( ( _reg ) & GPTIMER_TCNTVAL_TCVAL_MASK ) >> \
0099     GPTIMER_TCNTVAL_TCVAL_SHIFT )
0100 #define GPTIMER_TCNTVAL_TCVAL_SET( _reg, _val ) \
0101   ( ( ( _reg ) & ~GPTIMER_TCNTVAL_TCVAL_MASK ) | \
0102     ( ( ( _val ) << GPTIMER_TCNTVAL_TCVAL_SHIFT ) & \
0103       GPTIMER_TCNTVAL_TCVAL_MASK ) )
0104 #define GPTIMER_TCNTVAL_TCVAL( _val ) \
0105   ( ( ( _val ) << GPTIMER_TCNTVAL_TCVAL_SHIFT ) & \
0106     GPTIMER_TCNTVAL_TCVAL_MASK )
0107
0108 /** @} */
0109
0110 /**
0111  * @defgroup RTEMSDeviceGRLIBGPTIMERTimerTRLDVAL \
0112  *   Timer n counter reload value register (TRLDVAL)
0113  *
0114  * @brief This group contains register bit definitions.
0115  *
0116  * @{
0117  */
0118
0119 #define GPTIMER_TRLDVAL_TRLDVAL_SHIFT 0
0120 #define GPTIMER_TRLDVAL_TRLDVAL_MASK 0xffffffffU
0121 #define GPTIMER_TRLDVAL_TRLDVAL_GET( _reg ) \
0122   ( ( ( _reg ) & GPTIMER_TRLDVAL_TRLDVAL_MASK ) >> \
0123     GPTIMER_TRLDVAL_TRLDVAL_SHIFT )
0124 #define GPTIMER_TRLDVAL_TRLDVAL_SET( _reg, _val ) \
0125   ( ( ( _reg ) & ~GPTIMER_TRLDVAL_TRLDVAL_MASK ) | \
0126     ( ( ( _val ) << GPTIMER_TRLDVAL_TRLDVAL_SHIFT ) & \
0127       GPTIMER_TRLDVAL_TRLDVAL_MASK ) )
0128 #define GPTIMER_TRLDVAL_TRLDVAL( _val ) \
0129   ( ( ( _val ) << GPTIMER_TRLDVAL_TRLDVAL_SHIFT ) & \
0130     GPTIMER_TRLDVAL_TRLDVAL_MASK )
0131
0132 /** @} */
0133
0134 /**
0135  * @defgroup RTEMSDeviceGRLIBGPTIMERTimerTCTRL Timer n control register (TCTRL)
0136  *
0137  * @brief This group contains register bit definitions.
0138  *
0139  * @{
0140  */
0141
0142 #define GPTIMER_TCTRL_WS 0x100U
0143
0144 #define GPTIMER_TCTRL_WN 0x80U
0145
0146 #define GPTIMER_TCTRL_DH 0x40U
0147
0148 #define GPTIMER_TCTRL_CH 0x20U
0149
0150 #define GPTIMER_TCTRL_IP 0x10U
0151
0152 #define GPTIMER_TCTRL_IE 0x8U
0153
0154 #define GPTIMER_TCTRL_LD 0x4U
0155
0156 #define GPTIMER_TCTRL_RS 0x2U
0157
0158 #define GPTIMER_TCTRL_EN 0x1U
0159
0160 /** @} */
0161
0162 /**
0163  * @defgroup RTEMSDeviceGRLIBGPTIMERTimerTLATCH Timer n latch register (TLATCH)
0164  *
0165  * @brief This group contains register bit definitions.
0166  *
0167  * @{
0168  */
0169
0170 #define GPTIMER_TLATCH_LTCV_SHIFT 0
0171 #define GPTIMER_TLATCH_LTCV_MASK 0xffffffffU
0172 #define GPTIMER_TLATCH_LTCV_GET( _reg ) \
0173   ( ( ( _reg ) & GPTIMER_TLATCH_LTCV_MASK ) >> \
0174     GPTIMER_TLATCH_LTCV_SHIFT )
0175 #define GPTIMER_TLATCH_LTCV_SET( _reg, _val ) \
0176   ( ( ( _reg ) & ~GPTIMER_TLATCH_LTCV_MASK ) | \
0177     ( ( ( _val ) << GPTIMER_TLATCH_LTCV_SHIFT ) & \
0178       GPTIMER_TLATCH_LTCV_MASK ) )
0179 #define GPTIMER_TLATCH_LTCV( _val ) \
0180   ( ( ( _val ) << GPTIMER_TLATCH_LTCV_SHIFT ) & \
0181     GPTIMER_TLATCH_LTCV_MASK )
0182
0183 /** @} */
0184
0185 /**
0186  * @brief This structure defines the GPTIMER TIMER register block memory map.
0187  */
0188 typedef struct gptimer_timer {
0189   /**
0190    * @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTCNTVAL.
0191    */
0192   uint32_t tcntval;
0193
0194   /**
0195    * @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTRLDVAL.
0196    */
0197   uint32_t trldval;
0198
0199   /**
0200    * @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTCTRL.
0201    */
0202   uint32_t tctrl;
0203
0204   /**
0205    * @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTLATCH.
0206    */
0207   uint32_t tlatch;
0208 } gptimer_timer;
0209
0210 /** @} */
0211
0212 /* Generated from spec:/dev/grlib/if/gptimer */
0213
0214 /**
0215  * @defgroup RTEMSDeviceGRLIBGPTIMER GPTIMER
0216  *
0217  * @ingroup RTEMSDeviceGRLIB
0218  *
0219  * @brief This group contains the GPTIMER interfaces.
0220  *
0221  * @{
0222  */
0223
0224 /**
0225  * @defgroup RTEMSDeviceGRLIBGPTIMERSCALER Scaler value register (SCALER)
0226  *
0227  * @brief This group contains register bit definitions.
0228  *
0229  * @{
0230  */
0231
0232 #define GPTIMER_SCALER_SCALER_SHIFT 0
0233 #define GPTIMER_SCALER_SCALER_MASK 0xffffU
0234 #define GPTIMER_SCALER_SCALER_GET( _reg ) \
0235   ( ( ( _reg ) & GPTIMER_SCALER_SCALER_MASK ) >> \
0236     GPTIMER_SCALER_SCALER_SHIFT )
0237 #define GPTIMER_SCALER_SCALER_SET( _reg, _val ) \
0238   ( ( ( _reg ) & ~GPTIMER_SCALER_SCALER_MASK ) | \
0239     ( ( ( _val ) << GPTIMER_SCALER_SCALER_SHIFT ) & \
0240       GPTIMER_SCALER_SCALER_MASK ) )
0241 #define GPTIMER_SCALER_SCALER( _val ) \
0242   ( ( ( _val ) << GPTIMER_SCALER_SCALER_SHIFT ) & \
0243     GPTIMER_SCALER_SCALER_MASK )
0244
0245 /** @} */
0246
0247 /**
0248  * @defgroup RTEMSDeviceGRLIBGPTIMERSRELOAD \
0249  *   Scaler reload value register (SRELOAD)
0250  *
0251  * @brief This group contains register bit definitions.
0252  *
0253  * @{
0254  */
0255
0256 #define GPTIMER_SRELOAD_SRELOAD_SHIFT 0
0257 #define GPTIMER_SRELOAD_SRELOAD_MASK 0xffffU
0258 #define GPTIMER_SRELOAD_SRELOAD_GET( _reg ) \
0259   ( ( ( _reg ) & GPTIMER_SRELOAD_SRELOAD_MASK ) >> \
0260     GPTIMER_SRELOAD_SRELOAD_SHIFT )
0261 #define GPTIMER_SRELOAD_SRELOAD_SET( _reg, _val ) \
0262   ( ( ( _reg ) & ~GPTIMER_SRELOAD_SRELOAD_MASK ) | \
0263     ( ( ( _val ) << GPTIMER_SRELOAD_SRELOAD_SHIFT ) & \
0264       GPTIMER_SRELOAD_SRELOAD_MASK ) )
0265 #define GPTIMER_SRELOAD_SRELOAD( _val ) \
0266   ( ( ( _val ) << GPTIMER_SRELOAD_SRELOAD_SHIFT ) & \
0267     GPTIMER_SRELOAD_SRELOAD_MASK )
0268
0269 /** @} */
0270
0271 /**
0272  * @defgroup RTEMSDeviceGRLIBGPTIMERCONFIG Configuration register (CONFIG)
0273  *
0274  * @brief This group contains register bit definitions.
0275  *
0276  * @{
0277  */
0278
0279 #define GPTIMER_CONFIG_EV 0x2000U
0280
0281 #define GPTIMER_CONFIG_ES 0x1000U
0282
0283 #define GPTIMER_CONFIG_EL 0x800U
0284
0285 #define GPTIMER_CONFIG_EE 0x400U
0286
0287 #define GPTIMER_CONFIG_DF 0x200U
0288
0289 #define GPTIMER_CONFIG_SI 0x100U
0290
0291 #define GPTIMER_CONFIG_IRQ_SHIFT 3
0292 #define GPTIMER_CONFIG_IRQ_MASK 0xf8U
0293 #define GPTIMER_CONFIG_IRQ_GET( _reg ) \
0294   ( ( ( _reg ) & GPTIMER_CONFIG_IRQ_MASK ) >> \
0295     GPTIMER_CONFIG_IRQ_SHIFT )
0296 #define GPTIMER_CONFIG_IRQ_SET( _reg, _val ) \
0297   ( ( ( _reg ) & ~GPTIMER_CONFIG_IRQ_MASK ) | \
0298     ( ( ( _val ) << GPTIMER_CONFIG_IRQ_SHIFT ) & \
0299       GPTIMER_CONFIG_IRQ_MASK ) )
0300 #define GPTIMER_CONFIG_IRQ( _val ) \
0301   ( ( ( _val ) << GPTIMER_CONFIG_IRQ_SHIFT ) & \
0302     GPTIMER_CONFIG_IRQ_MASK )
0303
0304 #define GPTIMER_CONFIG_TIMERS_SHIFT 0
0305 #define GPTIMER_CONFIG_TIMERS_MASK 0x7U
0306 #define GPTIMER_CONFIG_TIMERS_GET( _reg ) \
0307   ( ( ( _reg ) & GPTIMER_CONFIG_TIMERS_MASK ) >> \
0308     GPTIMER_CONFIG_TIMERS_SHIFT )
0309 #define GPTIMER_CONFIG_TIMERS_SET( _reg, _val ) \
0310   ( ( ( _reg ) & ~GPTIMER_CONFIG_TIMERS_MASK ) | \
0311     ( ( ( _val ) << GPTIMER_CONFIG_TIMERS_SHIFT ) & \
0312       GPTIMER_CONFIG_TIMERS_MASK ) )
0313 #define GPTIMER_CONFIG_TIMERS( _val ) \
0314   ( ( ( _val ) << GPTIMER_CONFIG_TIMERS_SHIFT ) & \
0315     GPTIMER_CONFIG_TIMERS_MASK )
0316
0317 /** @} */
0318
0319 /**
0320  * @defgroup RTEMSDeviceGRLIBGPTIMERLATCHCFG \
0321  *   Timer latch configuration register (LATCHCFG)
0322  *
0323  * @brief This group contains register bit definitions.
0324  *
0325  * @{
0326  */
0327
0328 #define GPTIMER_LATCHCFG_LATCHSEL_SHIFT 0
0329 #define GPTIMER_LATCHCFG_LATCHSEL_MASK 0xffffffffU
0330 #define GPTIMER_LATCHCFG_LATCHSEL_GET( _reg ) \
0331   ( ( ( _reg ) & GPTIMER_LATCHCFG_LATCHSEL_MASK ) >> \
0332     GPTIMER_LATCHCFG_LATCHSEL_SHIFT )
0333 #define GPTIMER_LATCHCFG_LATCHSEL_SET( _reg, _val ) \
0334   ( ( ( _reg ) & ~GPTIMER_LATCHCFG_LATCHSEL_MASK ) | \
0335     ( ( ( _val ) << GPTIMER_LATCHCFG_LATCHSEL_SHIFT ) & \
0336       GPTIMER_LATCHCFG_LATCHSEL_MASK ) )
0337 #define GPTIMER_LATCHCFG_LATCHSEL( _val ) \
0338   ( ( ( _val ) << GPTIMER_LATCHCFG_LATCHSEL_SHIFT ) & \
0339     GPTIMER_LATCHCFG_LATCHSEL_MASK )
0340
0341 /** @} */
0342
0343 /**
0344  * @brief This structure defines the GPTIMER register block memory map.
0345  */
0346 typedef struct gptimer {
0347   /**
0348    * @brief See @ref RTEMSDeviceGRLIBGPTIMERSCALER.
0349    */
0350   uint32_t scaler;
0351
0352   /**
0353    * @brief See @ref RTEMSDeviceGRLIBGPTIMERSRELOAD.
0354    */
0355   uint32_t sreload;
0356
0357   /**
0358    * @brief See @ref RTEMSDeviceGRLIBGPTIMERCONFIG.
0359    */
0360   uint32_t config;
0361
0362   /**
0363    * @brief See @ref RTEMSDeviceGRLIBGPTIMERLATCHCFG.
0364    */
0365   uint32_t latchcfg;
0366
0367   /**
0368    * @brief See @ref RTEMSDeviceGRLIBGPTIMERTimer.
0369    */
0370   gptimer_timer timer[ 15 ];
0371 } gptimer;
0372
0373 /** @} */
0374
0375 #ifdef __cplusplus
0376 }
0377 #endif
0378
0379 #endif /* _GRLIB_GPTIMER_REGS_H */