include/grlib/ftmctrl-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRLIBFTMCTRL
0007  *
0008  * @brief This header file defines the FTMCTRL register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/ftmctrl-header */
0054
0055 #ifndef _GRLIB_FTMCTRL_REGS_H
0056 #define _GRLIB_FTMCTRL_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/ftmctrl */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRLIBFTMCTRL FTMCTRL
0068  *
0069  * @ingroup RTEMSDeviceGRLIB
0070  *
0071  * @brief This group contains the FTMCTRL interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG1 \
0078  *   Memory configuration register 1 (MCFG1)
0079  *
0080  * @brief This group contains register bit definitions.
0081  *
0082  * @{
0083  */
0084
0085 #define FTMCTRL_MCFG1_PBRDY 0x40000000U
0086
0087 #define FTMCTRL_MCFG1_ABRDY 0x20000000U
0088
0089 #define FTMCTRL_MCFG1_IOBUSW_SHIFT 27
0090 #define FTMCTRL_MCFG1_IOBUSW_MASK 0x18000000U
0091 #define FTMCTRL_MCFG1_IOBUSW_GET( _reg ) \
0092   ( ( ( _reg ) & FTMCTRL_MCFG1_IOBUSW_MASK ) >> \
0093     FTMCTRL_MCFG1_IOBUSW_SHIFT )
0094 #define FTMCTRL_MCFG1_IOBUSW_SET( _reg, _val ) \
0095   ( ( ( _reg ) & ~FTMCTRL_MCFG1_IOBUSW_MASK ) | \
0096     ( ( ( _val ) << FTMCTRL_MCFG1_IOBUSW_SHIFT ) & \
0097       FTMCTRL_MCFG1_IOBUSW_MASK ) )
0098 #define FTMCTRL_MCFG1_IOBUSW( _val ) \
0099   ( ( ( _val ) << FTMCTRL_MCFG1_IOBUSW_SHIFT ) & \
0100     FTMCTRL_MCFG1_IOBUSW_MASK )
0101
0102 #define FTMCTRL_MCFG1_IBRDY 0x4000000U
0103
0104 #define FTMCTRL_MCFG1_BEXCN 0x2000000U
0105
0106 #define FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT 20
0107 #define FTMCTRL_MCFG1_IO_WAITSTATES_MASK 0xf00000U
0108 #define FTMCTRL_MCFG1_IO_WAITSTATES_GET( _reg ) \
0109   ( ( ( _reg ) & FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) >> \
0110     FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT )
0111 #define FTMCTRL_MCFG1_IO_WAITSTATES_SET( _reg, _val ) \
0112   ( ( ( _reg ) & ~FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) | \
0113     ( ( ( _val ) << FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT ) & \
0114       FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) )
0115 #define FTMCTRL_MCFG1_IO_WAITSTATES( _val ) \
0116   ( ( ( _val ) << FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT ) & \
0117     FTMCTRL_MCFG1_IO_WAITSTATES_MASK )
0118
0119 #define FTMCTRL_MCFG1_IOEN 0x80000U
0120
0121 #define FTMCTRL_MCFG1_R 0x40000U
0122
0123 #define FTMCTRL_MCFG1_ROMBANKSZ_SHIFT 14
0124 #define FTMCTRL_MCFG1_ROMBANKSZ_MASK 0x3c000U
0125 #define FTMCTRL_MCFG1_ROMBANKSZ_GET( _reg ) \
0126   ( ( ( _reg ) & FTMCTRL_MCFG1_ROMBANKSZ_MASK ) >> \
0127     FTMCTRL_MCFG1_ROMBANKSZ_SHIFT )
0128 #define FTMCTRL_MCFG1_ROMBANKSZ_SET( _reg, _val ) \
0129   ( ( ( _reg ) & ~FTMCTRL_MCFG1_ROMBANKSZ_MASK ) | \
0130     ( ( ( _val ) << FTMCTRL_MCFG1_ROMBANKSZ_SHIFT ) & \
0131       FTMCTRL_MCFG1_ROMBANKSZ_MASK ) )
0132 #define FTMCTRL_MCFG1_ROMBANKSZ( _val ) \
0133   ( ( ( _val ) << FTMCTRL_MCFG1_ROMBANKSZ_SHIFT ) & \
0134     FTMCTRL_MCFG1_ROMBANKSZ_MASK )
0135
0136 #define FTMCTRL_MCFG1_PWEN 0x800U
0137
0138 #define FTMCTRL_MCFG1_PROM_WIDTH_SHIFT 8
0139 #define FTMCTRL_MCFG1_PROM_WIDTH_MASK 0x300U
0140 #define FTMCTRL_MCFG1_PROM_WIDTH_GET( _reg ) \
0141   ( ( ( _reg ) & FTMCTRL_MCFG1_PROM_WIDTH_MASK ) >> \
0142     FTMCTRL_MCFG1_PROM_WIDTH_SHIFT )
0143 #define FTMCTRL_MCFG1_PROM_WIDTH_SET( _reg, _val ) \
0144   ( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_WIDTH_MASK ) | \
0145     ( ( ( _val ) << FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) & \
0146       FTMCTRL_MCFG1_PROM_WIDTH_MASK ) )
0147 #define FTMCTRL_MCFG1_PROM_WIDTH( _val ) \
0148   ( ( ( _val ) << FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) & \
0149     FTMCTRL_MCFG1_PROM_WIDTH_MASK )
0150
0151 #define FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT 4
0152 #define FTMCTRL_MCFG1_PROM_WRITE_WS_MASK 0xf0U
0153 #define FTMCTRL_MCFG1_PROM_WRITE_WS_GET( _reg ) \
0154   ( ( ( _reg ) & FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) >> \
0155     FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT )
0156 #define FTMCTRL_MCFG1_PROM_WRITE_WS_SET( _reg, _val ) \
0157   ( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) | \
0158     ( ( ( _val ) << FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT ) & \
0159       FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) )
0160 #define FTMCTRL_MCFG1_PROM_WRITE_WS( _val ) \
0161   ( ( ( _val ) << FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT ) & \
0162     FTMCTRL_MCFG1_PROM_WRITE_WS_MASK )
0163
0164 #define FTMCTRL_MCFG1_PROM_READ_WS_SHIFT 0
0165 #define FTMCTRL_MCFG1_PROM_READ_WS_MASK 0xfU
0166 #define FTMCTRL_MCFG1_PROM_READ_WS_GET( _reg ) \
0167   ( ( ( _reg ) & FTMCTRL_MCFG1_PROM_READ_WS_MASK ) >> \
0168     FTMCTRL_MCFG1_PROM_READ_WS_SHIFT )
0169 #define FTMCTRL_MCFG1_PROM_READ_WS_SET( _reg, _val ) \
0170   ( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_READ_WS_MASK ) | \
0171     ( ( ( _val ) << FTMCTRL_MCFG1_PROM_READ_WS_SHIFT ) & \
0172       FTMCTRL_MCFG1_PROM_READ_WS_MASK ) )
0173 #define FTMCTRL_MCFG1_PROM_READ_WS( _val ) \
0174   ( ( ( _val ) << FTMCTRL_MCFG1_PROM_READ_WS_SHIFT ) & \
0175     FTMCTRL_MCFG1_PROM_READ_WS_MASK )
0176
0177 /** @} */
0178
0179 /**
0180  * @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG3 \
0181  *   Memory configuration register 3 (MCFG3)
0182  *
0183  * @brief This group contains register bit definitions.
0184  *
0185  * @{
0186  */
0187
0188 #define FTMCTRL_MCFG3_ME 0x8000000U
0189
0190 #define FTMCTRL_MCFG3_WB 0x800U
0191
0192 #define FTMCTRL_MCFG3_RB 0x400U
0193
0194 #define FTMCTRL_MCFG3_PE 0x100U
0195
0196 #define FTMCTRL_MCFG3_TCB_SHIFT 0
0197 #define FTMCTRL_MCFG3_TCB_MASK 0xffU
0198 #define FTMCTRL_MCFG3_TCB_GET( _reg ) \
0199   ( ( ( _reg ) & FTMCTRL_MCFG3_TCB_MASK ) >> \
0200     FTMCTRL_MCFG3_TCB_SHIFT )
0201 #define FTMCTRL_MCFG3_TCB_SET( _reg, _val ) \
0202   ( ( ( _reg ) & ~FTMCTRL_MCFG3_TCB_MASK ) | \
0203     ( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & \
0204       FTMCTRL_MCFG3_TCB_MASK ) )
0205 #define FTMCTRL_MCFG3_TCB( _val ) \
0206   ( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & \
0207     FTMCTRL_MCFG3_TCB_MASK )
0208
0209 /** @} */
0210
0211 /**
0212  * @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG5 \
0213  *   Memory configuration register 5 (MCFG5)
0214  *
0215  * @brief This group contains register bit definitions.
0216  *
0217  * @{
0218  */
0219
0220 #define FTMCTRL_MCFG5_IOHWS_SHIFT 23
0221 #define FTMCTRL_MCFG5_IOHWS_MASK 0x3f800000U
0222 #define FTMCTRL_MCFG5_IOHWS_GET( _reg ) \
0223   ( ( ( _reg ) & FTMCTRL_MCFG5_IOHWS_MASK ) >> \
0224     FTMCTRL_MCFG5_IOHWS_SHIFT )
0225 #define FTMCTRL_MCFG5_IOHWS_SET( _reg, _val ) \
0226   ( ( ( _reg ) & ~FTMCTRL_MCFG5_IOHWS_MASK ) | \
0227     ( ( ( _val ) << FTMCTRL_MCFG5_IOHWS_SHIFT ) & \
0228       FTMCTRL_MCFG5_IOHWS_MASK ) )
0229 #define FTMCTRL_MCFG5_IOHWS( _val ) \
0230   ( ( ( _val ) << FTMCTRL_MCFG5_IOHWS_SHIFT ) & \
0231     FTMCTRL_MCFG5_IOHWS_MASK )
0232
0233 #define FTMCTRL_MCFG5_ROMHWS_SHIFT 7
0234 #define FTMCTRL_MCFG5_ROMHWS_MASK 0x3f80U
0235 #define FTMCTRL_MCFG5_ROMHWS_GET( _reg ) \
0236   ( ( ( _reg ) & FTMCTRL_MCFG5_ROMHWS_MASK ) >> \
0237     FTMCTRL_MCFG5_ROMHWS_SHIFT )
0238 #define FTMCTRL_MCFG5_ROMHWS_SET( _reg, _val ) \
0239   ( ( ( _reg ) & ~FTMCTRL_MCFG5_ROMHWS_MASK ) | \
0240     ( ( ( _val ) << FTMCTRL_MCFG5_ROMHWS_SHIFT ) & \
0241       FTMCTRL_MCFG5_ROMHWS_MASK ) )
0242 #define FTMCTRL_MCFG5_ROMHWS( _val ) \
0243   ( ( ( _val ) << FTMCTRL_MCFG5_ROMHWS_SHIFT ) & \
0244     FTMCTRL_MCFG5_ROMHWS_MASK )
0245
0246 /** @} */
0247
0248 /**
0249  * @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG7 \
0250  *   Memory configuration register 7 (MCFG7)
0251  *
0252  * @brief This group contains register bit definitions.
0253  *
0254  * @{
0255  */
0256
0257 #define FTMCTRL_MCFG7_BRDYNCNT_SHIFT 16
0258 #define FTMCTRL_MCFG7_BRDYNCNT_MASK 0xffff0000U
0259 #define FTMCTRL_MCFG7_BRDYNCNT_GET( _reg ) \
0260   ( ( ( _reg ) & FTMCTRL_MCFG7_BRDYNCNT_MASK ) >> \
0261     FTMCTRL_MCFG7_BRDYNCNT_SHIFT )
0262 #define FTMCTRL_MCFG7_BRDYNCNT_SET( _reg, _val ) \
0263   ( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNCNT_MASK ) | \
0264     ( ( ( _val ) << FTMCTRL_MCFG7_BRDYNCNT_SHIFT ) & \
0265       FTMCTRL_MCFG7_BRDYNCNT_MASK ) )
0266 #define FTMCTRL_MCFG7_BRDYNCNT( _val ) \
0267   ( ( ( _val ) << FTMCTRL_MCFG7_BRDYNCNT_SHIFT ) & \
0268     FTMCTRL_MCFG7_BRDYNCNT_MASK )
0269
0270 #define FTMCTRL_MCFG7_BRDYNRLD_SHIFT 0
0271 #define FTMCTRL_MCFG7_BRDYNRLD_MASK 0xffffU
0272 #define FTMCTRL_MCFG7_BRDYNRLD_GET( _reg ) \
0273   ( ( ( _reg ) & FTMCTRL_MCFG7_BRDYNRLD_MASK ) >> \
0274     FTMCTRL_MCFG7_BRDYNRLD_SHIFT )
0275 #define FTMCTRL_MCFG7_BRDYNRLD_SET( _reg, _val ) \
0276   ( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNRLD_MASK ) | \
0277     ( ( ( _val ) << FTMCTRL_MCFG7_BRDYNRLD_SHIFT ) & \
0278       FTMCTRL_MCFG7_BRDYNRLD_MASK ) )
0279 #define FTMCTRL_MCFG7_BRDYNRLD( _val ) \
0280   ( ( ( _val ) << FTMCTRL_MCFG7_BRDYNRLD_SHIFT ) & \
0281     FTMCTRL_MCFG7_BRDYNRLD_MASK )
0282
0283 /** @} */
0284
0285 /**
0286  * @brief This structure defines the FTMCTRL register block memory map.
0287  */
0288 typedef struct ftmctrl {
0289   /**
0290    * @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG1.
0291    */
0292   uint32_t mcfg1;
0293
0294   uint32_t reserved_4_8;
0295
0296   /**
0297    * @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG3.
0298    */
0299   uint32_t mcfg3;
0300
0301   uint32_t reserved_c_10;
0302
0303   /**
0304    * @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG5.
0305    */
0306   uint32_t mcfg5;
0307
0308   uint32_t reserved_14_18;
0309
0310   /**
0311    * @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG7.
0312    */
0313   uint32_t mcfg7;
0314 } ftmctrl;
0315
0316 /** @} */
0317
0318 #ifdef __cplusplus
0319 }
0320 #endif
0321
0322 #endif /* _GRLIB_FTMCTRL_REGS_H */