include/grlib/ahbtrace-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceGRLIBAHBTRACE
0007  *
0008  * @brief This header file defines the AHBTRACE register block interface.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /*
0037  * This file is part of the RTEMS quality process and was automatically
0038  * generated.  If you find something that needs to be fixed or
0039  * worded better please post a report or patch to an RTEMS mailing list
0040  * or raise a bug report:
0041  *
0042  * https://www.rtems.org/bugs.html
0043  *
0044  * For information on updating and regenerating please refer to the How-To
0045  * section in the Software Requirements Engineering chapter of the
0046  * RTEMS Software Engineering manual.  The manual is provided as a part of
0047  * a release.  For development sources please refer to the online
0048  * documentation at:
0049  *
0050  * https://docs.rtems.org
0051  */
0052
0053 /* Generated from spec:/dev/grlib/if/ahbtrace-header */
0054
0055 #ifndef _GRLIB_AHBTRACE_REGS_H
0056 #define _GRLIB_AHBTRACE_REGS_H
0057
0058 #include <stdint.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif
0063
0064 /* Generated from spec:/dev/grlib/if/ahbtrace */
0065
0066 /**
0067  * @defgroup RTEMSDeviceGRLIBAHBTRACE AHBTRACE
0068  *
0069  * @ingroup RTEMSDeviceGRLIB
0070  *
0071  * @brief This group contains the AHBTRACE interfaces.
0072  *
0073  * @{
0074  */
0075
0076 /**
0077  * @defgroup RTEMSDeviceGRLIBAHBTRACECTRL Trace buffer control register (CTRL)
0078  *
0079  * @brief This group contains register bit definitions.
0080  *
0081  * @{
0082  */
0083
0084 #define AHBTRACE_CTRL_DCNT_SHIFT 16
0085 #define AHBTRACE_CTRL_DCNT_MASK 0x7f0000U
0086 #define AHBTRACE_CTRL_DCNT_GET( _reg ) \
0087   ( ( ( _reg ) & AHBTRACE_CTRL_DCNT_MASK ) >> \
0088     AHBTRACE_CTRL_DCNT_SHIFT )
0089 #define AHBTRACE_CTRL_DCNT_SET( _reg, _val ) \
0090   ( ( ( _reg ) & ~AHBTRACE_CTRL_DCNT_MASK ) | \
0091     ( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & \
0092       AHBTRACE_CTRL_DCNT_MASK ) )
0093 #define AHBTRACE_CTRL_DCNT( _val ) \
0094   ( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & \
0095     AHBTRACE_CTRL_DCNT_MASK )
0096
0097 #define AHBTRACE_CTRL_PF 0x100U
0098
0099 #define AHBTRACE_CTRL_BW_SHIFT 6
0100 #define AHBTRACE_CTRL_BW_MASK 0xc0U
0101 #define AHBTRACE_CTRL_BW_GET( _reg ) \
0102   ( ( ( _reg ) & AHBTRACE_CTRL_BW_MASK ) >> \
0103     AHBTRACE_CTRL_BW_SHIFT )
0104 #define AHBTRACE_CTRL_BW_SET( _reg, _val ) \
0105   ( ( ( _reg ) & ~AHBTRACE_CTRL_BW_MASK ) | \
0106     ( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & \
0107       AHBTRACE_CTRL_BW_MASK ) )
0108 #define AHBTRACE_CTRL_BW( _val ) \
0109   ( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & \
0110     AHBTRACE_CTRL_BW_MASK )
0111
0112 #define AHBTRACE_CTRL_RF 0x20U
0113
0114 #define AHBTRACE_CTRL_AF 0x10U
0115
0116 #define AHBTRACE_CTRL_FR 0x8U
0117
0118 #define AHBTRACE_CTRL_FW 0x4U
0119
0120 #define AHBTRACE_CTRL_DM 0x2U
0121
0122 #define AHBTRACE_CTRL_EN 0x1U
0123
0124 /** @} */
0125
0126 /**
0127  * @defgroup RTEMSDeviceGRLIBAHBTRACEINDEX Trace buffer index register (INDEX)
0128  *
0129  * @brief This group contains register bit definitions.
0130  *
0131  * @{
0132  */
0133
0134 #define AHBTRACE_INDEX_INDEX_SHIFT 4
0135 #define AHBTRACE_INDEX_INDEX_MASK 0x7f0U
0136 #define AHBTRACE_INDEX_INDEX_GET( _reg ) \
0137   ( ( ( _reg ) & AHBTRACE_INDEX_INDEX_MASK ) >> \
0138     AHBTRACE_INDEX_INDEX_SHIFT )
0139 #define AHBTRACE_INDEX_INDEX_SET( _reg, _val ) \
0140   ( ( ( _reg ) & ~AHBTRACE_INDEX_INDEX_MASK ) | \
0141     ( ( ( _val ) << AHBTRACE_INDEX_INDEX_SHIFT ) & \
0142       AHBTRACE_INDEX_INDEX_MASK ) )
0143 #define AHBTRACE_INDEX_INDEX( _val ) \
0144   ( ( ( _val ) << AHBTRACE_INDEX_INDEX_SHIFT ) & \
0145     AHBTRACE_INDEX_INDEX_MASK )
0146
0147 /** @} */
0148
0149 /**
0150  * @defgroup RTEMSDeviceGRLIBAHBTRACETIMETAG \
0151  *   Trace buffer time tag register (TIMETAG)
0152  *
0153  * @brief This group contains register bit definitions.
0154  *
0155  * @{
0156  */
0157
0158 #define AHBTRACE_TIMETAG_TIMETAG_SHIFT 0
0159 #define AHBTRACE_TIMETAG_TIMETAG_MASK 0xffffffffU
0160 #define AHBTRACE_TIMETAG_TIMETAG_GET( _reg ) \
0161   ( ( ( _reg ) & AHBTRACE_TIMETAG_TIMETAG_MASK ) >> \
0162     AHBTRACE_TIMETAG_TIMETAG_SHIFT )
0163 #define AHBTRACE_TIMETAG_TIMETAG_SET( _reg, _val ) \
0164   ( ( ( _reg ) & ~AHBTRACE_TIMETAG_TIMETAG_MASK ) | \
0165     ( ( ( _val ) << AHBTRACE_TIMETAG_TIMETAG_SHIFT ) & \
0166       AHBTRACE_TIMETAG_TIMETAG_MASK ) )
0167 #define AHBTRACE_TIMETAG_TIMETAG( _val ) \
0168   ( ( ( _val ) << AHBTRACE_TIMETAG_TIMETAG_SHIFT ) & \
0169     AHBTRACE_TIMETAG_TIMETAG_MASK )
0170
0171 /** @} */
0172
0173 /**
0174  * @defgroup RTEMSDeviceGRLIBAHBTRACEMSFILT \
0175  *   Trace buffer master/slave filter register (MSFILT)
0176  *
0177  * @brief This group contains register bit definitions.
0178  *
0179  * @{
0180  */
0181
0182 #define AHBTRACE_MSFILT_SMASK_15_0_SHIFT 16
0183 #define AHBTRACE_MSFILT_SMASK_15_0_MASK 0xffff0000U
0184 #define AHBTRACE_MSFILT_SMASK_15_0_GET( _reg ) \
0185   ( ( ( _reg ) & AHBTRACE_MSFILT_SMASK_15_0_MASK ) >> \
0186     AHBTRACE_MSFILT_SMASK_15_0_SHIFT )
0187 #define AHBTRACE_MSFILT_SMASK_15_0_SET( _reg, _val ) \
0188   ( ( ( _reg ) & ~AHBTRACE_MSFILT_SMASK_15_0_MASK ) | \
0189     ( ( ( _val ) << AHBTRACE_MSFILT_SMASK_15_0_SHIFT ) & \
0190       AHBTRACE_MSFILT_SMASK_15_0_MASK ) )
0191 #define AHBTRACE_MSFILT_SMASK_15_0( _val ) \
0192   ( ( ( _val ) << AHBTRACE_MSFILT_SMASK_15_0_SHIFT ) & \
0193     AHBTRACE_MSFILT_SMASK_15_0_MASK )
0194
0195 #define AHBTRACE_MSFILT_MMASK_15_0_SHIFT 0
0196 #define AHBTRACE_MSFILT_MMASK_15_0_MASK 0xffffU
0197 #define AHBTRACE_MSFILT_MMASK_15_0_GET( _reg ) \
0198   ( ( ( _reg ) & AHBTRACE_MSFILT_MMASK_15_0_MASK ) >> \
0199     AHBTRACE_MSFILT_MMASK_15_0_SHIFT )
0200 #define AHBTRACE_MSFILT_MMASK_15_0_SET( _reg, _val ) \
0201   ( ( ( _reg ) & ~AHBTRACE_MSFILT_MMASK_15_0_MASK ) | \
0202     ( ( ( _val ) << AHBTRACE_MSFILT_MMASK_15_0_SHIFT ) & \
0203       AHBTRACE_MSFILT_MMASK_15_0_MASK ) )
0204 #define AHBTRACE_MSFILT_MMASK_15_0( _val ) \
0205   ( ( ( _val ) << AHBTRACE_MSFILT_MMASK_15_0_SHIFT ) & \
0206     AHBTRACE_MSFILT_MMASK_15_0_MASK )
0207
0208 /** @} */
0209
0210 /**
0211  * @defgroup RTEMSDeviceGRLIBAHBTRACETBBA \
0212  *   Trace buffer break address registers (TBBA)
0213  *
0214  * @brief This group contains register bit definitions.
0215  *
0216  * @{
0217  */
0218
0219 #define AHBTRACE_TBBA_BADDR_31_2_SHIFT 2
0220 #define AHBTRACE_TBBA_BADDR_31_2_MASK 0xfffffffcU
0221 #define AHBTRACE_TBBA_BADDR_31_2_GET( _reg ) \
0222   ( ( ( _reg ) & AHBTRACE_TBBA_BADDR_31_2_MASK ) >> \
0223     AHBTRACE_TBBA_BADDR_31_2_SHIFT )
0224 #define AHBTRACE_TBBA_BADDR_31_2_SET( _reg, _val ) \
0225   ( ( ( _reg ) & ~AHBTRACE_TBBA_BADDR_31_2_MASK ) | \
0226     ( ( ( _val ) << AHBTRACE_TBBA_BADDR_31_2_SHIFT ) & \
0227       AHBTRACE_TBBA_BADDR_31_2_MASK ) )
0228 #define AHBTRACE_TBBA_BADDR_31_2( _val ) \
0229   ( ( ( _val ) << AHBTRACE_TBBA_BADDR_31_2_SHIFT ) & \
0230     AHBTRACE_TBBA_BADDR_31_2_MASK )
0231
0232 /** @} */
0233
0234 /**
0235  * @defgroup RTEMSDeviceGRLIBAHBTRACETBBM \
0236  *   Trace buffer break mask registers (TBBM)
0237  *
0238  * @brief This group contains register bit definitions.
0239  *
0240  * @{
0241  */
0242
0243 #define AHBTRACE_TBBM_BMASK_31_2_SHIFT 2
0244 #define AHBTRACE_TBBM_BMASK_31_2_MASK 0xfffffffcU
0245 #define AHBTRACE_TBBM_BMASK_31_2_GET( _reg ) \
0246   ( ( ( _reg ) & AHBTRACE_TBBM_BMASK_31_2_MASK ) >> \
0247     AHBTRACE_TBBM_BMASK_31_2_SHIFT )
0248 #define AHBTRACE_TBBM_BMASK_31_2_SET( _reg, _val ) \
0249   ( ( ( _reg ) & ~AHBTRACE_TBBM_BMASK_31_2_MASK ) | \
0250     ( ( ( _val ) << AHBTRACE_TBBM_BMASK_31_2_SHIFT ) & \
0251       AHBTRACE_TBBM_BMASK_31_2_MASK ) )
0252 #define AHBTRACE_TBBM_BMASK_31_2( _val ) \
0253   ( ( ( _val ) << AHBTRACE_TBBM_BMASK_31_2_SHIFT ) & \
0254     AHBTRACE_TBBM_BMASK_31_2_MASK )
0255
0256 #define AHBTRACE_TBBM_LD 0x2U
0257
0258 #define AHBTRACE_TBBM_ST 0x1U
0259
0260 /** @} */
0261
0262 /**
0263  * @brief This structure defines the AHBTRACE register block memory map.
0264  */
0265 typedef struct ahbtrace {
0266   /**
0267    * @brief See @ref RTEMSDeviceGRLIBAHBTRACECTRL.
0268    */
0269   uint32_t ctrl;
0270
0271   /**
0272    * @brief See @ref RTEMSDeviceGRLIBAHBTRACEINDEX.
0273    */
0274   uint32_t index;
0275
0276   /**
0277    * @brief See @ref RTEMSDeviceGRLIBAHBTRACETIMETAG.
0278    */
0279   uint32_t timetag;
0280
0281   /**
0282    * @brief See @ref RTEMSDeviceGRLIBAHBTRACEMSFILT.
0283    */
0284   uint32_t msfilt;
0285
0286   /**
0287    * @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBA.
0288    */
0289   uint32_t tbba_0;
0290
0291   /**
0292    * @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBM.
0293    */
0294   uint32_t tbbm_0;
0295
0296   /**
0297    * @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBA.
0298    */
0299   uint32_t tbba_1;
0300
0301   /**
0302    * @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBM.
0303    */
0304   uint32_t tbbm_1;
0305 } ahbtrace;
0306
0307 /** @} */
0308
0309 #ifdef __cplusplus
0310 }
0311 #endif
0312
0313 #endif /* _GRLIB_AHBTRACE_REGS_H */