dev/spi/xqspipsu_flash_config.h

0001 /******************************************************************************
0002 * Copyright (C) 2020 - 2022 Xilinx, Inc.  All rights reserved.
0003 * SPDX-License-Identifier: MIT
0004 ******************************************************************************/
0005 /*****************************************************************************/
0006 /**
0007 *
0008 * @file xqspipsu_flash_config.h
0009 *
0010 *
0011 * This file contains flash configuration table and flash related defines.
0012 * This file should be included in the example files and compiled along with
0013 * the examples (*.c).
0014 *
0015 * @note
0016 *
0017 * None.
0018 *
0019 * <pre>
0020 * MODIFICATION HISTORY:
0021 *
0022 * Ver   Who Date     Changes
0023 * ----- --- -------- -----------------------------------------------
0024 * 1.12  akm 07/07/20 First release
0025 * 1.12  akm 07/07/20 Add support for Macronix flash(MX66U2G45G, MX66L2G45G)
0026 *                    and ISSI flash(IS25LP01G, IS25WP01G) parts.
0027 * 1.13  akm 12/10/20 Set Read command as per the qspi bus width.
0028 * 1.14  akm 07/16/21 Enable Quad Mode for Winbond flashes.
0029 * 1.15  akm 11/19/21 Fix read/write failures on Spansion flash parts.
0030 *
0031 *</pre>
0032 *
0033  ******************************************************************************/
0034
0035 #ifndef XQSPIPSU_FLASH_CONFIG_H_        /* prevent circular inclusions */
0036 #define XQSPIPSU_FLASH_CONFIG_H_        /* by using protection macros */
0037
0038 #ifdef __cplusplus
0039 extern "C" {
0040 #endif
0041
0042 /***************************** Include Files *********************************/
0043
0044 #ifndef __rtems__
0045 #include "xparameters.h"    /* SDK generated parameters */
0046 #else
0047 #include <bsp/xil-compat.h>
0048 #endif
0049 #include "xqspipsu.h"       /* QSPIPSU device driver */
0050
0051 /************************** Constant Definitions *****************************/
0052
0053 /*
0054  * The following constants define the commands which may be sent to the Flash
0055  * device.
0056  */
0057 #define WRITE_STATUS_CMD    0x01
0058 #define WRITE_CMD       0x02
0059 #define READ_CMD        0x03
0060 #define WRITE_DISABLE_CMD   0x04
0061 #define READ_STATUS_CMD     0x05
0062 #define WRITE_ENABLE_CMD    0x06
0063 #define VOLATILE_WRITE_ENABLE_CMD   0x50
0064 #define QUAD_MODE_ENABLE_BIT    0x06
0065 #define FAST_READ_CMD       0x0B
0066 #define DUAL_READ_CMD       0x3B
0067 #define QUAD_READ_CMD       0x6B
0068 #define BULK_ERASE_CMD      0xC7
0069 #define SEC_ERASE_CMD       0xD8
0070 #define READ_ID         0x9F
0071 #define READ_SFDP       0x5A
0072 #define READ_CONFIG_CMD     0x35
0073 #define WRITE_CONFIG_CMD    0x01
0074 #define ENTER_4B_ADDR_MODE  0xB7
0075 #define EXIT_4B_ADDR_MODE   0xE9
0076 #define EXIT_4B_ADDR_MODE_ISSI  0x29
0077 /* 4-byte address opcodes */
0078 #define READ_CMD_4B         0x13
0079 #define FAST_READ_CMD_4B        0x0C
0080 #define DUAL_READ_CMD_4B        0x3C
0081 #define QUAD_READ_CMD_4B        0x6C
0082 #define WRITE_CMD_4B            0x12
0083 #define SEC_ERASE_CMD_4B        0xDC
0084
0085 #define BANK_REG_RD     0x16
0086 #define BANK_REG_WR     0x17
0087 #define READ_ECCSR      0x18
0088 /* Bank register is called Extended Address Register in Micron */
0089 #define EXTADD_REG_RD       0xC8
0090 #define EXTADD_REG_WR       0xC5
0091 #define DIE_ERASE_CMD       0xC4
0092 #define READ_FLAG_STATUS_CMD    0x70
0093
0094 #define WRITE_STATUS_REG_2_CMD  0x31
0095 #define READ_STATUS_REG_2_CMD   0x35
0096 #define WB_QUAD_MODE_ENABLE_BIT 0x01
0097
0098 /*
0099  * The following constants define the offsets within a FlashBuffer data
0100  * type for each kind of data.  Note that the read data offset is not the
0101  * same as the write data because the QSPIPSU driver is designed to allow full
0102  * duplex transfers such that the number of bytes received is the number
0103  * sent and received.
0104  */
0105 #define COMMAND_OFFSET      0 /* Flash instruction */
0106 #define ADDRESS_1_OFFSET    1 /* MSB byte of address to read or write */
0107 #define ADDRESS_2_OFFSET    2 /* Middle byte of address to read or write */
0108 #define ADDRESS_3_OFFSET    3 /* LSB byte of address to read or write */
0109 #define ADDRESS_4_OFFSET    4 /* LSB byte of address to read or write
0110                    * when 4 byte address
0111                    */
0112 #define DATA_OFFSET     5 /* Start of Data for Read/Write */
0113 #define DUMMY_OFFSET        4 /* Dummy byte offset for fast, dual and quad
0114                    * reads
0115                    */
0116 #define DUMMY_SIZE      1 /* Number of dummy bytes for fast, dual and
0117                    * quad reads
0118                    */
0119 #define DUMMY_CLOCKS        8 /* Number of dummy bytes for fast, dual and
0120                    * quad reads
0121                    */
0122 #define RD_ID_SIZE      4 /* Read ID command + 3 bytes ID response */
0123 #define BULK_ERASE_SIZE     1 /* Bulk Erase command size */
0124 #define SEC_ERASE_SIZE      4 /* Sector Erase command + Sector address */
0125 #define BANK_SEL_SIZE       2 /* BRWR or EARWR command + 1 byte bank
0126                    * value
0127                    */
0128 #define RD_CFG_SIZE     2 /* 1 byte Configuration register + RD CFG
0129                    * command
0130                    */
0131 #define WR_CFG_SIZE     3 /* WRR command + 1 byte each Status and
0132                    * Config Reg
0133                    */
0134 #define DIE_ERASE_SIZE  4   /* Die Erase command + Die address */
0135
0136 /*
0137  * The following constants specify the extra bytes which are sent to the
0138  * Flash on the QSPIPSu interface, that are not data, but control information
0139  * which includes the command and address
0140  */
0141 #define OVERHEAD_SIZE       4
0142
0143 /*
0144  * Base address of Flash1
0145  */
0146 #define FLASH1BASE 0x0000000
0147
0148 /*
0149  * Sixteen MB
0150  */
0151 #define SIXTEENMB 0x1000000
0152
0153
0154 /*
0155  * Mask for quad enable bit in Flash configuration register
0156  */
0157 #define FLASH_QUAD_EN_MASK 0x02
0158
0159 #define FLASH_SRWD_MASK 0x80
0160
0161 /*
0162  * Bank mask
0163  */
0164 #define BANKMASK 0xF000000
0165
0166 /*
0167  * Bus width
0168  */
0169 #define BUSWIDTH_SINGLE 0
0170 #define BUSWIDTH_DOUBLE 1
0171
0172 /*
0173  * Identification of Flash
0174  * Micron:
0175  * Byte 0 is Manufacturer ID;
0176  * Byte 1 is first byte of Device ID - 0xBB or 0xBA
0177  * Byte 2 is second byte of Device ID describes flash size:
0178  * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
0179  * Spansion:
0180  * Byte 0 is Manufacturer ID;
0181  * Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02
0182  * Byte 2 is second byte of Device ID describes flash size:
0183  * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
0184  */
0185 #define MICRON_ID_BYTE0     0x20
0186 #define SPANSION_ID_BYTE0   0x01
0187 #define WINBOND_ID_BYTE0    0xEF
0188 #define MACRONIX_ID_BYTE0   0xC2
0189 #define ISSI_ID_BYTE0       0x9D
0190
0191 /**************************** Type Definitions *******************************/
0192
0193 typedef struct{
0194     u32 jedec_id;   /* JEDEC ID */
0195
0196     u32 SectSize;       /* Individual sector size or combined sector
0197                  * size in case of parallel config
0198                  */
0199     u32 NumSect;        /* Total no. of sectors in one/two
0200                  * flash devices
0201                  */
0202     u32 PageSize;       /* Individual page size or
0203                  * combined page size in case of parallel
0204                  * config
0205                  */
0206     u32 NumPage;        /* Total no. of pages in one/two flash
0207                  * devices
0208                  */
0209     u32 FlashDeviceSize;    /* This is the size of one flash device
0210                  * NOT the combination of both devices,
0211                  * if present
0212                  */
0213     u32 SectMask;       /* Mask to get sector start address */
0214     u8 NumDie;      /* No. of die forming a single flash */
0215 } FlashInfo;
0216
0217 /************************** Variable Definitions *****************************/
0218 FlashInfo Flash_Config_Table[] = {
0219     /* Spansion */
0220     /*s25fl064l*/
0221     {0x016017, SECTOR_SIZE_64K, NUM_OF_SECTORS128, BYTES256_PER_PAGE,
0222         0x8000, 0x800000, 0xFFFF0000, 1},
0223     /*s25fl128l*/
0224     {0x016018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE,
0225         0x10000, 0x1000000, 0xFFFF0000, 1},
0226     /*s25fl256l*/
0227     {0x016019, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE,
0228         0x20000, 0x2000000, 0xFFFF0000, 1},
0229     /*s25fl512s*/
0230     {0x010220, SECTOR_SIZE_256K, NUM_OF_SECTORS256, BYTES512_PER_PAGE,
0231         0x20000, 0x4000000, 0xFFFC0000, 1},
0232     /* Spansion 1Gbit is handled as 512Mbit stacked */
0233     /* Micron */
0234     /*n25q128a11*/
0235     {0x20bb18, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE,
0236         0x10000, 0x1000000, 0xFFFF0000, 1},
0237     /*n25q128a13*/
0238     {0x20ba18, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE,
0239         0x10000, 0x1000000, 0xFFFF0000, 1},
0240     /*n25q256ax1*/
0241     {0x20bb19, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE,
0242         0x20000, 0x2000000, 0xFFFF0000, 1},
0243     /*n25q256a*/
0244     {0x20ba19, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE,
0245         0x20000, 0x2000000, 0xFFFF0000, 1},
0246     /*mt25qu512a*/
0247     {0x20bb20, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE,
0248         0x40000, 0x4000000, 0xFFFF0000, 2},
0249     /*n25q512ax3*/
0250     {0x20ba20, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE,
0251         0x40000, 0x4000000, 0xFFFF0000, 2},
0252     /*n25q00a*/
0253     {0x20bb21, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE,
0254         0x80000, 0x8000000, 0xFFFF0000, 4},
0255     /*n25q00*/
0256     {0x20ba21, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE,
0257         0x80000, 0x8000000, 0xFFFF0000, 4},
0258     /*mt25qu02g*/
0259     {0x20bb22, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE,
0260         0x100000, 0x10000000, 0xFFFF0000, 4},
0261     /*mt25ql02g*/
0262     {0x20ba22, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE,
0263         0x100000, 0x10000000, 0xFFFF0000, 4},
0264     /* Winbond */
0265     /*w25q128fw*/
0266     {0xef6018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE,
0267         0x10000, 0x1000000, 0xFFFF0000, 1},
0268     /*w25q128jv*/
0269     {0xef7018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE,
0270         0x10000, 0x1000000, 0xFFFF0000, 1},
0271     /*w25h02jv*/
0272     {0xef9022, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE,
0273         0x100000, 0x10000000, 0xFFFF0000, 4},
0274     /* Macronix */
0275     /*mx66l1g45g*/
0276     {0xc2201b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE,
0277         0x80000, 0x8000000, 0xFFFF0000, 4},
0278     /*mx66l1g55g*/
0279     {0xc2261b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE,
0280         0x80000, 0x8000000, 0xFFFF0000, 4},
0281     /*mx66u1g45g*/
0282     {0xc2253b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE,
0283         0x80000, 0x8000000, 0xFFFF0000, 4},
0284     /*mx66l2g45g*/
0285     {0xc2201c, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE,
0286         0x100000, 0x10000000, 0xFFFF0000, 1},
0287     /*mx66u2g45g*/
0288     {0xc2253c, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE,
0289         0x100000, 0x10000000, 0xFFFF0000, 1},
0290     /* ISSI */
0291     /*is25wp080d*/
0292     {0x9d7014, SECTOR_SIZE_64K, NUM_OF_SECTORS16, BYTES256_PER_PAGE,
0293         0x1000, 0x100000, 0xFFFF0000, 1},
0294     /*is25lp080d*/
0295     {0x9d6014, SECTOR_SIZE_64K, NUM_OF_SECTORS16, BYTES256_PER_PAGE,
0296         0x1000, 0x100000, 0xFFFF0000, 1},
0297     /*is25wp016d*/
0298     {0x9d7015, SECTOR_SIZE_64K, NUM_OF_SECTORS32, BYTES256_PER_PAGE,
0299         0x2000, 0x200000, 0xFFFF0000, 1},
0300     /*is25lp016d*/
0301     {0x9d6015, SECTOR_SIZE_64K, NUM_OF_SECTORS32, BYTES256_PER_PAGE,
0302         0x2000, 0x200000, 0xFFFF0000, 1},
0303     /*is25wp032*/
0304     {0x9d7016, SECTOR_SIZE_64K, NUM_OF_SECTORS64, BYTES256_PER_PAGE,
0305         0x4000, 0x400000, 0xFFFF0000, 1},
0306     /*is25lp032*/
0307     {0x9d6016, SECTOR_SIZE_64K, NUM_OF_SECTORS64, BYTES256_PER_PAGE,
0308         0x4000, 0x400000, 0xFFFF0000, 1},
0309     /*is25wp064*/
0310     {0x9d7017, SECTOR_SIZE_64K, NUM_OF_SECTORS128, BYTES256_PER_PAGE,
0311         0x8000, 0x800000, 0xFFFF0000, 1},
0312     /*is25lp064*/
0313     {0x9d6017, SECTOR_SIZE_64K, NUM_OF_SECTORS128, BYTES256_PER_PAGE,
0314         0x8000, 0x800000, 0xFFFF0000, 1},
0315     /*is25wp128*/
0316     {0x9d7018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE,
0317         0x10000, 0x1000000, 0xFFFF0000, 1},
0318     /*is25lp128*/
0319     {0x9d6018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE,
0320         0x10000, 0x1000000, 0xFFFF0000, 1},
0321     /*is25lp256d*/
0322     {0x9d6019, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE,
0323         0x20000, 0x2000000, 0xFFFF0000, 1},
0324     /*is25wp256d*/
0325     {0x9d7019, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE,
0326         0x20000, 0x2000000, 0xFFFF0000, 1},
0327     /*is25lp512m*/
0328     {0x9d601a, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE,
0329         0x40000, 0x4000000, 0xFFFF0000, 2},
0330     /*is25wp512m*/
0331     {0x9d701a, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE,
0332         0x40000, 0x4000000, 0xFFFF0000, 2},
0333     /*is25lp01g*/
0334     {0x9d601b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE,
0335         0x80000, 0x8000000, 0xFFFF0000, 1},
0336     /*is25wp01g*/
0337     {0x9d701b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE,
0338         0x80000, 0x8000000, 0xFFFF0000, 1}
0339 };
0340
0341 static INLINE u32 CalculateFCTIndex(u32 ReadId, u32 *FCTIndex)
0342 {
0343     u32 Index;
0344
0345     for (Index = 0; Index < sizeof(Flash_Config_Table)/sizeof(Flash_Config_Table[0]);
0346                 Index++) {
0347         if (ReadId == Flash_Config_Table[Index].jedec_id) {
0348             *FCTIndex = Index;
0349             return XST_SUCCESS;
0350         }
0351     }
0352
0353     return XST_FAILURE;
0354 }
0355
0356 #ifdef __cplusplus
0357 }
0358 #endif
0359
0360 #endif /* XQSPIPSU_FLASH_CONFIG_H_ */
0361 /** @} */