dev/spi/xqspipsu_control.h

0001 /******************************************************************************
0002 * Copyright (C) 2020 - 2022 Xilinx, Inc.  All rights reserved.
0003 * SPDX-License-Identifier: MIT
0004 ******************************************************************************/
0005
0006
0007 /*****************************************************************************/
0008 /**
0009  *
0010  * @file xqspipsu_control.h
0011  * @addtogroup Overview
0012  * @{
0013  *
0014  * This is the header file for the implementation of QSPIPSU driver.
0015  * Generic QSPI interface allows for communication to any QSPI slave device.
0016  * GQSPI contains a GENFIFO into which the bus transfers required are to be
0017  * pushed with appropriate configuration. The controller provides TX and RX
0018  * FIFO's and a DMA to be used for RX transfers. The controller executes each
0019  * GENFIFO entry noting the configuration and places data on the bus as required
0020  *
0021  *
0022  * <pre>
0023  * MODIFICATION HISTORY:
0024  *
0025  * Ver   Who Date     Changes
0026  * ----- --- -------- -----------------------------------------------.
0027  * 1.11   akm  03/09/20 First release
0028  * 1.13   akm  01/04/21 Fix MISRA-C violations.
0029  * 1.15   akm  03/03/22 Enable tapdelay settings for applications on
0030  *           Microblaze platform.
0031  *
0032  * </pre>
0033  *
0034  ******************************************************************************/
0035
0036 /** @cond INTERNAL */
0037 #ifndef XQSPIPSU_CONTROL_H_     /**< prevent circular inclusions */
0038 #define XQSPIPSU_CONTROL_H_     /**< by using protection macros */
0039
0040 #ifdef __cplusplus
0041 extern "C" {
0042 #endif
0043
0044 /***************************** Include Files *********************************/
0045
0046 #include "xqspipsu.h"
0047
0048 /**************************** Type Definitions *******************************/
0049
0050 /***************** Macros (Inline Functions) Definitions *********************/
0051
0052 #if defined (ARMR5) || defined (__aarch64__) || defined (__MICROBLAZE__)
0053 #define TAPDLY_BYPASS_VALVE_40MHZ 0x01U
0054 #define TAPDLY_BYPASS_VALVE_100MHZ 0x01U
0055 #define USE_DLY_LPBK  0x01U
0056 #define USE_DATA_DLY_ADJ 0x01U
0057 #define DATA_DLY_ADJ_DLY 0X02U
0058 #define LPBK_DLY_ADJ_DLY0 0X02U
0059 #define LPBK_DLY_ADJ_DLY1 0X02U
0060 #endif
0061
0062 #ifdef __MICROBLAZE__
0063 #define XPS_SYS_CTRL_BASEADDR   0xFF180000U     /**< System controller Baseaddress */
0064 #endif
0065 /************************** Function Prototypes ******************************/
0066 void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
0067 u32 XQspiPsu_SetIOMode(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
0068 void XQspiPsu_IORead(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
0069         u32 StatusReg);
0070 void XQspiPsu_PollDataConfig(XQspiPsu *InstancePtr, XQspiPsu_Msg *FlashMsg);
0071 void XQspiPsu_TXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
0072 void XQspiPsu_SetupRxDma(const XQspiPsu *InstancePtr,
0073                     XQspiPsu_Msg *Msg);
0074 void XQspiPsu_Setup64BRxDma(const XQspiPsu *InstancePtr,
0075                     XQspiPsu_Msg *Msg);
0076 void XQspiPsu_RXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
0077 void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
0078                     u32 *GenFifoEntry);
0079 void XQspiPsu_GenFifoEntryDataLen(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
0080         u32 *GenFifoEntry);
0081 u32 XQspiPsu_CreatePollDataConfig(const XQspiPsu *InstancePtr,
0082         const XQspiPsu_Msg *FlashMsg);
0083 void XQspiPsu_PollDataHandler(XQspiPsu *InstancePtr, u32 StatusReg);
0084 u32 XQspiPsu_SelectSpiMode(u8 SpiMode);
0085 void XQspiPsu_SetDefaultConfig(XQspiPsu *InstancePtr);
0086 void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, u32 Size);
0087 void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, s32 Size);
0088
0089 #if defined (ARMR5) || defined (__aarch64__) || defined (__MICROBLAZE__)
0090 s32 XQspipsu_Set_TapDelay(const XQspiPsu *InstancePtr, u32 TapdelayBypass,
0091                         u32 LPBKDelay, u32 Datadelay);
0092 s32 XQspipsu_Calculate_Tapdelay(const XQspiPsu *InstancePtr, u8 Prescaler);
0093 #endif
0094
0095 #ifdef __cplusplus
0096 }
0097 #endif
0098
0099
0100 #endif /* XQSPIPSU_CONTROL_H_ */
0101 /** @endcond */
0102 /** @} */