dev/spi/xilinx-axi-spi-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (C) 2021 Jan Sommer, German Aerospace Center (DLR)
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #ifndef LIBBSP_ARM_XILINX_AXI_SPI_REGS_H
0029 #define LIBBSP_ARM_XILINX_AXI_SPI_REGS_H
0030
0031 #include <bsp/utility.h>
0032
0033 typedef struct {
0034     uint32_t reserved1[7];
0035     uint32_t globalirq;
0036 #define XILINX_AXI_SPI_GLOBAL_IRQ_ENABLE BSP_BIT32(31)
0037     uint32_t irqstatus;
0038     uint32_t reserved2;
0039     uint32_t irqenable;
0040 #define XILINX_AXI_SPI_IRQ_CMD_ERR BSP_BIT32(13)
0041 #define XILINX_AXI_SPI_IRQ_LOOP_ERR BSP_BIT32(12)
0042 #define XILINX_AXI_SPI_IRQ_MSB_ERR BSP_BIT32(11)
0043 #define XILINX_AXI_SPI_IRQ_SLV_ERR BSP_BIT32(10)
0044 #define XILINX_AXI_SPI_IRQ_CPOL_CPHA_ERR BSP_BIT32(9)
0045 #define XILINX_AXI_SPI_IRQ_RXNEMPTY BSP_BIT32(8)
0046 #define XILINX_AXI_SPI_IRQ_CS_MODE BSP_BIT32(7)
0047 #define XILINX_AXI_SPI_IRQ_TXHALF BSP_BIT32(6)
0048 #define XILINX_AXI_SPI_IRQ_RXOVR BSP_BIT32(5)
0049 #define XILINX_AXI_SPI_IRQ_RXFULL BSP_BIT32(4)
0050 #define XILINX_AXI_SPI_IRQ_TXUF BSP_BIT32(3)
0051 #define XILINX_AXI_SPI_IRQ_TXEMPTY BSP_BIT32(2)
0052 #define XILINX_AXI_SPI_IRQ_SLV_MODF BSP_BIT32(1)
0053 #define XILINX_AXI_SPI_IRQ_MODF BSP_BIT32(0)
0054     uint32_t reserved3[5];
0055     uint32_t reset;
0056 #define XILINX_AXI_SPI_RESET 0x0000000a
0057     uint32_t reserved4[7];
0058     uint32_t control;
0059 #define XILINX_AXI_SPI_CONTROL_LSBFIRST BSP_BIT32(9)
0060 #define XILINX_AXI_SPI_CONTROL_MST_TRANS_INHIBIT BSP_BIT32(8)
0061 #define XILINX_AXI_SPI_CONTROL_MANUAL_CS BSP_BIT32(7)
0062 #define XILINX_AXI_SPI_CONTROL_RX_FIFO_RESET BSP_BIT32(6)
0063 #define XILINX_AXI_SPI_CONTROL_TX_FIFO_RESET BSP_BIT32(5)
0064 #define XILINX_AXI_SPI_CONTROL_CPHA BSP_BIT32(4)
0065 #define XILINX_AXI_SPI_CONTROL_CPOL BSP_BIT32(3)
0066 #define XILINX_AXI_SPI_CONTROL_MSTREN BSP_BIT32(2)
0067 #define XILINX_AXI_SPI_CONTROL_SPIEN BSP_BIT32(1)
0068 #define XILINX_AXI_SPI_CONTROL_LOOP BSP_BIT32(0)
0069     uint32_t status;
0070 #define XILINX_AXI_SPI_STATUS_CMD_ERR BSP_BIT32(10)
0071 #define XILINX_AXI_SPI_STATUS_LOOP_ERR BSP_BIT32(9)
0072 #define XILINX_AXI_SPI_STATUS_MSB_ERR BSP_BIT32(8)
0073 #define XILINX_AXI_SPI_STATUS_SLV_ERR BSP_BIT32(7)
0074 #define XILINX_AXI_SPI_STATUS_CPOL_CPHA_ERR BSP_BIT32(6)
0075 #define XILINX_AXI_SPI_STATUS_SLV_MODE BSP_BIT32(5)
0076 #define XILINX_AXI_SPI_STATUS_MODF BSP_BIT32(4)
0077 #define XILINX_AXI_SPI_STATUS_TXFULL BSP_BIT32(3)
0078 #define XILINX_AXI_SPI_STATUS_TXEMPTY BSP_BIT32(2)
0079 #define XILINX_AXI_SPI_STATUS_RXFULL BSP_BIT32(1)
0080 #define XILINX_AXI_SPI_STATUS_RXEMPTY BSP_BIT32(0)
0081     uint32_t txdata;
0082     uint32_t rxdata;
0083     uint32_t cs;
0084     uint32_t tx_fifo_len;
0085     uint32_t rx_fifo_len;
0086 } xilinx_axi_spi;
0087
0088 #endif /* LIBBSP_ARM_XILINX_AXI_SPI_REGS_H */