dev/spi/cadence-spi-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (C) 2021 Jan Sommer, German Aerospace Center (DLR)
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
0029 #define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
0030
0031 #include <bsp/utility.h>
0032
0033 typedef struct {
0034     uint32_t config;
0035 #define CADENCE_SPI_CONFIG_MODEFAIL_EN BSP_BIT32(17)
0036 #define CADENCE_SPI_CONFIG_MANSTRT BSP_BIT32(16)
0037 #define CADENCE_SPI_CONFIG_MANSTRT_EN BSP_BIT32(15)
0038 #define CADENCE_SPI_CONFIG_MANUAL_CS BSP_BIT32(14)
0039 #define CADENCE_SPI_CONFIG_CS(val) BSP_FLD32(val, 10, 13)
0040 #define CADENCE_SPI_CONFIG_CS_GET(reg) BSP_FLD32GET(reg, 10, 13)
0041 #define CADENCE_SPI_CONFIG_CS_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13)
0042 #define CADENCE_SPI_CONFIG_PERI_SEL BSP_BIT32(9)
0043 #define CADENCE_SPI_CONFIG_REF_CLK BSP_BIT32(8)
0044 #define CADENCE_SPI_CONFIG_BAUD_DIV(val) BSP_FLD32(val, 3, 5)
0045 #define CADENCE_SPI_CONFIG_BAUD_DIV_GET(reg) BSP_FLD32GET(reg, 3, 5)
0046 #define CADENCE_SPI_CONFIG_BAUD_DIV_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
0047 #define CADENCE_SPI_CONFIG_CLK_PH BSP_BIT32(2)
0048 #define CADENCE_SPI_CONFIG_CLK_POL BSP_BIT32(1)
0049 #define CADENCE_SPI_CONFIG_MSTREN BSP_BIT32(0)
0050     uint32_t irqstatus;
0051     uint32_t irqenable;
0052     uint32_t irqdisable;
0053     uint32_t irqmask;
0054 #define CADENCE_SPI_IXR_TXUF BSP_BIT32(6)
0055 #define CADENCE_SPI_IXR_RXFULL BSP_BIT32(5)
0056 #define CADENCE_SPI_IXR_RXNEMPTY BSP_BIT32(4)
0057 #define CADENCE_SPI_IXR_TXFULL BSP_BIT32(3)
0058 #define CADENCE_SPI_IXR_TXOW BSP_BIT32(2)
0059 #define CADENCE_SPI_IXR_MODF BSP_BIT32(1)
0060 #define CADENCE_SPI_IXR_RXOVR BSP_BIT32(0)
0061     uint32_t spienable;
0062 #define CADENCE_SPI_EN BSP_BIT32(0)
0063     uint32_t delay;
0064 #define CADENCE_SPI_DELAY_DNSS(val) BSP_FLD32(val, 24, 31)
0065 #define CADENCE_SPI_DELAY_DNSS_GET(reg) BSP_FLD32GET(reg, 24, 31)
0066 #define CADENCE_SPI_DELAY_DNSS_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
0067 #define CADENCE_SPI_DELAY_DBTWN(val) BSP_FLD32(val, 16, 23)
0068 #define CADENCE_SPI_DELAY_DBTWN_GET(reg) BSP_FLD32GET(reg, 16, 23)
0069 #define CADENCE_SPI_DELAY_DBTWN_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
0070 #define CADENCE_SPI_DELAY_DAFTER(val) BSP_FLD32(val, 8, 15)
0071 #define CADENCE_SPI_DELAY_DAFTER_GET(reg) BSP_FLD32GET(reg, 8, 15)
0072 #define CADENCE_SPI_DELAY_DAFTER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
0073 #define CADENCE_SPI_DELAY_DINT(val) BSP_FLD32(val, 0, 7)
0074 #define CADENCE_SPI_DELAY_DINT_GET(reg) BSP_FLD32GET(reg, 0, 7)
0075 #define CADENCE_SPI_DELAY_DINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
0076     uint32_t txdata;
0077     uint32_t rxdata;
0078     uint32_t slave_idle_count;
0079     uint32_t txthreshold;
0080     uint32_t rxthreshold;
0081     uint32_t unused[51];
0082     uint32_t moduleid;
0083 } cadence_spi;
0084
0085 #endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H */