dev/serial/zynq-uart-zynqmp.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDeviceSerialZynq
0007  *
0008  * @brief This header file provides interfaces with respect to the Zynq
0009  *   UltraScale+ MPSoC and RFSoC platforms.
0010  */
0011
0012 /*
0013  * Copyright (C) 2024 embedded brains GmbH & Co. KG
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifndef _DEV_SERIAL_ZYNQ_UART_ZYNQMP_H
0038 #define _DEV_SERIAL_ZYNQ_UART_ZYNQMP_H
0039
0040 #ifdef __cplusplus
0041 extern "C" {
0042 #endif /* __cplusplus */
0043
0044 /**
0045  * @addtogroup RTEMSDeviceSerialZynq
0046  *
0047  * @{
0048  */
0049
0050 /**
0051  * @brief This constant defines the Xilinx Zynq UART 0 base address.
0052  */
0053 #define ZYNQ_UART_0_BASE_ADDR 0xff000000
0054
0055 /**
0056  * @brief This constant defines the Xilinx Zynq UART 1 base address.
0057  */
0058 #define ZYNQ_UART_1_BASE_ADDR 0xff010000
0059
0060 /** @} */
0061
0062 #ifdef __cplusplus
0063 }
0064 #endif /* __cplusplus */
0065
0066 #endif /* _DEV_SERIAL_ZYNQ_UART_ZYNQMP_H */