dev/serial/zynq-uart-regs.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSDeviceSerialZynq
0005  *
0006  * @brief This header file provides Zynq UART interfaces.
0007  */
0008
0009 /*
0010  * SPDX-License-Identifier: BSD-2-Clause
0011  *
0012  * Copyright (C) 2013 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /**
0037  * @defgroup RTEMSDeviceSerialZynq Zynq UART Support
0038  *
0039  * @ingroup RTEMSDeviceConsole
0040  *
0041  * @brief This group contains the Zynq UART support.
0042  *
0043  * @{
0044  */
0045
0046 #ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
0047 #define LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
0048
0049 #include <bsp/utility.h>
0050
0051 #define ZYNQ_UART_DEFAULT_BAUD 115200
0052
0053 #define ZYNQ_UART_FIFO_DEPTH 64
0054
0055 typedef struct zynq_uart {
0056     uint32_t control;
0057 #define ZYNQ_UART_CONTROL_STPBRK BSP_BIT32(8)
0058 #define ZYNQ_UART_CONTROL_STTBRK BSP_BIT32(7)
0059 #define ZYNQ_UART_CONTROL_RSTTO BSP_BIT32(6)
0060 #define ZYNQ_UART_CONTROL_TXDIS BSP_BIT32(5)
0061 #define ZYNQ_UART_CONTROL_TXEN BSP_BIT32(4)
0062 #define ZYNQ_UART_CONTROL_RXDIS BSP_BIT32(3)
0063 #define ZYNQ_UART_CONTROL_RXEN BSP_BIT32(2)
0064 #define ZYNQ_UART_CONTROL_TXRES BSP_BIT32(1)
0065 #define ZYNQ_UART_CONTROL_RXRES BSP_BIT32(0)
0066     uint32_t mode;
0067 #define ZYNQ_UART_MODE_CHMODE(val) BSP_FLD32(val, 8, 9)
0068 #define ZYNQ_UART_MODE_CHMODE_GET(reg) BSP_FLD32GET(reg, 8, 9)
0069 #define ZYNQ_UART_MODE_CHMODE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9)
0070 #define ZYNQ_UART_MODE_CHMODE_NORMAL 0x00U
0071 #define ZYNQ_UART_MODE_CHMODE_AUTO_ECHO 0x01U
0072 #define ZYNQ_UART_MODE_CHMODE_LOCAL_LOOPBACK 0x02U
0073 #define ZYNQ_UART_MODE_CHMODE_REMOTE_LOOPBACK 0x03U
0074 #define ZYNQ_UART_MODE_NBSTOP(val) BSP_FLD32(val, 6, 7)
0075 #define ZYNQ_UART_MODE_NBSTOP_GET(reg) BSP_FLD32GET(reg, 6, 7)
0076 #define ZYNQ_UART_MODE_NBSTOP_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7)
0077 #define ZYNQ_UART_MODE_NBSTOP_STOP_1 0x00U
0078 #define ZYNQ_UART_MODE_NBSTOP_STOP_1_5 0x01U
0079 #define ZYNQ_UART_MODE_NBSTOP_STOP_2 0x02U
0080 #define ZYNQ_UART_MODE_PAR(val) BSP_FLD32(val, 3, 5)
0081 #define ZYNQ_UART_MODE_PAR_GET(reg) BSP_FLD32GET(reg, 3, 5)
0082 #define ZYNQ_UART_MODE_PAR_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
0083 #define ZYNQ_UART_MODE_PAR_EVEN 0x00U
0084 #define ZYNQ_UART_MODE_PAR_ODD 0x01U
0085 #define ZYNQ_UART_MODE_PAR_SPACE 0x02U
0086 #define ZYNQ_UART_MODE_PAR_MARK 0x03U
0087 #define ZYNQ_UART_MODE_PAR_NONE 0x04U
0088 #define ZYNQ_UART_MODE_CHRL(val) BSP_FLD32(val, 1, 2)
0089 #define ZYNQ_UART_MODE_CHRL_GET(reg) BSP_FLD32GET(reg, 1, 2)
0090 #define ZYNQ_UART_MODE_CHRL_SET(reg, val) BSP_FLD32SET(reg, val, 1, 2)
0091 #define ZYNQ_UART_MODE_CHRL_8 0x00U
0092 #define ZYNQ_UART_MODE_CHRL_7 0x02U
0093 #define ZYNQ_UART_MODE_CHRL_6 0x03U
0094 #define ZYNQ_UART_MODE_CLKS BSP_BIT32(0)
0095     uint32_t irq_en;
0096     uint32_t irq_dis;
0097     uint32_t irq_mask;
0098     uint32_t irq_sts;
0099 #define ZYNQ_UART_TOVR BSP_BIT32(12)
0100 #define ZYNQ_UART_TNFUL BSP_BIT32(11)
0101 #define ZYNQ_UART_TTRIG BSP_BIT32(10)
0102 #define ZYNQ_UART_DMSI BSP_BIT32(9)
0103 #define ZYNQ_UART_TIMEOUT BSP_BIT32(8)
0104 #define ZYNQ_UART_PARE BSP_BIT32(7)
0105 #define ZYNQ_UART_FRAME BSP_BIT32(6)
0106 #define ZYNQ_UART_ROVR BSP_BIT32(5)
0107 #define ZYNQ_UART_TFUL BSP_BIT32(4)
0108 #define ZYNQ_UART_TEMPTY BSP_BIT32(3)
0109 #define ZYNQ_UART_RFUL BSP_BIT32(2)
0110 #define ZYNQ_UART_REMPTY BSP_BIT32(1)
0111 #define ZYNQ_UART_RTRIG BSP_BIT32(0)
0112     uint32_t baud_rate_gen;
0113 #define ZYNQ_UART_BAUD_RATE_GEN_CD(val) BSP_FLD32(val, 0, 15)
0114 #define ZYNQ_UART_BAUD_RATE_GEN_CD_GET(reg) BSP_FLD32GET(reg, 0, 15)
0115 #define ZYNQ_UART_BAUD_RATE_GEN_CD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
0116     uint32_t rx_timeout;
0117 #define ZYNQ_UART_RX_TIMEOUT_RTO(val) BSP_FLD32(val, 0, 7)
0118 #define ZYNQ_UART_RX_TIMEOUT_RTO_GET(reg) BSP_FLD32GET(reg, 0, 7)
0119 #define ZYNQ_UART_RX_TIMEOUT_RTO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
0120     uint32_t rx_fifo_trg_lvl;
0121 #define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(val) BSP_FLD32(val, 0, 5)
0122 #define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
0123 #define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
0124     uint32_t modem_ctrl;
0125 #define ZYNQ_UART_MODEM_CTRL_FCM BSP_BIT32(5)
0126 #define ZYNQ_UART_MODEM_CTRL_RTS BSP_BIT32(1)
0127 #define ZYNQ_UART_MODEM_CTRL_DTR BSP_BIT32(0)
0128     uint32_t modem_sts;
0129 #define ZYNQ_UART_MODEM_STS_FCMS BSP_BIT32(8)
0130 #define ZYNQ_UART_MODEM_STS_DCD BSP_BIT32(7)
0131 #define ZYNQ_UART_MODEM_STS_RI BSP_BIT32(6)
0132 #define ZYNQ_UART_MODEM_STS_DSR BSP_BIT32(5)
0133 #define ZYNQ_UART_MODEM_STS_CTS BSP_BIT32(4)
0134 #define ZYNQ_UART_MODEM_STS_DDCD BSP_BIT32(3)
0135 #define ZYNQ_UART_MODEM_STS_TERI BSP_BIT32(2)
0136 #define ZYNQ_UART_MODEM_STS_DDSR BSP_BIT32(1)
0137 #define ZYNQ_UART_MODEM_STS_DCTS BSP_BIT32(0)
0138     uint32_t channel_sts;
0139 #define ZYNQ_UART_CHANNEL_STS_TNFUL BSP_BIT32(14)
0140 #define ZYNQ_UART_CHANNEL_STS_TTRIG BSP_BIT32(13)
0141 #define ZYNQ_UART_CHANNEL_STS_FDELT BSP_BIT32(12)
0142 #define ZYNQ_UART_CHANNEL_STS_TACTIVE BSP_BIT32(11)
0143 #define ZYNQ_UART_CHANNEL_STS_RACTIVE BSP_BIT32(10)
0144 #define ZYNQ_UART_CHANNEL_STS_TFUL BSP_BIT32(4)
0145 #define ZYNQ_UART_CHANNEL_STS_TEMPTY BSP_BIT32(3)
0146 #define ZYNQ_UART_CHANNEL_STS_RFUL BSP_BIT32(2)
0147 #define ZYNQ_UART_CHANNEL_STS_REMPTY BSP_BIT32(1)
0148 #define ZYNQ_UART_CHANNEL_STS_RTRIG BSP_BIT32(0)
0149     uint32_t tx_rx_fifo;
0150 #define ZYNQ_UART_TX_RX_FIFO_FIFO(val) BSP_FLD32(val, 0, 7)
0151 #define ZYNQ_UART_TX_RX_FIFO_FIFO_GET(reg) BSP_FLD32GET(reg, 0, 7)
0152 #define ZYNQ_UART_TX_RX_FIFO_FIFO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
0153     uint32_t baud_rate_div;
0154 #define ZYNQ_UART_BAUD_RATE_DIV_BDIV(val) BSP_FLD32(val, 0, 7)
0155 #define ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET(reg) BSP_FLD32GET(reg, 0, 7)
0156 #define ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
0157     uint32_t flow_delay;
0158 #define ZYNQ_UART_FLOW_DELAY_FDEL(val) BSP_FLD32(val, 0, 5)
0159 #define ZYNQ_UART_FLOW_DELAY_FDEL_GET(reg) BSP_FLD32GET(reg, 0, 5)
0160 #define ZYNQ_UART_FLOW_DELAY_FDEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
0161     uint32_t reserved_3c[2];
0162     uint32_t tx_fifo_trg_lvl;
0163 #define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG(val) BSP_FLD32(val, 0, 5)
0164 #define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
0165 #define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
0166 } zynq_uart;
0167
0168 void zynq_uart_initialize(volatile zynq_uart *regs);
0169
0170 int zynq_uart_read_char_polled(volatile zynq_uart *regs);
0171
0172 void zynq_uart_write_char_polled(volatile zynq_uart *regs, char c);
0173
0174 /**
0175   * Flush TX FIFO and wait until it is empty. Used in bsp_reset.
0176   */
0177 void zynq_uart_reset_tx_flush(volatile zynq_uart *regs);
0178
0179 /**
0180  * @brief Returns the Zynq UART input clock frequency in Hz.
0181  */
0182 uint32_t zynq_uart_input_clock(void);
0183
0184 /**
0185  * @brief Calculates the clock and baud divisor of the best approximation of
0186  *   the desired baud.
0187  *
0188  * The function tries to yield a sample set around 16 per RX-bit.
0189  *
0190  * @param desired_baud is the desired baud for an Zynq UART device.
0191  *
0192  * @param mode_clks is the value of the CLKS bit of the Zynq UART mode register.
0193  *
0194  * @param cd_ptr[out] is a reference to an uint32_t object.  The function
0195  *   stores the calculated clock divisor to this object.
0196  *
0197  * @param bdiv_ptr[out] is a reference to an uint32_t object.  The function
0198  *   stores the calculated baud divisor to this object.
0199  *
0200  * @return Returns the absolute error of the calculated baud to the desired
0201  *   baud in Hz.
0202  */
0203 uint32_t zynq_uart_calculate_baud(
0204   uint32_t  desired_baud,
0205   uint32_t  mode_clks,
0206   uint32_t *cd_ptr,
0207   uint32_t *bdiv_ptr
0208 );
0209
0210 /** @} */
0211
0212 #endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */