dev/serial/arm-pl011-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  *  @file
0005  *
0006  *  @ingroup RTEMSBSPsARMShared
0007  *
0008  *  @brief ARM PL011 Register definitions
0009  */
0010
0011 /*
0012  * Copyright (c) 2013 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /**
0037  * @defgroup ARM PL011 UART Register Definitions
0038  * @ingroup RTEMSBSPsARMShared
0039  * @brief UART Register Definitions
0040  * @{
0041  */
0042
0043 #ifndef LIBBSP_ARM_SHARED_ARM_PL011_REGS_H
0044 #define LIBBSP_ARM_SHARED_ARM_PL011_REGS_H
0045
0046 #include <bsp/utility.h>
0047
0048 typedef struct {
0049   uint32_t uartdr;
0050 #define PL011_UARTDR_OE BSP_BIT32(11)
0051 #define PL011_UARTDR_BE BSP_BIT32(10)
0052 #define PL011_UARTDR_PE BSP_BIT32(9)
0053 #define PL011_UARTDR_FE BSP_BIT32(8)
0054 #define PL011_UARTDR_DATA(val) BSP_FLD32(val, 0, 7)
0055 #define PL011_UARTDR_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7)
0056 #define PL011_UARTDR_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
0057   uint32_t uartrsr_uartecr;
0058 #define PL011_UARTRSR_UARTECR_OE BSP_BIT32(3)
0059 #define PL011_UARTRSR_UARTECR_BE BSP_BIT32(2)
0060 #define PL011_UARTRSR_UARTECR_PE BSP_BIT32(1)
0061 #define PL011_UARTRSR_UARTECR_FE BSP_BIT32(0)
0062   uint32_t reserved_08[4];
0063   uint32_t uartfr;
0064 #define PL011_UARTFR_RI BSP_BIT32(8)
0065 #define PL011_UARTFR_TXFE BSP_BIT32(7)
0066 #define PL011_UARTFR_RXFF BSP_BIT32(6)
0067 #define PL011_UARTFR_TXFF BSP_BIT32(5)
0068 #define PL011_UARTFR_RXFE BSP_BIT32(4)
0069 #define PL011_UARTFR_BUSY BSP_BIT32(3)
0070 #define PL011_UARTFR_DCD BSP_BIT32(2)
0071 #define PL011_UARTFR_DSR BSP_BIT32(1)
0072 #define PL011_UARTFR_CTS BSP_BIT32(0)
0073   uint32_t reserved_1c;
0074   uint32_t uartilpr;
0075 #define PL011_UARTILPR_ILPDVSR(val) BSP_FLD32(val, 0, 7)
0076 #define PL011_UARTILPR_ILPDVSR_GET(reg) BSP_FLD32GET(reg, 0, 7)
0077 #define PL011_UARTILPR_ILPDVSR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
0078   uint32_t uartibrd;
0079 #define PL011_UARTIBRD_BAUD_DIVINT_WIDTH 16
0080 #define PL011_UARTIBRD_BAUD_DIVINT_MASK \
0081   BSP_MSK32(0, PL011_UARTIBRD_BAUD_DIVINT_WIDTH - 1)
0082 #define PL011_UARTIBRD_BAUD_DIVINT(val) BSP_FLD32(val, 0, 15)
0083 #define PL011_UARTIBRD_BAUD_DIVINT_GET(reg) BSP_FLD32GET(reg, 0, 15)
0084 #define PL011_UARTIBRD_BAUD_DIVINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
0085   uint32_t uartfbrd;
0086 #define PL011_UARTFBRD_BAUD_DIVFRAC_WIDTH 6
0087 #define PL011_UARTFBRD_BAUD_DIVFRAC_MASK \
0088   BSP_MSK32(0, PL011_UARTFBRD_BAUD_DIVFRAC_WIDTH - 1)
0089 #define PL011_UARTFBRD_BAUD_DIVFRAC(val) BSP_FLD32(val, 0, 5)
0090 #define PL011_UARTFBRD_BAUD_DIVFRAC_GET(reg) BSP_FLD32GET(reg, 0, 5)
0091 #define PL011_UARTFBRD_BAUD_DIVFRAC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
0092   uint32_t uartlcr_h;
0093 #define PL011_UARTLCR_H_SPS BSP_BIT32(7)
0094 #define PL011_UARTLCR_H_WLEN(val) BSP_FLD32(val, 5, 6)
0095 #define PL011_UARTLCR_H_WLEN_GET(reg) BSP_FLD32GET(reg, 5, 6)
0096 #define PL011_UARTLCR_H_WLEN_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6)
0097 #define PL011_UARTLCR_H_WLEN_5 0x00U
0098 #define PL011_UARTLCR_H_WLEN_6 0x01U
0099 #define PL011_UARTLCR_H_WLEN_7 0x02U
0100 #define PL011_UARTLCR_H_WLEN_8 0x03U
0101 #define PL011_UARTLCR_H_FEN BSP_BIT32(4)
0102 #define PL011_UARTLCR_H_STP2 BSP_BIT32(3)
0103 #define PL011_UARTLCR_H_EPS BSP_BIT32(2)
0104 #define PL011_UARTLCR_H_PEN BSP_BIT32(1)
0105 #define PL011_UARTLCR_H_BRK BSP_BIT32(0)
0106   uint32_t uartcr;
0107 #define PL011_UARTCR_CTSEN BSP_BIT32(15)
0108 #define PL011_UARTCR_RTSEN BSP_BIT32(14)
0109 #define PL011_UARTCR_OUT2 BSP_BIT32(13)
0110 #define PL011_UARTCR_OUT1 BSP_BIT32(12)
0111 #define PL011_UARTCR_RTS BSP_BIT32(11)
0112 #define PL011_UARTCR_DTR BSP_BIT32(10)
0113 #define PL011_UARTCR_RXE BSP_BIT32(9)
0114 #define PL011_UARTCR_TXE BSP_BIT32(8)
0115 #define PL011_UARTCR_LBE BSP_BIT32(7)
0116 #define PL011_UARTCR_SIRLP BSP_BIT32(2)
0117 #define PL011_UARTCR_SIREN BSP_BIT32(1)
0118 #define PL011_UARTCR_UARTEN BSP_BIT32(0)
0119   uint32_t uartifls;
0120 #define PL011_UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5)
0121 #define PL011_UARTIFLS_RXIFLSEL_GET(reg) BSP_FLD32GET(reg, 3, 5)
0122 #define PL011_UARTIFLS_RXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
0123 #define PL011_UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2)
0124 #define PL011_UARTIFLS_TXIFLSEL_GET(reg) BSP_FLD32GET(reg, 0, 2)
0125 #define PL011_UARTIFLS_TXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
0126   uint32_t uartimsc;
0127   uint32_t uartris;
0128   uint32_t uartmis;
0129   uint32_t uarticr;
0130 #define PL011_UARTI_OEI BSP_BIT32(10)
0131 #define PL011_UARTI_BEI BSP_BIT32(9)
0132 #define PL011_UARTI_PEI BSP_BIT32(8)
0133 #define PL011_UARTI_FEI BSP_BIT32(7)
0134 #define PL011_UARTI_RTI BSP_BIT32(6)
0135 #define PL011_UARTI_TXI BSP_BIT32(5)
0136 #define PL011_UARTI_RXI BSP_BIT32(4)
0137 #define PL011_UARTI_DSRMI BSP_BIT32(3)
0138 #define PL011_UARTI_DCDMI BSP_BIT32(2)
0139 #define PL011_UARTI_CTSMI BSP_BIT32(1)
0140 #define PL011_UARTI_RIMI BSP_BIT32(0)
0141 #define PL011_UARTI_MASK BSP_MSK32(0, 10)
0142   uint32_t uartdmacr;
0143 #define PL011_UARTDMACR_DMAONERR BSP_BIT32(2)
0144 #define PL011_UARTDMACR_TXDMAE BSP_BIT32(1)
0145 #define PL011_UARTDMACR_RXDMAE BSP_BIT32(0)
0146 } pl011_base;
0147
0148 /** @} */
0149
0150 #endif /* LIBBSP_ARM_SHARED_ARM_PL011_REGS_H */