dev/nand/xnandpsu_onfi.h

0001 /******************************************************************************
0002 * Copyright (C) 2015 - 2022 Xilinx, Inc.  All rights reserved.
0003 * SPDX-License-Identifier: MIT
0004 ******************************************************************************/
0005
0006 /*****************************************************************************/
0007 /**
0008 *
0009 * @file xnandpsu_onfi.h
0010 * @addtogroup Overview
0011 * @{
0012 *
0013 * This file defines all the ONFI 3.1 specific commands and values.
0014 *
0015 * @note     None
0016 *
0017 * <pre>
0018 * MODIFICATION HISTORY:
0019 *
0020 * Ver   Who    Date    Changes
0021 * ----- ----   ----------  -----------------------------------------------
0022 * 1.0   nm     05/06/2014  First release
0023 * 1.4   nsk    04/10/2018  Added ICCARM compiler support.
0024 * </pre>
0025 *
0026 ******************************************************************************/
0027 #ifndef XNANDPSU_ONFI_H     /* prevent circular inclusions */
0028 #define XNANDPSU_ONFI_H     /* by using protection macros */
0029
0030 #ifdef __cplusplus
0031 extern "C" {
0032 #endif
0033
0034 /***************************** Include Files *********************************/
0035 #ifndef __rtems__
0036 #include "xil_types.h"
0037 #else
0038 #include <bsp/xil-compat.h>
0039 #endif
0040
0041 /************************** Constant Definitions *****************************/
0042 /* Standard ONFI 3.1 Commands */
0043 /* ONFI 3.1 Mandatory Commands */
0044 #define ONFI_CMD_RD1            0x00U   /**< Read (1st cycle) */
0045 #define ONFI_CMD_RD2            0x30U   /**< Read (2nd cycle) */
0046 #define ONFI_CMD_CHNG_RD_COL1       0x05U   /**< Change Read Column
0047                           (1st cycle) */
0048 #define ONFI_CMD_CHNG_RD_COL2       0xE0U   /**< Change Read Column
0049                           (2nd cycle) */
0050 #define ONFI_CMD_BLK_ERASE1     0x60U   /**< Block Erase (1st cycle) */
0051 #define ONFI_CMD_BLK_ERASE2     0xD0U   /**< Block Erase (2nd cycle) */
0052 #define ONFI_CMD_RD_STS         0x70U   /**< Read Status */
0053 #define ONFI_CMD_PG_PROG1       0x80U   /**< Page Program(1st cycle) */
0054 #define ONFI_CMD_PG_PROG2       0x10U   /**< Page Program(2nd cycle) */
0055 #define ONFI_CMD_CHNG_WR_COL        0x85U   /**< Change Write Column */
0056 #define ONFI_CMD_RD_ID          0x90U   /**< Read ID */
0057 #define ONFI_CMD_RD_PRM_PG      0xECU   /**< Read Parameter Page */
0058 #define ONFI_CMD_RST            0xFFU   /**< Reset */
0059 /* ONFI 3.1 Optional Commands */
0060 #define ONFI_CMD_MUL_RD1        0x00U   /**< Multiplane Read
0061                           (1st cycle) */
0062 #define ONFI_CMD_MUL_RD2        0x32U   /**< Multiplane Read
0063                           (2nd cycle) */
0064 #define ONFI_CMD_CPBK_RD1       0x00U   /**< Copyback Read
0065                           (1st cycle) */
0066 #define ONFI_CMD_CPBK_RD2       0x35U   /**< Copyback Read
0067                           (2nd cycle) */
0068 #define ONFI_CMD_CHNG_RD_COL_ENHCD1 0x06U   /**< Change Read Column
0069                           Enhanced (1st cycle) */
0070 #define ONFI_CMD_CHNG_RD_COL_ENHCD2 0xE0U   /**< Change Read Column
0071                           Enhanced (2nd cycle) */
0072 #define ONFI_CMD_RD_CACHE_RND1      0x00U   /**< Read Cache Random
0073                           (1st cycle) */
0074 #define ONFI_CMD_RD_CACHE_RND2      0x31U   /**< Read Cache Random
0075                           (2nd cycle) */
0076 #define ONFI_CMD_RD_CACHE_SEQ       0x31U   /**< Read Cache Sequential */
0077 #define ONFI_CMD_RD_CACHE_END       0x3FU   /**< Read Cache End */
0078 #define ONFI_CMD_MUL_BLK_ERASE1     0x60U   /**< Multiplane Block Erase
0079                           (1st cycle) */
0080 #define ONFI_CMD_MUL_BLK_ERASE2     0xD1U   /**< Multiplane Block Erase
0081                           (2nd cycle) */
0082 #define ONFI_CMD_RD_STS_ENHCD       0x78U   /**< Read Status Enhanced */
0083 #define ONFI_CMD_BLK_ERASE_INTRLVD2 0xD1U   /**< Block Erase Interleaved
0084                           (2nd cycle) */
0085 #define ONFI_CMD_MUL_PG_PROG1       0x80U   /**< Multiplane Page Program
0086                           (1st cycle) */
0087 #define ONFI_CMD_MUL_PG_PROG2       0x11U   /**< Multiplane Page Program
0088                           (2nd cycle) */
0089 #define ONFI_CMD_PG_CACHE_PROG1     0x80U   /**< Page Cache Program
0090                           (1st cycle) */
0091 #define ONFI_CMD_PG_CACHE_PROG2     0x15U   /**< Page Cache Program
0092                           (2nd cycle) */
0093 #define ONFI_CMD_CPBK_PROG1     0x85U   /**< Copyback Program
0094                           (1st cycle) */
0095 #define ONFI_CMD_CPBK_PROG2     0x10U   /**< Copyback Program
0096                           (2nd cycle) */
0097 #define ONFI_CMD_MUL_CPBK_PROG1     0x85U   /**< Multiplane Copyback
0098                           Program (1st cycle) */
0099 #define ONFI_CMD_MUL_CPBK_PROG2     0x10U   /**< Multiplane Copyback
0100                           Program (2nd cycle) */
0101 #define ONFI_CMD_SMALL_DATA_MV1     0x85U   /**< Small Data Move
0102                           (1st cycle) */
0103 #define ONFI_CMD_SMALL_DATA_MV2     0x10U   /**< Small Data Move
0104                           (2nd cycle) */
0105 #define ONFI_CMD_CHNG_ROW_ADDR      0x85U   /**< Change Row Address */
0106 #define ONFI_CMD_VOL_SEL        0xE1U   /**< Volume Select */
0107 #define ONFI_CMD_ODT_CONF       0xE2U   /**< ODT Configure */
0108 #define ONFI_CMD_RD_UNIQID      0xEDU   /**< Read Unique ID */
0109 #define ONFI_CMD_GET_FEATURES       0xEEU   /**< Get Features */
0110 #define ONFI_CMD_SET_FEATURES       0xEFU   /**< Set Features */
0111 #define ONFI_CMD_LUN_GET_FEATURES   0xD4U   /**< LUN Get Features */
0112 #define ONFI_CMD_LUN_SET_FEATURES   0xD5U   /**< LUN Set Features */
0113 #define ONFI_CMD_RST_LUN        0xFAU   /**< Reset LUN */
0114 #define ONFI_CMD_SYN_RST        0xFCU   /**< Synchronous Reset */
0115
0116 /* ONFI Status Register bit offsets */
0117 #define ONFI_STS_FAIL           0x01U   /**< FAIL */
0118 #define ONFI_STS_FAILC          0x02U   /**< FAILC */
0119 #define ONFI_STS_CSP            0x08U   /**< CSP */
0120 #define ONFI_STS_VSP            0x10U   /**< VSP */
0121 #define ONFI_STS_ARDY           0x20U   /**< ARDY */
0122 #define ONFI_STS_RDY            0x40U   /**< RDY */
0123 #define ONFI_STS_WP         0x80U   /**< WP_n */
0124
0125 /* ONFI constants */
0126 #define ONFI_CRC_LEN            254U    /**< ONFI CRC Buf Length */
0127 #define ONFI_PRM_PG_LEN         256U    /**< Parameter Page Length */
0128 #define ONFI_MND_PRM_PGS        3U  /**< Number of mandatory
0129                           parameter pages */
0130 #define ONFI_SIG_LEN            4U  /**< Signature Length */
0131 #define ONFI_CMD_INVALID        0x00U   /**< Invalid Command */
0132
0133 #define ONFI_READ_ID_LEN        4U  /**< ONFI ID length */
0134 #define ONFI_READ_ID_ADDR       0x20U   /**< ONFI Read ID Address */
0135 #define ONFI_READ_ID_ADDR_CYCLES    1U  /**< ONFI Read ID Address
0136                           cycles */
0137
0138 #define ONFI_PRM_PG_ADDR_CYCLES     1U  /**< ONFI Read Parameter page
0139                           address cycles */
0140
0141 /**
0142  * This enum defines the ONFI 3.1 commands.
0143  */
0144 enum OnfiCommandList {
0145     READ=0,             /**< Read */
0146     MULTIPLANE_READ,        /**< Multiplane Read */
0147     COPYBACK_READ,          /**< Copyback Read */
0148     CHANGE_READ_COLUMN,     /**< Change Read Column */
0149     CHANGE_READ_COLUMN_ENHANCED,    /**< Change Read Column Enhanced */
0150     READ_CACHE_RANDOM,      /**< Read Cache Random */
0151     READ_CACHE_SEQUENTIAL,      /**< Read Cache Sequential */
0152     READ_CACHE_END,         /**< Read Cache End */
0153     BLOCK_ERASE,            /**< Block Erase */
0154     MULTIPLANE_BLOCK_ERASE,     /**< Multiplane Block Erase */
0155     READ_STATUS,            /**< Read Status */
0156     READ_STATUS_ENHANCED,       /**< Read Status Enhanced */
0157     PAGE_PROGRAM,           /**< Page Program */
0158     MULTIPLANE_PAGE_PROGRAM,    /**< Multiplane Page Program */
0159     PAGE_CACHE_PROGRAM,     /**< Page Cache Program */
0160     COPYBACK_PROGRAM,       /**< Copyback Program */
0161     MULTIPLANE_COPYBACK_PROGRAM,    /**< Multiplance Copyback Program */
0162     SMALL_DATA_MOVE,        /**< Small Data Move */
0163     CHANGE_WRITE_COLUMN,        /**< Change Write Column */
0164     CHANGE_ROW_ADDR,        /**< Change Row Address */
0165     READ_ID,            /**< Read ID */
0166     VOLUME_SELECT,          /**< Volume Select */
0167     ODT_CONFIGURE,          /**< ODT Configure */
0168     READ_PARAM_PAGE,        /**< Read Parameter Page */
0169     READ_UNIQUE_ID,         /**< Read Unique ID */
0170     GET_FEATURES,           /**< Get Features */
0171     SET_FEATURES,           /**< Set Features */
0172     LUN_GET_FEATURES,       /**< LUN Get Features */
0173     LUN_SET_FEATURES,       /**< LUN Set Features */
0174     RESET_LUN,          /**< Reset LUN */
0175     SYN_RESET,          /**< Synchronous Reset */
0176     RESET,              /**< Reset */
0177     MAX_CMDS            /**< Dummy Command */
0178 };
0179
0180 /**************************** Type Definitions *******************************/
0181 /* Parameter page structure of ONFI 3.1 specification. */
0182 #ifdef __ICCARM__
0183 #pragma pack(push, 1)
0184 #endif
0185 typedef struct {
0186     /* Revision information and features block */
0187     u8 Signature[4];        /**< Parameter page signature */
0188     u16 Revision;           /**< Revision Number */
0189     u16 Features;           /**< Features supported */
0190     u16 OptionalCmds;       /**< Optional commands supported */
0191     u8 JedecJtgPrmAdvCmd;       /**< ONFI JEDEC JTG primary advanced
0192                       command support */
0193     u8 Reserved0;           /**< Reserved (11) */
0194     u16 ExtParamPageLen;        /**< Extended Parameter Page Length */
0195     u8 NumOfParamPages;     /**< Number of Parameter Pages */
0196     u8 Reserved1[17];       /**< Reserved (15-31) */
0197     /* Manufacturer information block */
0198     u8 DeviceManufacturer[12];  /**< Device manufacturer */
0199     u8 DeviceModel[20];     /**< Device model */
0200     u8 JedecManufacturerId;     /**< JEDEC Manufacturer ID */
0201     u8 DateCode[2];         /**< Date code */
0202     u8 Reserved2[13];       /**< Reserved (67-79) */
0203     /* Memory organization block */
0204     u32 BytesPerPage;       /**< Number of data bytes per page */
0205     u16 SpareBytesPerPage;      /**< Number of spare bytes per page */
0206     u32 BytesPerPartialPage;    /**< Number of data bytes per
0207                       partial page */
0208     u16 SpareBytesPerPartialPage;   /**< Number of spare bytes per
0209                       partial page */
0210     u32 PagesPerBlock;      /**< Number of pages per block */
0211     u32 BlocksPerLun;       /**< Number of blocks per LUN */
0212     u8 NumLuns;         /**< Number of LUN's */
0213     u8 AddrCycles;          /**< Number of address cycles */
0214     u8 BitsPerCell;         /**< Number of bits per cell */
0215     u16 MaxBadBlocksPerLun;     /**< Bad blocks maximum per LUN */
0216     u16 BlockEndurance;     /**< Block endurance */
0217     u8 GuaranteedValidBlock;    /**< Guaranteed valid blocks at
0218                       beginning of target */
0219     u16 BlockEnduranceGVB;      /**< Block endurance for guaranteed
0220                       valid block */
0221     u8 ProgramsPerPage;     /**< Number of programs per page */
0222     u8 PartialProgAttr;     /**< Partial programming attributes */
0223     u8 EccBits;         /**< Number of bits ECC
0224                       correctability */
0225     u8 PlaneAddrBits;       /**< Number of plane address bits */
0226     u8 PlaneOperationAttr;      /**< Multi-plane operation
0227                       attributes */
0228     u8 EzNandSupport;       /**< EZ NAND support */
0229     u8 Reserved3[12];       /**< Reserved (116 - 127) */
0230     /* Electrical parameters block */
0231     u8 IOPinCapacitance;        /**< I/O pin capacitance, maximum */
0232     u16 SDRTimingMode;      /**< SDR Timing mode support */
0233     u16 SDRPagecacheTimingMode; /**< SDR Program cache timing mode */
0234     u16 TProg;          /**< Maximum page program time */
0235     u16 TBers;          /**< Maximum block erase time */
0236     u16 TR;             /**< Maximum page read time */
0237     u16 TCcs;           /**< Maximum change column setup
0238                       time */
0239     u8 NVDDRTimingMode;     /**< NVDDR timing mode support */
0240     u8 NVDDR2TimingMode;        /**< NVDDR2 timing mode support */
0241     u8 SynFeatures;         /**< NVDDR/NVDDR2 features */
0242     u16 ClkInputPinCap;     /**< CLK input pin capacitance */
0243     u16 IOPinCap;           /**< I/O pin capacitance */
0244     u16 InputPinCap;        /**< Input pin capacitance typical */
0245     u8 InputPinCapMax;      /**< Input pin capacitance maximum */
0246     u8 DrvStrength;         /**< Driver strength support */
0247     u16 TMr;            /**< Maximum multi-plane read time */
0248     u16 TAdl;           /**< Program page register clear
0249                       enhancement value */
0250     u16 TEr;            /**< Typical page read time for
0251                       EZ NAND */
0252     u8 NVDDR2Features;      /**< NVDDR2 Features */
0253     u8 NVDDR2WarmupCycles;      /**< NVDDR2 Warmup Cycles */
0254     u8 Reserved4[4];        /**< Reserved (160 - 163) */
0255     /* Vendor block */
0256     u16 VendorRevisionNum;      /**< Vendor specific revision number */
0257     u8 VendorSpecific[88];      /**< Vendor specific */
0258     u16 Crc;            /**< Integrity CRC */
0259 #ifdef __ICCARM__
0260 } OnfiParamPage;
0261 #pragma pack(pop)
0262 #else
0263 }__attribute__((packed))OnfiParamPage;
0264 #endif
0265
0266 /* ONFI extended parameter page structure. */
0267 #ifdef __ICCARM__
0268 #pragma pack(push, 1)
0269 #endif
0270 typedef struct {
0271     u16 Crc;
0272     u8 Sig[4];
0273     u8 Reserved1[10];
0274     u8 Section0Type;
0275     u8 Section0Len;
0276     u8 Section1Type;
0277     u8 Section1Len;
0278     u8 ResSection[12];
0279     u8 SectionData[256];
0280 #ifdef __ICCARM__
0281 } OnfiExtPrmPage;
0282 #pragma pack(pop)
0283 #else
0284 }__attribute__((packed))OnfiExtPrmPage;
0285 #endif
0286
0287 /* Driver extended parameter page information. */
0288 #ifdef __ICCARM__
0289 #pragma pack(push, 1)
0290 #endif
0291 typedef struct {
0292     u8 NumEccBits;
0293     u8 CodeWordSize;
0294     u16 MaxBadBlocks;
0295     u16 BlockEndurance;
0296     u16 Reserved;
0297 #ifdef __ICCARM__
0298 } OnfiExtEccBlock;
0299 #pragma pack(pop)
0300 #else
0301 }__attribute__((packed))OnfiExtEccBlock;
0302 #endif
0303
0304 typedef struct {
0305     u8 Command1;            /**< Command Cycle 1 */
0306     u8 Command2;            /**< Command Cycle 2 */
0307 } OnfiCmdFormat;
0308
0309 extern const OnfiCmdFormat OnfiCmd[MAX_CMDS];
0310
0311 /************************** Function Prototypes ******************************/
0312
0313 u32 XNandPsu_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length);
0314
0315 #ifdef __cplusplus
0316 }
0317 #endif
0318
0319 #endif /* XNANDPSU_ONFI_H end of protection macro */
0320 /** @} */