dev/nand/xnandpsu_hw.h

0001 /******************************************************************************
0002 * Copyright (C) 2015 - 2022 Xilinx, Inc.  All rights reserved.
0003 * SPDX-License-Identifier: MIT
0004 ******************************************************************************/
0005
0006 /*****************************************************************************/
0007 /**
0008 *
0009 * @file xnandpsu_hw.h
0010 * @addtogroup Overview
0011 * @{
0012 *
0013 * This file contains identifiers and low-level macros/functions for the Arasan
0014 * NAND flash controller driver.
0015 *
0016 * See xnandpsu.h for more information.
0017 *
0018 * @note     None
0019 *
0020 * <pre>
0021 * MODIFICATION HISTORY:
0022 *
0023 * Ver   Who    Date        Changes
0024 * ----- ----   ----------  -----------------------------------------------
0025 * 1.0   nm     05/06/2014  First Release
0026 * 2.0   sb     11/04/2014  Changed XNANDPSU_ECC_SLC_MLC_MASK to
0027 *              XNANDPSU_ECC_HAMMING_BCH_MASK.
0028 * 1.7   akm    09/03/20    Updated the Makefile to support parallel make
0029 *              execution.
0030 * </pre>
0031 *
0032 ******************************************************************************/
0033
0034 #ifndef XNANDPSU_HW_H       /* prevent circular inclusions */
0035 #define XNANDPSU_HW_H       /* by using protection macros */
0036
0037 #ifdef __cplusplus
0038 extern "C" {
0039 #endif
0040
0041 /***************************** Include Files *********************************/
0042 #ifndef __rtems__
0043 #include "xil_io.h"
0044 #else
0045 #include <bsp/xil-compat.h>
0046 #endif
0047
0048 /************************** Constant Definitions *****************************/
0049
0050 /************************** Register Offset Definitions **********************/
0051
0052 #define XNANDPSU_PKT_OFFSET     0x00U   /**< Packet Register */
0053 #define XNANDPSU_MEM_ADDR1_OFFSET   0x04U   /**< Memory Address
0054                           Register 1 */
0055 #define XNANDPSU_MEM_ADDR2_OFFSET   0x08U   /**< Memory Address
0056                           Register 2 */
0057 #define XNANDPSU_CMD_OFFSET     0x0CU   /**< Command Register */
0058 #define XNANDPSU_PROG_OFFSET        0x10U   /**< Program Register */
0059 #define XNANDPSU_INTR_STS_EN_OFFSET 0x14U   /**< Interrupt Status
0060                              Enable Register */
0061 #define XNANDPSU_INTR_SIG_EN_OFFSET 0x18U   /**< Interrupt Signal
0062                              Enable Register */
0063 #define XNANDPSU_INTR_STS_OFFSET    0x1CU   /**< Interrupt Status
0064                           Register */
0065 #define XNANDPSU_READY_BUSY_OFFSET  0x20U   /**< Ready/Busy status
0066                           Register */
0067 #define XNANDPSU_FLASH_STS_OFFSET   0x28U   /**< Flash Status Register */
0068 #define XNANDPSU_TIMING_OFFSET      0x2CU   /**< Timing Register */
0069 #define XNANDPSU_BUF_DATA_PORT_OFFSET   0x30U   /**< Buffer Data Port
0070                           Register */
0071 #define XNANDPSU_ECC_OFFSET     0x34U   /**< ECC Register */
0072 #define XNANDPSU_ECC_ERR_CNT_OFFSET 0x38U   /**< ECC Error Count
0073                           Register */
0074 #define XNANDPSU_ECC_SPR_CMD_OFFSET 0x3CU   /**< ECC Spare Command
0075                              Register */
0076 #define XNANDPSU_ECC_CNT_1BIT_OFFSET    0x40U   /**< Error Count 1bit
0077                           Register */
0078 #define XNANDPSU_ECC_CNT_2BIT_OFFSET    0x44U   /**< Error Count 2bit
0079                           Register */
0080 #define XNANDPSU_ECC_CNT_3BIT_OFFSET    0x48U   /**< Error Count 3bit
0081                           Register */
0082 #define XNANDPSU_ECC_CNT_4BIT_OFFSET    0x4CU   /**< Error Count 4bit
0083                           Register */
0084 #define XNANDPSU_CPU_REL_OFFSET     0x58U   /**< CPU Release Register */
0085 #define XNANDPSU_ECC_CNT_5BIT_OFFSET    0x5CU   /**< Error Count 5bit
0086                           Register */
0087 #define XNANDPSU_ECC_CNT_6BIT_OFFSET    0x60U   /**< Error Count 6bit
0088                           Register */
0089 #define XNANDPSU_ECC_CNT_7BIT_OFFSET    0x64U   /**< Error Count 7bit
0090                           Register */
0091 #define XNANDPSU_ECC_CNT_8BIT_OFFSET    0x68U   /**< Error Count 8bit
0092                           Register */
0093 #define XNANDPSU_DATA_INTF_OFFSET   0x6CU   /**< Data Interface Register */
0094 #define XNANDPSU_DMA_SYS_ADDR0_OFFSET   0x50U   /**< DMA System Address 0
0095                           Register */
0096 #define XNANDPSU_DMA_SYS_ADDR1_OFFSET   0x24U   /**< DMA System Address 1
0097                           Register */
0098 #define XNANDPSU_DMA_BUF_BND_OFFSET 0x54U   /**< DMA Buffer Boundary
0099                           Register */
0100 #define XNANDPSU_SLV_DMA_CONF_OFFSET    0x80U   /**< Slave DMA Configuration
0101                           Register */
0102
0103 /** @name Packet Register bit definitions and masks
0104  *  @{
0105  */
0106 #define XNANDPSU_PKT_PKT_SIZE_MASK      0x000007FFU /**< Packet Size */
0107 #define XNANDPSU_PKT_PKT_CNT_MASK       0x00FFF000U /**< Packet Count*/
0108 #define XNANDPSU_PKT_PKT_CNT_SHIFT      12U /**< Packet Count Shift */
0109 /* @} */
0110
0111 /** @name Memory Address Register 1 bit definitions and masks
0112  *  @{
0113  */
0114 #define XNANDPSU_MEM_ADDR1_COL_ADDR_MASK    0x0000FFFFU /**< Column Address
0115                                  Mask */
0116 #define XNANDPSU_MEM_ADDR1_PG_ADDR_MASK     0xFFFF0000U /**< Page, Block
0117                                  Address Mask */
0118 #define XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT    16U /**< Page Shift */
0119 /* @} */
0120
0121 /** @name Memory Address Register 2 bit definitions and masks
0122  *  @{
0123  */
0124 #define XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK    0x000000FFU /**< Memory Address
0125                                 */
0126 #define XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK   0x01000000U /**< Bus Width */
0127 #define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK    0x0E000000U /**< BCH Mode
0128                                  Value */
0129 #define XNANDPSU_MEM_ADDR2_MODE_MASK        0x30000000U /**< Flash
0130                                  Connection Mode */
0131 #define XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK    0xC0000000U /**< Chip Select */
0132 #define XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT   30U /**< Chip select
0133                             shift */
0134 #define XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT  24U /**< Bus width shift */
0135 #define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT   25U
0136 /* @} */
0137
0138 /** @name Command Register bit definitions and masks
0139  *  @{
0140  */
0141 #define XNANDPSU_CMD_CMD1_MASK          0x000000FFU /**< 1st Cycle
0142                                  Command */
0143 #define XNANDPSU_CMD_CMD2_MASK          0x0000FF00U /**< 2nd Cycle
0144                                  Command */
0145 #define XNANDPSU_CMD_PG_SIZE_MASK       0x03800000U /**< Page Size */
0146 #define XNANDPSU_CMD_DMA_EN_MASK        0x0C000000U /**< DMA Enable
0147                                  Mode */
0148 #define XNANDPSU_CMD_ADDR_CYCLES_MASK       0x70000000U /**< Number of
0149                                  Address Cycles */
0150 #define XNANDPSU_CMD_ECC_ON_MASK        0x80000000U /**< ECC ON/OFF */
0151 #define XNANDPSU_CMD_CMD2_SHIFT         8U /**< 2nd Cycle Command
0152                             Shift */
0153 #define XNANDPSU_CMD_PG_SIZE_SHIFT      23U /**< Page Size Shift */
0154 #define XNANDPSU_CMD_DMA_EN_SHIFT       26U /**< DMA Enable Shift */
0155 #define XNANDPSU_CMD_ADDR_CYCLES_SHIFT      28U /**< Number of Address
0156                              Cycles Shift */
0157 #define XNANDPSU_CMD_ECC_ON_SHIFT       31U /**< ECC ON/OFF */
0158 /* @} */
0159
0160 /** @name Program Register bit definitions and masks
0161  *  @{
0162  */
0163 #define XNANDPSU_PROG_RD_MASK           0x00000001U /**< Read */
0164 #define XNANDPSU_PROG_MUL_DIE_MASK      0x00000002U /**< Multi Die */
0165 #define XNANDPSU_PROG_BLK_ERASE_MASK        0x00000004U /**< Block Erase */
0166 #define XNANDPSU_PROG_RD_STS_MASK       0x00000008U /**< Read Status */
0167 #define XNANDPSU_PROG_PG_PROG_MASK      0x00000010U /**< Page Program */
0168 #define XNANDPSU_PROG_MUL_DIE_RD_MASK       0x00000020U /**< Multi Die Rd */
0169 #define XNANDPSU_PROG_RD_ID_MASK        0x00000040U /**< Read ID */
0170 #define XNANDPSU_PROG_RD_PRM_PG_MASK        0x00000080U /**< Read Param
0171                                  Page */
0172 #define XNANDPSU_PROG_RST_MASK          0x00000100U /**< Reset */
0173 #define XNANDPSU_PROG_GET_FEATURES_MASK     0x00000200U /**< Get Features */
0174 #define XNANDPSU_PROG_SET_FEATURES_MASK     0x00000400U /**< Set Features */
0175 #define XNANDPSU_PROG_RD_UNQ_ID_MASK        0x00000800U /**< Read Unique
0176                                  ID */
0177 #define XNANDPSU_PROG_RD_STS_ENH_MASK       0x00001000U /**< Read Status
0178                                  Enhanced */
0179 #define XNANDPSU_PROG_RD_INTRLVD_MASK       0x00002000U /**< Read
0180                                  Interleaved */
0181 #define XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK  0x00004000U /**< Change Read
0182                                 Column
0183                                 Enhanced */
0184 #define XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK    0x00008000U /**< Copy Back
0185                                 Interleaved */
0186 #define XNANDPSU_PROG_RD_CACHE_START_MASK   0x00010000U /**< Read Cache
0187                                  Start */
0188 #define XNANDPSU_PROG_RD_CACHE_SEQ_MASK     0x00020000U /**< Read Cache
0189                                  Sequential */
0190 #define XNANDPSU_PROG_RD_CACHE_RAND_MASK    0x00040000U /**< Read Cache
0191                                 Random */
0192 #define XNANDPSU_PROG_RD_CACHE_END_MASK     0x00080000U /**< Read Cache
0193                                  End */
0194 #define XNANDPSU_PROG_SMALL_DATA_MOVE_MASK  0x00100000U /**< Small Data
0195                                  Move */
0196 #define XNANDPSU_PROG_CHNG_ROW_ADDR_MASK    0x00200000U /**< Change Row
0197                                 Address */
0198 #define XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK    0x00400000U /**< Change Row
0199                                 Address End */
0200 #define XNANDPSU_PROG_RST_LUN_MASK      0x00800000U /**< Reset LUN */
0201 #define XNANDPSU_PROG_PGM_PG_CLR_MASK       0x01000000U /**< Enhanced
0202                                  Program Page
0203                                  Register Clear */
0204 #define XNANDPSU_PROG_VOL_SEL_MASK      0x02000000U /**< Volume Select */
0205 #define XNANDPSU_PROG_ODT_CONF_MASK     0x04000000U /**< ODT Configure */
0206 /* @} */
0207
0208 /** @name Interrupt Status Enable Register bit definitions and masks
0209  *  @{
0210  */
0211 #define XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK    0x00000001U /**< Buffer
0212                                      Write Ready
0213                                      Status
0214                                      Enable */
0215 #define XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK    0x00000002U /**< Buffer
0216                                      Read Ready
0217                                      Status
0218                                      Enable */
0219 #define XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer
0220                                      Complete
0221                                      Status
0222                                      Enable */
0223 #define XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK    0x00000008U /**< Multi
0224                                      Bit Error
0225                                      Status
0226                                      Enable */
0227 #define XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK   0x00000010U /**< Single
0228                                      Bit Error
0229                                      Status
0230                                      Enable,
0231                                      BCH Detect
0232                                      Error
0233                                      Status
0234                                      Enable */
0235 #define XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK    0x00000040U /**< DMA
0236                                      Status
0237                                      Enable */
0238 #define XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK    0x00000080U /**< Error
0239                                      AHB Status
0240                                      Enable */
0241 /* @} */
0242
0243 /** @name Interrupt Signal Enable Register bit definitions and masks
0244  *  @{
0245  */
0246 #define XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK    0x00000001U /**< Buffer
0247                                      Write Ready
0248                                      Signal
0249                                      Enable */
0250 #define XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK    0x00000002U /**< Buffer
0251                                      Read Ready
0252                                      Signal
0253                                      Enable */
0254 #define XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer
0255                                      Complete
0256                                      Signal
0257                                      Enable */
0258 #define XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK    0x00000008U /**< Multi
0259                                      Bit Error
0260                                      Signal
0261                                      Enable */
0262 #define XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK   0x00000010U /**< Single
0263                                      Bit Error
0264                                      Signal
0265                                      Enable,
0266                                      BCH Detect
0267                                      Error
0268                                      Signal
0269                                      Enable */
0270 #define XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK    0x00000040U /**< DMA
0271                                      Signal
0272                                      Enable */
0273 #define XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK    0x00000080U /**< Error
0274                                      AHB Signal
0275                                      Enable */
0276 /* @} */
0277
0278 /** @name Interrupt Status Register bit definitions and masks
0279  *  @{
0280  */
0281 #define XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK   0x00000001U /**< Buffer
0282                                      Write
0283                                      Ready */
0284 #define XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK   0x00000002U /**< Buffer
0285                                      Read
0286                                      Ready */
0287 #define XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK    0x00000004U /**< Transfer
0288                                      Complete */
0289 #define XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK   0x00000008U /**< Multi
0290                                     Bit Error */
0291 #define XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK      0x00000010U /**< Single
0292                                      Bit Error,
0293                                      BCH Detect
0294                                      Error */
0295 #define XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK       0x00000040U /**< DMA
0296                                      Interrupt
0297                                      */
0298 #define XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK       0x00000080U /**< Error
0299                                      AHB */
0300 /* @} */
0301
0302 /** @name Interrupt bit definitions and masks
0303  *  @{
0304  */
0305 #define XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK   0x00000001U /**< Buffer Write
0306                                 Ready Status
0307                                 Enable */
0308 #define XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK   0x00000002U /**< Buffer Read
0309                                 Ready Status
0310                                 Enable */
0311 #define XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK    0x00000004U /**< Transfer
0312                                 Complete Status
0313                                 Enable */
0314 #define XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK   0x00000008U /**< Multi Bit Error
0315                                 Status Enable */
0316 #define XNANDPSU_INTR_ERR_INTR_STS_EN_MASK  0x00000010U /**< Single Bit Error
0317                                 Status Enable,
0318                                 BCH Detect Error
0319                                 Status Enable */
0320 #define XNANDPSU_INTR_DMA_INT_STS_EN_MASK   0x00000040U /**< DMA Status
0321                                 Enable */
0322 #define XNANDPSU_INTR_ERR_AHB_STS_EN_MASK   0x00000080U /**< Error AHB Status
0323                                 Enable */
0324 /* @} */
0325
0326 /** @name ID2 Register bit definitions and masks
0327  *  @{
0328  */
0329 #define XNANDPSU_ID2_DEVICE_ID2_MASK        0x000000FFU /**< MSB Device ID */
0330 /* @} */
0331
0332 /** @name Flash Status Register bit definitions and masks
0333  *  @{
0334  */
0335 #define XNANDPSU_FLASH_STS_FLASH_STS_MASK   0x0000FFFFU /**< Flash Status
0336                                  Value */
0337 /* @} */
0338
0339 /** @name Timing Register bit definitions and masks
0340  *  @{
0341  */
0342 #define XNANDPSU_TIMING_TCCS_TIME_MASK      0x00000003U /**< Change column
0343                                  setup time */
0344 #define XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK 0x00000004U /**< Slow/Fast device
0345                                  */
0346 #define XNANDPSU_TIMING_DQS_BUFF_SEL_MASK   0x00000078U /**< Write/Read data
0347                                  transaction value
0348                                  */
0349 #define XNANDPSU_TIMING_TADL_TIME_MASK      0x00007F80U /**< Address latch
0350                                  enable to Data
0351                                  loading time */
0352 /* @} */
0353
0354 /** @name ECC Register bit definitions and masks
0355  *  @{
0356  */
0357 #define XNANDPSU_ECC_ADDR_MASK          0x0000FFFFU /**< ECC address */
0358 #define XNANDPSU_ECC_SIZE_MASK          0x01FF0000U /**< ECC size */
0359 #define XNANDPSU_ECC_HAMMING_BCH_MASK       0x02000000U /**< Hamming/BCH
0360                                  support */
0361 /* @} */
0362
0363 /** @name ECC Error Count Register bit definitions and masks
0364  *  @{
0365  */
0366 #define XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK   0x000000FFU /**< Packet
0367                                      bound error
0368                                      count */
0369 #define XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK    0x0000FF00U /**< Page
0370                                      bound error
0371                                      count */
0372 /* @} */
0373
0374 /** @name ECC Spare Command Register bit definitions and masks
0375  *  @{
0376  */
0377 #define XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK       0x000000FFU /**< ECC
0378                                      spare
0379                                      command */
0380 #define XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK   0x70000000U /**< Number
0381                                      of ECC/
0382                                      spare
0383                                      address
0384                                      cycles */
0385 /* @} */
0386
0387 /** @name Data Interface Register bit definitions and masks
0388  *  @{
0389  */
0390 #define XNANDPSU_DATA_INTF_SDR_MASK     0x00000007U /**< SDR mode */
0391 #define XNANDPSU_DATA_INTF_NVDDR_MASK       0x00000038U /**< NVDDR mode */
0392 #define XNANDPSU_DATA_INTF_NVDDR2_MASK      0x000001C0U /**< NVDDR2 mode */
0393 #define XNANDPSU_DATA_INTF_DATA_INTF_MASK   0x00000600U /**< Data
0394                                  Interface */
0395 #define XNANDPSU_DATA_INTF_NVDDR_SHIFT      3U /**< NVDDR mode shift */
0396 #define XNANDPSU_DATA_INTF_DATA_INTF_SHIFT  9U /**< Data Interface Shift */
0397 /* @} */
0398
0399 /** @name DMA Buffer Boundary Register bit definitions and masks
0400  *  @{
0401  */
0402 #define XNANDPSU_DMA_BUF_BND_BND_MASK       0x00000007U /**< DMA buffer
0403                                  boundary */
0404 #define XNANDPSU_DMA_BUF_BND_4K         0x0U
0405 #define XNANDPSU_DMA_BUF_BND_8K         0x1U
0406 #define XNANDPSU_DMA_BUF_BND_16K        0x2U
0407 #define XNANDPSU_DMA_BUF_BND_32K        0x3U
0408 #define XNANDPSU_DMA_BUF_BND_64K        0x4U
0409 #define XNANDPSU_DMA_BUF_BND_128K       0x5U
0410 #define XNANDPSU_DMA_BUF_BND_256K       0x6U
0411 #define XNANDPSU_DMA_BUF_BND_512K       0x7U
0412 /* @} */
0413
0414 /** @name Slave DMA Configuration Register bit definitions and masks
0415  *  @{
0416  */
0417 #define XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK       0x00000001U /**< Slave
0418                                      DMA
0419                                      Transfer
0420                                      Direction
0421                                      */
0422 #define XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK    0x001FFFFEU /**< Slave
0423                                      DMA
0424                                      Transfer
0425                                      Count */
0426 #define XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK   0x00E00000U /**< Slave
0427                                      DMA
0428                                      Burst
0429                                      Size */
0430 #define XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK    0x0F000000U /**< DMA
0431                                      Timeout
0432                                      Counter
0433                                      Value */
0434 #define XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK      0x10000000U /**< Slave
0435                                      DMA
0436                                      Enable */
0437 /* @} */
0438
0439 /**************************** Type Definitions *******************************/
0440
0441 /***************** Macros (Inline Functions) Definitions *********************/
0442
0443 /****************************************************************************/
0444 /**
0445 *
0446 * This macro reads the given register.
0447 *
0448 * @param    BaseAddress is the base address of controller registers.
0449 * @param    RegOffset is the register offset to be read.
0450 *
0451 * @return   The 32-bit value of the register.
0452 *
0453 * @note     C-style signature:
0454 *       u32 XNandPsu_ReadReg(u32 BaseAddress, u32 RegOffset)
0455 *
0456 *****************************************************************************/
0457 #define XNandPsu_ReadReg(BaseAddress, RegOffset)            \
0458             Xil_In32((BaseAddress) + (RegOffset))
0459
0460 /****************************************************************************/
0461 /**
0462 *
0463 * This macro writes the given register.
0464 *
0465 * @param    BaseAddress is the the base address of controller registers.
0466 * @param    RegOffset is the register offset to be written.
0467 * @param    Data is the the 32-bit value to write to the register.
0468 *
0469 * @return   None.
0470 *
0471 * @note     C-style signature:
0472 *       void XNandPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
0473 *
0474 ******************************************************************************/
0475 #define XNandPsu_WriteReg(BaseAddress, RegOffset, Data)         \
0476             Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
0477
0478 /************************** Function Prototypes ******************************/
0479
0480 /************************** Variable Definitions *****************************/
0481
0482 #ifdef __cplusplus
0483 }
0484 #endif
0485
0486 #endif /* XNANDPSU_HW_H end of protection macro */
0487 /** @} */