dev/irq/arm-gic-tm27.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup DevIRQGIC
0007  *
0008  * @brief This header file provides the TM27 support for the ARM Generic
0009  *   Interrupt Controller (GIC).
0010  */
0011
0012 /*
0013  * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifndef _RTEMS_TMTEST27
0038 #error "This is an RTEMS internal file you must not include directly."
0039 #endif
0040
0041 #ifndef LIBBSP_ARM_SHARED_ARM_GIC_TM27_H
0042 #define LIBBSP_ARM_SHARED_ARM_GIC_TM27_H
0043
0044 #include <bsp.h>
0045 #include <bsp/irq.h>
0046
0047 #include <rtems/score/assert.h>
0048
0049 #define MUST_WAIT_FOR_INTERRUPT 1
0050
0051 #ifndef ARM_GIC_TM27_IRQ_LOW
0052 #define ARM_GIC_TM27_IRQ_LOW ARM_GIC_IRQ_SGI_12
0053 #endif
0054
0055 #ifndef ARM_GIC_TM27_IRQ_HIGH
0056 #define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_13
0057 #endif
0058
0059 #define TM27_INTERRUPT_VECTOR_DEFAULT ARM_GIC_TM27_IRQ_LOW
0060
0061 #define ARM_GIC_TM27_PRIO_LOW 0x80
0062
0063 #define ARM_GIC_TM27_PRIO_HIGH 0x00
0064
0065 static inline void Install_tm27_vector( rtems_interrupt_handler handler )
0066 {
0067   static rtems_interrupt_entry entry_low;
0068   static rtems_interrupt_entry entry_high;
0069   rtems_status_code sc;
0070
0071   rtems_interrupt_entry_initialize(
0072     &entry_low,
0073     handler,
0074     NULL,
0075     "tm27 low"
0076   );
0077   sc = rtems_interrupt_entry_install(
0078     ARM_GIC_TM27_IRQ_LOW,
0079     RTEMS_INTERRUPT_UNIQUE,
0080     &entry_low
0081   );
0082   _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
0083
0084   sc = rtems_interrupt_set_priority(
0085     ARM_GIC_TM27_IRQ_LOW,
0086     ARM_GIC_TM27_PRIO_LOW
0087   );
0088   _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
0089
0090   rtems_interrupt_entry_initialize(
0091     &entry_high,
0092     handler,
0093     NULL,
0094     "tm27 high"
0095   );
0096   sc = rtems_interrupt_entry_install(
0097     ARM_GIC_TM27_IRQ_HIGH,
0098     RTEMS_INTERRUPT_UNIQUE,
0099     &entry_high
0100   );
0101   _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
0102
0103   sc = rtems_interrupt_set_priority(
0104     ARM_GIC_TM27_IRQ_HIGH,
0105     ARM_GIC_TM27_PRIO_HIGH
0106   );
0107   _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
0108 }
0109
0110 static inline void Cause_tm27_intr(void)
0111 {
0112   rtems_status_code sc;
0113
0114   sc = rtems_interrupt_raise_on(
0115     ARM_GIC_TM27_IRQ_LOW,
0116     _SMP_Get_current_processor()
0117   );
0118   _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
0119 }
0120
0121 static inline void Clear_tm27_intr(void)
0122 {
0123   /* Nothing to do */
0124 }
0125
0126 static inline void Lower_tm27_intr(void)
0127 {
0128   rtems_status_code sc;
0129
0130   sc = rtems_interrupt_raise_on(
0131     ARM_GIC_TM27_IRQ_HIGH,
0132     _SMP_Get_current_processor()
0133   );
0134   _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
0135 }
0136
0137 #endif /* LIBBSP_ARM_SHARED_ARM_GIC_TM27_H */